1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 8/17/2017 22 // User Name:gunjans 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __WFSS_CE_REG_SEQ_REG_H__ 29 #define __WFSS_CE_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "wfss_ce_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block WFSS_CE_CHANNEL_DST_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB //// 45 46 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) (x+0x00000000) 47 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) (x+0x00000000) 48 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 49 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_SHFT 0 50 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ 51 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 52 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, mask) \ 53 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) 54 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, val) \ 55 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), val) 56 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 64 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 65 66 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB //// 67 68 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) (x+0x00000004) 69 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) (x+0x00000004) 70 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0x00ffffff 71 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_SHFT 0 72 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ 73 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 74 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, mask) \ 75 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) 76 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, val) \ 77 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), val) 78 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x, mask, val) \ 79 do {\ 80 HWIO_INTLOCK(); \ 81 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)); \ 82 HWIO_INTFREE();\ 83 } while (0) 84 85 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 86 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 87 88 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 89 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 90 91 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID //// 92 93 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) (x+0x00000008) 94 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) (x+0x00000008) 95 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x000000ff 96 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT 0 97 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ 98 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 99 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, mask) \ 100 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) 101 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, val) \ 102 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), val) 103 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x, mask, val) \ 104 do {\ 105 HWIO_INTLOCK(); \ 106 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)); \ 107 HWIO_INTFREE();\ 108 } while (0) 109 110 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 111 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 112 113 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS //// 114 115 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) (x+0x0000000c) 116 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) (x+0x0000000c) 117 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 118 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_SHFT 0 119 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ 120 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 121 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, mask) \ 122 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) 123 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUT(x, val) \ 124 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), val) 125 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUTM(x, mask, val) \ 126 do {\ 127 HWIO_INTLOCK(); \ 128 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)); \ 129 HWIO_INTFREE();\ 130 } while (0) 131 132 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 133 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 134 135 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 136 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 137 138 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC //// 139 140 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) (x+0x00000010) 141 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) (x+0x00000010) 142 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x003fffff 143 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SHFT 0 144 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ 145 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 146 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, mask) \ 147 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) 148 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, val) \ 149 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), val) 150 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x, mask, val) \ 151 do {\ 152 HWIO_INTLOCK(); \ 153 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)); \ 154 HWIO_INTFREE();\ 155 } while (0) 156 157 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 158 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 159 160 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 161 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 162 163 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 164 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 165 166 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 167 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 168 169 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 170 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 171 172 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 173 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 174 175 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 176 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 177 178 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 179 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 180 181 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x00000004 182 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 183 184 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 185 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 186 187 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 188 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 189 190 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB //// 191 192 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) 193 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) 194 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 195 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_SHFT 0 196 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ 197 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 198 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, mask) \ 199 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) 200 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, val) \ 201 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), val) 202 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 203 do {\ 204 HWIO_INTLOCK(); \ 205 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)); \ 206 HWIO_INTFREE();\ 207 } while (0) 208 209 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 210 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 211 212 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB //// 213 214 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) 215 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) 216 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0x000000ff 217 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_SHFT 0 218 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ 219 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 220 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, mask) \ 221 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) 222 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, val) \ 223 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), val) 224 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 225 do {\ 226 HWIO_INTLOCK(); \ 227 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)); \ 228 HWIO_INTFREE();\ 229 } while (0) 230 231 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 232 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 233 234 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0 //// 235 236 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) 237 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) 238 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 239 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 240 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 241 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 242 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 243 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 244 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 245 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 246 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 247 do {\ 248 HWIO_INTLOCK(); \ 249 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 250 HWIO_INTFREE();\ 251 } while (0) 252 253 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 254 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 255 256 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 257 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 258 259 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 260 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 261 262 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1 //// 263 264 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) 265 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) 266 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 267 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 268 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 269 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 270 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 271 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 272 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 273 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 274 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 275 do {\ 276 HWIO_INTLOCK(); \ 277 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 278 HWIO_INTFREE();\ 279 } while (0) 280 281 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 282 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 283 284 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS //// 285 286 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) 287 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) 288 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 289 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_SHFT 0 290 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ 291 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 292 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 293 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 294 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 295 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), val) 296 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 297 do {\ 298 HWIO_INTLOCK(); \ 299 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x)); \ 300 HWIO_INTFREE();\ 301 } while (0) 302 303 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 304 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 305 306 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 307 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 308 309 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 310 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 311 312 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER //// 313 314 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) 315 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) 316 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 317 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 318 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 319 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 320 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 321 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 322 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 323 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 324 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 325 do {\ 326 HWIO_INTLOCK(); \ 327 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 328 HWIO_INTFREE();\ 329 } while (0) 330 331 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 332 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 333 334 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER //// 335 336 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) 337 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) 338 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 339 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 340 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 341 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 342 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 343 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 344 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 345 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 346 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 347 do {\ 348 HWIO_INTLOCK(); \ 349 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 350 HWIO_INTFREE();\ 351 } while (0) 352 353 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 354 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 355 356 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS //// 357 358 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) 359 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) 360 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 361 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 362 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 363 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 364 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 365 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 366 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 367 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 368 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 369 do {\ 370 HWIO_INTLOCK(); \ 371 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 372 HWIO_INTFREE();\ 373 } while (0) 374 375 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 376 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 377 378 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 379 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 380 381 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB //// 382 383 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) 384 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) 385 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 386 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_SHFT 0 387 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ 388 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 389 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, mask) \ 390 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) 391 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, val) \ 392 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), val) 393 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 394 do {\ 395 HWIO_INTLOCK(); \ 396 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)); \ 397 HWIO_INTFREE();\ 398 } while (0) 399 400 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 401 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 402 403 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB //// 404 405 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) 406 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) 407 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x000001ff 408 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_SHFT 0 409 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ 410 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 411 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, mask) \ 412 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) 413 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, val) \ 414 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), val) 415 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 416 do {\ 417 HWIO_INTLOCK(); \ 418 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)); \ 419 HWIO_INTFREE();\ 420 } while (0) 421 422 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 423 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 424 425 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 426 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 427 428 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA //// 429 430 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) (x+0x00000050) 431 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) (x+0x00000050) 432 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 433 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_SHFT 0 434 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ 435 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 436 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, mask) \ 437 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) 438 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, val) \ 439 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), val) 440 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x, mask, val) \ 441 do {\ 442 HWIO_INTLOCK(); \ 443 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)); \ 444 HWIO_INTFREE();\ 445 } while (0) 446 447 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 448 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 449 450 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET //// 451 452 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) 453 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) 454 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 455 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT 0 456 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ 457 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 458 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 459 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 460 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 461 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), val) 462 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 463 do {\ 464 HWIO_INTLOCK(); \ 465 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)); \ 466 HWIO_INTFREE();\ 467 } while (0) 468 469 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 470 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 471 472 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB //// 473 474 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000058) 475 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000058) 476 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 477 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_SHFT 0 478 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ 479 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 480 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, mask) \ 481 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) 482 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, val) \ 483 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), val) 484 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 485 do {\ 486 HWIO_INTLOCK(); \ 487 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)); \ 488 HWIO_INTFREE();\ 489 } while (0) 490 491 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 492 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 493 494 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB //// 495 496 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) (x+0x0000005c) 497 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) (x+0x0000005c) 498 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 499 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_SHFT 0 500 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ 501 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 502 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, mask) \ 503 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) 504 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, val) \ 505 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), val) 506 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 507 do {\ 508 HWIO_INTLOCK(); \ 509 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)); \ 510 HWIO_INTFREE();\ 511 } while (0) 512 513 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 514 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 515 516 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 517 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 518 519 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID //// 520 521 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) (x+0x00000060) 522 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) (x+0x00000060) 523 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0x0000ffff 524 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_SHFT 0 525 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ 526 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 527 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, mask) \ 528 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) 529 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, val) \ 530 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), val) 531 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x, mask, val) \ 532 do {\ 533 HWIO_INTLOCK(); \ 534 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)); \ 535 HWIO_INTFREE();\ 536 } while (0) 537 538 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 539 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 540 541 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 542 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 543 544 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS //// 545 546 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) (x+0x00000064) 547 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) (x+0x00000064) 548 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 549 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_SHFT 0 550 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ 551 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 552 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, mask) \ 553 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) 554 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUT(x, val) \ 555 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), val) 556 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUTM(x, mask, val) \ 557 do {\ 558 HWIO_INTLOCK(); \ 559 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)); \ 560 HWIO_INTFREE();\ 561 } while (0) 562 563 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 564 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 565 566 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 567 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 568 569 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC //// 570 571 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) (x+0x00000068) 572 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) (x+0x00000068) 573 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x03ffffff 574 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SHFT 0 575 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ 576 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 577 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, mask) \ 578 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) 579 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, val) \ 580 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), val) 581 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x, mask, val) \ 582 do {\ 583 HWIO_INTLOCK(); \ 584 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)); \ 585 HWIO_INTFREE();\ 586 } while (0) 587 588 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000 589 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 590 591 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 592 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 593 594 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 595 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 596 597 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 598 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 599 600 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 601 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 602 603 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 604 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 605 606 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 607 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 608 609 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 610 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 611 612 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 613 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 614 615 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 616 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 617 618 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 619 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 620 621 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 622 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 623 624 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB //// 625 626 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000006c) 627 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000006c) 628 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 629 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_SHFT 0 630 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ 631 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 632 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 633 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 634 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 635 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 636 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 637 do {\ 638 HWIO_INTLOCK(); \ 639 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 640 HWIO_INTFREE();\ 641 } while (0) 642 643 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 644 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 645 646 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB //// 647 648 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000070) 649 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000070) 650 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 651 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_SHFT 0 652 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ 653 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 654 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 655 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 656 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 657 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 658 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 659 do {\ 660 HWIO_INTLOCK(); \ 661 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 662 HWIO_INTFREE();\ 663 } while (0) 664 665 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 666 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 667 668 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP //// 669 670 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000007c) 671 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000007c) 672 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 673 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 674 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 675 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 676 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 677 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 678 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 679 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 680 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 681 do {\ 682 HWIO_INTLOCK(); \ 683 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 684 HWIO_INTFREE();\ 685 } while (0) 686 687 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 688 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 689 690 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 691 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 692 693 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 694 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 695 696 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS //// 697 698 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000080) 699 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000080) 700 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 701 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 702 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 703 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 704 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 705 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 706 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 707 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 708 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 709 do {\ 710 HWIO_INTLOCK(); \ 711 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 712 HWIO_INTFREE();\ 713 } while (0) 714 715 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 716 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 717 718 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 719 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 720 721 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 722 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 723 724 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER //// 725 726 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084) 727 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084) 728 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 729 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 730 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 731 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 732 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 733 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 734 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 735 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 736 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 737 do {\ 738 HWIO_INTLOCK(); \ 739 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 740 HWIO_INTFREE();\ 741 } while (0) 742 743 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 744 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 745 746 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB //// 747 748 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000a0) 749 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000a0) 750 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 751 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_SHFT 0 752 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 753 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 754 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 755 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 756 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 757 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 758 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 759 do {\ 760 HWIO_INTLOCK(); \ 761 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 762 HWIO_INTFREE();\ 763 } while (0) 764 765 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 766 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 767 768 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB //// 769 770 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000a4) 771 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000a4) 772 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 773 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_SHFT 0 774 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 775 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 776 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 777 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 778 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 779 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 780 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 781 do {\ 782 HWIO_INTLOCK(); \ 783 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 784 HWIO_INTFREE();\ 785 } while (0) 786 787 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 788 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 789 790 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 791 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 792 793 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA //// 794 795 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000000a8) 796 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000000a8) 797 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 798 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_SHFT 0 799 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ 800 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 801 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, mask) \ 802 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) 803 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, val) \ 804 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), val) 805 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 806 do {\ 807 HWIO_INTLOCK(); \ 808 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)); \ 809 HWIO_INTFREE();\ 810 } while (0) 811 812 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 813 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 814 815 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET //// 816 817 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac) 818 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac) 819 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 820 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 821 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 822 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 823 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 824 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 825 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 826 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 827 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 828 do {\ 829 HWIO_INTLOCK(); \ 830 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 831 HWIO_INTFREE();\ 832 } while (0) 833 834 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 835 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 836 837 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL //// 838 839 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) (x+0x000000b0) 840 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) (x+0x000000b0) 841 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x0001ffff 842 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_SHFT 0 843 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ 844 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 845 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, mask) \ 846 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) 847 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, val) \ 848 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), val) 849 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x, mask, val) \ 850 do {\ 851 HWIO_INTLOCK(); \ 852 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)); \ 853 HWIO_INTFREE();\ 854 } while (0) 855 856 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x00010000 857 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 858 859 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff 860 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 861 862 //// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS //// 863 864 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) (x+0x000000b4) 865 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) (x+0x000000b4) 866 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x0000003f 867 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_SHFT 0 868 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ 869 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 870 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, mask) \ 871 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) 872 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, val) \ 873 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), val) 874 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x, mask, val) \ 875 do {\ 876 HWIO_INTLOCK(); \ 877 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)); \ 878 HWIO_INTFREE();\ 879 } while (0) 880 881 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x00000020 882 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 883 884 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x00000010 885 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 886 887 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x00000008 888 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 889 890 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x00000004 891 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 892 893 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x00000002 894 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 895 896 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x00000001 897 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 898 899 //// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2 //// 900 901 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) (x+0x000000b8) 902 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) (x+0x000000b8) 903 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0x0000000f 904 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_SHFT 0 905 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ 906 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 907 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, mask) \ 908 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) 909 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, val) \ 910 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), val) 911 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x, mask, val) \ 912 do {\ 913 HWIO_INTLOCK(); \ 914 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)); \ 915 HWIO_INTFREE();\ 916 } while (0) 917 918 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x00000008 919 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 920 921 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x00000004 922 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 923 924 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x00000002 925 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 926 927 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x00000001 928 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 929 930 //// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP //// 931 932 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) (x+0x00000400) 933 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) (x+0x00000400) 934 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0x0000ffff 935 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_SHFT 0 936 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ 937 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 938 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, mask) \ 939 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) 940 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, val) \ 941 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), val) 942 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x, mask, val) \ 943 do {\ 944 HWIO_INTLOCK(); \ 945 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)); \ 946 HWIO_INTFREE();\ 947 } while (0) 948 949 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0x0000ffff 950 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 951 952 //// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP //// 953 954 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) (x+0x00000404) 955 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) (x+0x00000404) 956 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0x0000ffff 957 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_SHFT 0 958 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ 959 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 960 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, mask) \ 961 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) 962 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, val) \ 963 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), val) 964 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x, mask, val) \ 965 do {\ 966 HWIO_INTLOCK(); \ 967 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)); \ 968 HWIO_INTFREE();\ 969 } while (0) 970 971 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0x0000ffff 972 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 973 974 //// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP //// 975 976 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) (x+0x00000408) 977 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) (x+0x00000408) 978 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0x0000ffff 979 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_SHFT 0 980 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ 981 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 982 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, mask) \ 983 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) 984 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, val) \ 985 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), val) 986 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x, mask, val) \ 987 do {\ 988 HWIO_INTLOCK(); \ 989 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)); \ 990 HWIO_INTFREE();\ 991 } while (0) 992 993 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 994 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 995 996 //// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP //// 997 998 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) (x+0x0000040c) 999 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) (x+0x0000040c) 1000 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0x0000ffff 1001 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_SHFT 0 1002 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ 1003 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 1004 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, mask) \ 1005 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) 1006 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, val) \ 1007 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), val) 1008 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x, mask, val) \ 1009 do {\ 1010 HWIO_INTLOCK(); \ 1011 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)); \ 1012 HWIO_INTFREE();\ 1013 } while (0) 1014 1015 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 1016 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 1017 1018 1019 /////////////////////////////////////////////////////////////////////////////////////////////// 1020 // Register Data for Block WFSS_CE_CHANNEL_SRC_REG 1021 /////////////////////////////////////////////////////////////////////////////////////////////// 1022 1023 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB //// 1024 1025 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) (x+0x00000000) 1026 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) (x+0x00000000) 1027 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 1028 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_SHFT 0 1029 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ 1030 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 1031 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, mask) \ 1032 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) 1033 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, val) \ 1034 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), val) 1035 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x, mask, val) \ 1036 do {\ 1037 HWIO_INTLOCK(); \ 1038 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)); \ 1039 HWIO_INTFREE();\ 1040 } while (0) 1041 1042 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1043 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1044 1045 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB //// 1046 1047 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) (x+0x00000004) 1048 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) (x+0x00000004) 1049 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0x00ffffff 1050 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_SHFT 0 1051 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ 1052 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 1053 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, mask) \ 1054 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) 1055 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, val) \ 1056 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), val) 1057 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x, mask, val) \ 1058 do {\ 1059 HWIO_INTLOCK(); \ 1060 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)); \ 1061 HWIO_INTFREE();\ 1062 } while (0) 1063 1064 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1065 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1066 1067 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1068 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1069 1070 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID //// 1071 1072 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) (x+0x00000008) 1073 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) (x+0x00000008) 1074 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x000000ff 1075 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT 0 1076 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ 1077 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 1078 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, mask) \ 1079 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) 1080 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, val) \ 1081 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), val) 1082 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x, mask, val) \ 1083 do {\ 1084 HWIO_INTLOCK(); \ 1085 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)); \ 1086 HWIO_INTFREE();\ 1087 } while (0) 1088 1089 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1090 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 1091 1092 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS //// 1093 1094 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) (x+0x0000000c) 1095 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) (x+0x0000000c) 1096 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 1097 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_SHFT 0 1098 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ 1099 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 1100 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, mask) \ 1101 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) 1102 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUT(x, val) \ 1103 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), val) 1104 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUTM(x, mask, val) \ 1105 do {\ 1106 HWIO_INTLOCK(); \ 1107 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)); \ 1108 HWIO_INTFREE();\ 1109 } while (0) 1110 1111 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1112 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1113 1114 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1115 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1116 1117 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC //// 1118 1119 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) (x+0x00000010) 1120 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) (x+0x00000010) 1121 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x003fffff 1122 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SHFT 0 1123 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ 1124 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 1125 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, mask) \ 1126 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) 1127 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, val) \ 1128 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), val) 1129 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x, mask, val) \ 1130 do {\ 1131 HWIO_INTLOCK(); \ 1132 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)); \ 1133 HWIO_INTFREE();\ 1134 } while (0) 1135 1136 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1137 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 1138 1139 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1140 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1141 1142 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1143 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1144 1145 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1146 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1147 1148 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1149 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 1150 1151 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1152 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1153 1154 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1155 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1156 1157 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1158 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1159 1160 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1161 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 1162 1163 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1164 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1165 1166 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1167 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1168 1169 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB //// 1170 1171 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) 1172 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) 1173 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 1174 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_SHFT 0 1175 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ 1176 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 1177 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, mask) \ 1178 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) 1179 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, val) \ 1180 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), val) 1181 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1182 do {\ 1183 HWIO_INTLOCK(); \ 1184 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)); \ 1185 HWIO_INTFREE();\ 1186 } while (0) 1187 1188 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1189 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1190 1191 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB //// 1192 1193 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) 1194 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) 1195 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0x000000ff 1196 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_SHFT 0 1197 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ 1198 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 1199 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, mask) \ 1200 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) 1201 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, val) \ 1202 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), val) 1203 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1204 do {\ 1205 HWIO_INTLOCK(); \ 1206 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)); \ 1207 HWIO_INTFREE();\ 1208 } while (0) 1209 1210 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1211 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1212 1213 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0 //// 1214 1215 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) 1216 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) 1217 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1218 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1219 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1220 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1221 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1222 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1223 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1224 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1225 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1226 do {\ 1227 HWIO_INTLOCK(); \ 1228 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1229 HWIO_INTFREE();\ 1230 } while (0) 1231 1232 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1233 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1234 1235 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1236 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1237 1238 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1239 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1240 1241 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1 //// 1242 1243 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) 1244 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) 1245 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1246 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1247 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1248 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1249 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1250 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1251 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1252 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1253 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1254 do {\ 1255 HWIO_INTLOCK(); \ 1256 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1257 HWIO_INTFREE();\ 1258 } while (0) 1259 1260 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1261 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1262 1263 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS //// 1264 1265 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) 1266 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) 1267 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1268 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_SHFT 0 1269 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ 1270 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 1271 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1272 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1273 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1274 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1275 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1276 do {\ 1277 HWIO_INTLOCK(); \ 1278 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x)); \ 1279 HWIO_INTFREE();\ 1280 } while (0) 1281 1282 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1283 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1284 1285 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1286 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1287 1288 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1289 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1290 1291 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER //// 1292 1293 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) 1294 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) 1295 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1296 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1297 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1298 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1299 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1300 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1301 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1302 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1303 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1304 do {\ 1305 HWIO_INTLOCK(); \ 1306 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1307 HWIO_INTFREE();\ 1308 } while (0) 1309 1310 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1311 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1312 1313 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER //// 1314 1315 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) 1316 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) 1317 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1318 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1319 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1320 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1321 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1322 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1323 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1324 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1325 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1326 do {\ 1327 HWIO_INTLOCK(); \ 1328 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1329 HWIO_INTFREE();\ 1330 } while (0) 1331 1332 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1333 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1334 1335 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS //// 1336 1337 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) 1338 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) 1339 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1340 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1341 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1342 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1343 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1344 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1345 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1346 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1347 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1348 do {\ 1349 HWIO_INTLOCK(); \ 1350 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1351 HWIO_INTFREE();\ 1352 } while (0) 1353 1354 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1355 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1356 1357 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1358 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1359 1360 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB //// 1361 1362 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) 1363 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) 1364 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1365 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_SHFT 0 1366 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ 1367 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 1368 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, mask) \ 1369 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) 1370 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, val) \ 1371 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), val) 1372 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1373 do {\ 1374 HWIO_INTLOCK(); \ 1375 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)); \ 1376 HWIO_INTFREE();\ 1377 } while (0) 1378 1379 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1380 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1381 1382 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB //// 1383 1384 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) 1385 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) 1386 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1387 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_SHFT 0 1388 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ 1389 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 1390 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, mask) \ 1391 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) 1392 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, val) \ 1393 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), val) 1394 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1395 do {\ 1396 HWIO_INTLOCK(); \ 1397 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)); \ 1398 HWIO_INTFREE();\ 1399 } while (0) 1400 1401 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1402 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1403 1404 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1405 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1406 1407 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA //// 1408 1409 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) (x+0x00000050) 1410 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) (x+0x00000050) 1411 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 1412 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_SHFT 0 1413 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ 1414 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 1415 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, mask) \ 1416 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) 1417 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, val) \ 1418 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), val) 1419 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x, mask, val) \ 1420 do {\ 1421 HWIO_INTLOCK(); \ 1422 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)); \ 1423 HWIO_INTFREE();\ 1424 } while (0) 1425 1426 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1427 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 1428 1429 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET //// 1430 1431 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) 1432 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) 1433 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1434 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT 0 1435 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ 1436 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 1437 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1438 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1439 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1440 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1441 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1442 do {\ 1443 HWIO_INTLOCK(); \ 1444 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)); \ 1445 HWIO_INTFREE();\ 1446 } while (0) 1447 1448 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1449 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1450 1451 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL //// 1452 1453 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) (x+0x00000058) 1454 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) (x+0x00000058) 1455 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x0000001f 1456 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SHFT 0 1457 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ 1458 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 1459 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, mask) \ 1460 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) 1461 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, val) \ 1462 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), val) 1463 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x, mask, val) \ 1464 do {\ 1465 HWIO_INTLOCK(); \ 1466 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)); \ 1467 HWIO_INTFREE();\ 1468 } while (0) 1469 1470 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x00000010 1471 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 1472 1473 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x00000008 1474 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 1475 1476 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x00000004 1477 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 1478 1479 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x00000002 1480 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 1481 1482 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x00000001 1483 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 1484 1485 //// Register WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS //// 1486 1487 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) (x+0x0000005c) 1488 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) (x+0x0000005c) 1489 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x0000001f 1490 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SHFT 0 1491 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ 1492 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 1493 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, mask) \ 1494 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) 1495 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, val) \ 1496 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), val) 1497 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x, mask, val) \ 1498 do {\ 1499 HWIO_INTLOCK(); \ 1500 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)); \ 1501 HWIO_INTFREE();\ 1502 } while (0) 1503 1504 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x00000010 1505 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 1506 1507 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x00000008 1508 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 1509 1510 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x00000004 1511 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 1512 1513 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x00000002 1514 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 1515 1516 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x00000001 1517 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 1518 1519 //// Register WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG //// 1520 1521 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) (x+0x00000060) 1522 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) (x+0x00000060) 1523 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 1524 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_SHFT 0 1525 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ 1526 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 1527 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, mask) \ 1528 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) 1529 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, val) \ 1530 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), val) 1531 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x, mask, val) \ 1532 do {\ 1533 HWIO_INTLOCK(); \ 1534 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)); \ 1535 HWIO_INTFREE();\ 1536 } while (0) 1537 1538 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 1539 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 1540 1541 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0x0000ffff 1542 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 1543 1544 //// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP //// 1545 1546 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) (x+0x00000400) 1547 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) (x+0x00000400) 1548 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0x0000ffff 1549 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_SHFT 0 1550 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ 1551 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 1552 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, mask) \ 1553 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) 1554 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, val) \ 1555 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), val) 1556 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x, mask, val) \ 1557 do {\ 1558 HWIO_INTLOCK(); \ 1559 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)); \ 1560 HWIO_INTFREE();\ 1561 } while (0) 1562 1563 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0x0000ffff 1564 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 1565 1566 //// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP //// 1567 1568 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) (x+0x00000404) 1569 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) (x+0x00000404) 1570 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0x0000ffff 1571 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_SHFT 0 1572 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ 1573 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 1574 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, mask) \ 1575 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) 1576 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, val) \ 1577 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), val) 1578 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x, mask, val) \ 1579 do {\ 1580 HWIO_INTLOCK(); \ 1581 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)); \ 1582 HWIO_INTFREE();\ 1583 } while (0) 1584 1585 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0x0000ffff 1586 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 1587 1588 1589 /////////////////////////////////////////////////////////////////////////////////////////////// 1590 // Register Data for Block WFSS_CE_COMMON_REG 1591 /////////////////////////////////////////////////////////////////////////////////////////////// 1592 1593 //// Register WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER //// 1594 1595 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) (x+0x00000000) 1596 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) (x+0x00000000) 1597 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff 1598 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_SHFT 0 1599 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ 1600 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) 1601 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, mask) \ 1602 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) 1603 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUT(x, val) \ 1604 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), val) 1605 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUTM(x, mask, val) \ 1606 do {\ 1607 HWIO_INTLOCK(); \ 1608 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)); \ 1609 HWIO_INTFREE();\ 1610 } while (0) 1611 1612 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 1613 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 1614 1615 //// Register WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER //// 1616 1617 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) (x+0x00000004) 1618 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) (x+0x00000004) 1619 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0x000000ff 1620 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_SHFT 0 1621 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ 1622 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) 1623 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, mask) \ 1624 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) 1625 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUT(x, val) \ 1626 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), val) 1627 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUTM(x, mask, val) \ 1628 do {\ 1629 HWIO_INTLOCK(); \ 1630 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)); \ 1631 HWIO_INTFREE();\ 1632 } while (0) 1633 1634 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 1635 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 1636 1637 //// Register WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0 //// 1638 1639 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) (x+0x00000008) 1640 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) (x+0x00000008) 1641 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0x00000fff 1642 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SHFT 0 1643 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ 1644 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) 1645 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, mask) \ 1646 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) 1647 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUT(x, val) \ 1648 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), val) 1649 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUTM(x, mask, val) \ 1650 do {\ 1651 HWIO_INTLOCK(); \ 1652 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)); \ 1653 HWIO_INTFREE();\ 1654 } while (0) 1655 1656 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 1657 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 1658 1659 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 1660 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 1661 1662 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 1663 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 1664 1665 //// Register WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK //// 1666 1667 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000000c) 1668 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000000c) 1669 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x00000001 1670 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_SHFT 0 1671 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ 1672 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) 1673 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, mask) \ 1674 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) 1675 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, val) \ 1676 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), val) 1677 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 1678 do {\ 1679 HWIO_INTLOCK(); \ 1680 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)); \ 1681 HWIO_INTFREE();\ 1682 } while (0) 1683 1684 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 1685 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 1686 1687 //// Register WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE //// 1688 1689 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000010) 1690 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000010) 1691 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff 1692 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SHFT 0 1693 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ 1694 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) 1695 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, mask) \ 1696 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) 1697 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, val) \ 1698 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), val) 1699 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 1700 do {\ 1701 HWIO_INTLOCK(); \ 1702 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)); \ 1703 HWIO_INTFREE();\ 1704 } while (0) 1705 1706 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 1707 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 1708 1709 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 1710 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 1711 1712 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 1713 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 1714 1715 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 1716 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 1717 1718 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 1719 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 1720 1721 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 1722 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 1723 1724 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 1725 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 1726 1727 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 1728 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 1729 1730 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 1731 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 1732 1733 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 1734 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 1735 1736 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 1737 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 1738 1739 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 1740 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 1741 1742 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 1743 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 1744 1745 //// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS //// 1746 1747 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) (x+0x00000014) 1748 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) (x+0x00000014) 1749 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x01010101 1750 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_SHFT 0 1751 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ 1752 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) 1753 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, mask) \ 1754 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) 1755 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUT(x, val) \ 1756 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), val) 1757 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUTM(x, mask, val) \ 1758 do {\ 1759 HWIO_INTLOCK(); \ 1760 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)); \ 1761 HWIO_INTFREE();\ 1762 } while (0) 1763 1764 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 1765 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 1766 1767 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 1768 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 1769 1770 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 1771 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 1772 1773 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 1774 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 1775 1776 //// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS //// 1777 1778 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) (x+0x00000018) 1779 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) (x+0x00000018) 1780 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x003f3f3f 1781 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_SHFT 0 1782 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ 1783 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) 1784 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, mask) \ 1785 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) 1786 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUT(x, val) \ 1787 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), val) 1788 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUTM(x, mask, val) \ 1789 do {\ 1790 HWIO_INTLOCK(); \ 1791 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)); \ 1792 HWIO_INTFREE();\ 1793 } while (0) 1794 1795 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 1796 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 1797 1798 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 1799 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 1800 1801 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 1802 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 1803 1804 //// Register WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL //// 1805 1806 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x0000001c) 1807 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x0000001c) 1808 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 1809 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_SHFT 0 1810 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ 1811 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) 1812 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, mask) \ 1813 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) 1814 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, val) \ 1815 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), val) 1816 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 1817 do {\ 1818 HWIO_INTLOCK(); \ 1819 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)); \ 1820 HWIO_INTFREE();\ 1821 } while (0) 1822 1823 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 1824 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 1825 1826 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 1827 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 1828 1829 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 1830 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 1831 1832 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 1833 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 1834 1835 //// Register WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL //// 1836 1837 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000020) 1838 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000020) 1839 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 1840 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_SHFT 0 1841 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ 1842 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) 1843 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, mask) \ 1844 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) 1845 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, val) \ 1846 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), val) 1847 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 1848 do {\ 1849 HWIO_INTLOCK(); \ 1850 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)); \ 1851 HWIO_INTFREE();\ 1852 } while (0) 1853 1854 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 1855 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 1856 1857 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 1858 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 1859 1860 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 1861 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 1862 1863 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 1864 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 1865 1866 //// Register WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL //// 1867 1868 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) (x+0x00000024) 1869 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) (x+0x00000024) 1870 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0x007fffff 1871 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_SHFT 0 1872 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ 1873 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) 1874 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, mask) \ 1875 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) 1876 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, val) \ 1877 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), val) 1878 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 1879 do {\ 1880 HWIO_INTLOCK(); \ 1881 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)); \ 1882 HWIO_INTFREE();\ 1883 } while (0) 1884 1885 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 1886 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 1887 1888 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 1889 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 1890 1891 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 1892 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 1893 1894 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 1895 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 1896 1897 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 1898 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 1899 1900 //// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL //// 1901 1902 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000028) 1903 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000028) 1904 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 1905 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_SHFT 0 1906 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ 1907 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) 1908 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, mask) \ 1909 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) 1910 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, val) \ 1911 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), val) 1912 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 1913 do {\ 1914 HWIO_INTLOCK(); \ 1915 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)); \ 1916 HWIO_INTFREE();\ 1917 } while (0) 1918 1919 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 1920 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 1921 1922 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 1923 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 1924 1925 //// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS //// 1926 1927 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) (x+0x0000002c) 1928 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) (x+0x0000002c) 1929 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0x0000ffff 1930 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_SHFT 0 1931 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ 1932 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) 1933 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, mask) \ 1934 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) 1935 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUT(x, val) \ 1936 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), val) 1937 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 1938 do {\ 1939 HWIO_INTLOCK(); \ 1940 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)); \ 1941 HWIO_INTFREE();\ 1942 } while (0) 1943 1944 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 1945 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 1946 1947 //// Register WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS //// 1948 1949 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000030) 1950 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000030) 1951 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff 1952 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_SHFT 0 1953 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ 1954 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) 1955 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, mask) \ 1956 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) 1957 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUT(x, val) \ 1958 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), val) 1959 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 1960 do {\ 1961 HWIO_INTLOCK(); \ 1962 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)); \ 1963 HWIO_INTFREE();\ 1964 } while (0) 1965 1966 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 1967 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 1968 1969 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 1970 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 1971 1972 //// Register WFSS_CE_COMMON_R0_CE_HOST_IE_0 //// 1973 1974 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) (x+0x00000034) 1975 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) (x+0x00000034) 1976 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x01ffffff 1977 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SHFT 0 1978 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ 1979 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) 1980 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, mask) \ 1981 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) 1982 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, val) \ 1983 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), val) 1984 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x, mask, val) \ 1985 do {\ 1986 HWIO_INTLOCK(); \ 1987 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)); \ 1988 HWIO_INTFREE();\ 1989 } while (0) 1990 1991 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x01000000 1992 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 1993 1994 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0x00fff000 1995 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc 1996 1997 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0x00000fff 1998 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0 1999 2000 //// Register WFSS_CE_COMMON_R0_CE_HOST_IE_1 //// 2001 2002 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) (x+0x00000038) 2003 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) (x+0x00000038) 2004 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0x00000fff 2005 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_SHFT 0 2006 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ 2007 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) 2008 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, mask) \ 2009 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) 2010 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, val) \ 2011 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), val) 2012 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x, mask, val) \ 2013 do {\ 2014 HWIO_INTLOCK(); \ 2015 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)); \ 2016 HWIO_INTFREE();\ 2017 } while (0) 2018 2019 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0x00000fff 2020 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 2021 2022 //// Register WFSS_CE_COMMON_R0_CE_SECURITY //// 2023 2024 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) (x+0x0000003c) 2025 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) (x+0x0000003c) 2026 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0x00ffffff 2027 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SHFT 0 2028 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ 2029 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) 2030 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, mask) \ 2031 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) 2032 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, val) \ 2033 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), val) 2034 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x, mask, val) \ 2035 do {\ 2036 HWIO_INTLOCK(); \ 2037 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)); \ 2038 HWIO_INTFREE();\ 2039 } while (0) 2040 2041 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0x00fff000 2042 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc 2043 2044 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0x00000fff 2045 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0 2046 2047 //// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_0 //// 2048 2049 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) (x+0x00000040) 2050 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) (x+0x00000040) 2051 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x01ffffff 2052 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SHFT 0 2053 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ 2054 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) 2055 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, mask) \ 2056 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) 2057 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, val) \ 2058 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), val) 2059 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x, mask, val) \ 2060 do {\ 2061 HWIO_INTLOCK(); \ 2062 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)); \ 2063 HWIO_INTFREE();\ 2064 } while (0) 2065 2066 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x01000000 2067 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 2068 2069 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0x00fff000 2070 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc 2071 2072 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0x00000fff 2073 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0 2074 2075 //// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_1 //// 2076 2077 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) (x+0x00000044) 2078 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) (x+0x00000044) 2079 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0x00000fff 2080 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_SHFT 0 2081 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ 2082 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) 2083 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, mask) \ 2084 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) 2085 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, val) \ 2086 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), val) 2087 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x, mask, val) \ 2088 do {\ 2089 HWIO_INTLOCK(); \ 2090 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)); \ 2091 HWIO_INTFREE();\ 2092 } while (0) 2093 2094 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0x00000fff 2095 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 2096 2097 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0 //// 2098 2099 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) (x+0x00000048) 2100 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) (x+0x00000048) 2101 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff 2102 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SHFT 0 2103 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ 2104 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) 2105 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, mask) \ 2106 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) 2107 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, val) \ 2108 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), val) 2109 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x, mask, val) \ 2110 do {\ 2111 HWIO_INTLOCK(); \ 2112 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)); \ 2113 HWIO_INTFREE();\ 2114 } while (0) 2115 2116 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff 2117 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 2118 2119 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1 //// 2120 2121 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) (x+0x0000004c) 2122 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) (x+0x0000004c) 2123 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0x0001ffff 2124 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SHFT 0 2125 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ 2126 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) 2127 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, mask) \ 2128 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) 2129 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, val) \ 2130 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), val) 2131 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x, mask, val) \ 2132 do {\ 2133 HWIO_INTLOCK(); \ 2134 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)); \ 2135 HWIO_INTFREE();\ 2136 } while (0) 2137 2138 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0x0001ffff 2139 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 2140 2141 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0 //// 2142 2143 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x) (x+0x00000050) 2144 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x) (x+0x00000050) 2145 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xffffffff 2146 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_SHFT 0 2147 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x) \ 2148 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK) 2149 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(x, mask) \ 2150 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), mask) 2151 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(x, val) \ 2152 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), val) 2153 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(x, mask, val) \ 2154 do {\ 2155 HWIO_INTLOCK(); \ 2156 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x)); \ 2157 HWIO_INTFREE();\ 2158 } while (0) 2159 2160 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xffffffff 2161 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0x0 2162 2163 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1 //// 2164 2165 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x) (x+0x00000054) 2166 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x) (x+0x00000054) 2167 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0x0001ffff 2168 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_SHFT 0 2169 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x) \ 2170 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK) 2171 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(x, mask) \ 2172 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), mask) 2173 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(x, val) \ 2174 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), val) 2175 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(x, mask, val) \ 2176 do {\ 2177 HWIO_INTLOCK(); \ 2178 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x)); \ 2179 HWIO_INTFREE();\ 2180 } while (0) 2181 2182 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0x0001ffff 2183 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0x0 2184 2185 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0 //// 2186 2187 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) (x+0x00000058) 2188 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) (x+0x00000058) 2189 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff 2190 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_SHFT 0 2191 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ 2192 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) 2193 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, mask) \ 2194 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) 2195 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUT(x, val) \ 2196 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), val) 2197 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUTM(x, mask, val) \ 2198 do {\ 2199 HWIO_INTLOCK(); \ 2200 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)); \ 2201 HWIO_INTFREE();\ 2202 } while (0) 2203 2204 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff 2205 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 2206 2207 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1 //// 2208 2209 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) (x+0x0000005c) 2210 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) (x+0x0000005c) 2211 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff 2212 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_SHFT 0 2213 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ 2214 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) 2215 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, mask) \ 2216 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) 2217 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUT(x, val) \ 2218 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), val) 2219 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUTM(x, mask, val) \ 2220 do {\ 2221 HWIO_INTLOCK(); \ 2222 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)); \ 2223 HWIO_INTFREE();\ 2224 } while (0) 2225 2226 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff 2227 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 2228 2229 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2 //// 2230 2231 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) (x+0x00000060) 2232 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) (x+0x00000060) 2233 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff 2234 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_SHFT 0 2235 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ 2236 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) 2237 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, mask) \ 2238 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) 2239 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUT(x, val) \ 2240 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), val) 2241 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUTM(x, mask, val) \ 2242 do {\ 2243 HWIO_INTLOCK(); \ 2244 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)); \ 2245 HWIO_INTFREE();\ 2246 } while (0) 2247 2248 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff 2249 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 2250 2251 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3 //// 2252 2253 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) (x+0x00000064) 2254 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) (x+0x00000064) 2255 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff 2256 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_SHFT 0 2257 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ 2258 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) 2259 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, mask) \ 2260 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) 2261 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUT(x, val) \ 2262 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), val) 2263 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUTM(x, mask, val) \ 2264 do {\ 2265 HWIO_INTLOCK(); \ 2266 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)); \ 2267 HWIO_INTFREE();\ 2268 } while (0) 2269 2270 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff 2271 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 2272 2273 //// Register WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS //// 2274 2275 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x) (x+0x00000068) 2276 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_PHYS(x) (x+0x00000068) 2277 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK 0xfffdffff 2278 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_SHFT 0 2279 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x) \ 2280 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK) 2281 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_INM(x, mask) \ 2282 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) 2283 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUT(x, val) \ 2284 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), val) 2285 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUTM(x, mask, val) \ 2286 do {\ 2287 HWIO_INTLOCK(); \ 2288 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)); \ 2289 HWIO_INTFREE();\ 2290 } while (0) 2291 2292 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_BMSK 0x80000000 2293 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_SHFT 0x1f 2294 2295 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_BMSK 0x40000000 2296 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_SHFT 0x1e 2297 2298 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_BMSK 0x3ffc0000 2299 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_SHFT 0x12 2300 2301 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_BMSK 0x00010000 2302 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_SHFT 0x10 2303 2304 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_BMSK 0x0000f000 2305 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_SHFT 0xc 2306 2307 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK 0x00000fff 2308 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT 0x0 2309 2310 //// Register WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR //// 2311 2312 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x) (x+0x0000006c) 2313 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_PHYS(x) (x+0x0000006c) 2314 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK 0xffffffff 2315 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_SHFT 0 2316 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x) \ 2317 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK) 2318 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_INM(x, mask) \ 2319 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask) 2320 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUT(x, val) \ 2321 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), val) 2322 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUTM(x, mask, val) \ 2323 do {\ 2324 HWIO_INTLOCK(); \ 2325 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x)); \ 2326 HWIO_INTFREE();\ 2327 } while (0) 2328 2329 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_BMSK 0xffffffff 2330 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_SHFT 0x0 2331 2332 //// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL //// 2333 2334 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) (x+0x00000400) 2335 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) (x+0x00000400) 2336 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x000000ff 2337 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_SHFT 0 2338 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ 2339 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) 2340 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, mask) \ 2341 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) 2342 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, val) \ 2343 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), val) 2344 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 2345 do {\ 2346 HWIO_INTLOCK(); \ 2347 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)); \ 2348 HWIO_INTFREE();\ 2349 } while (0) 2350 2351 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0x000000ff 2352 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 2353 2354 //// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_0 //// 2355 2356 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00000404) 2357 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00000404) 2358 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff 2359 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_SHFT 0 2360 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ 2361 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) 2362 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, mask) \ 2363 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) 2364 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, val) \ 2365 out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), val) 2366 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 2367 do {\ 2368 HWIO_INTLOCK(); \ 2369 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)); \ 2370 HWIO_INTFREE();\ 2371 } while (0) 2372 2373 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 2374 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 2375 2376 //// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_1 //// 2377 2378 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00000408) 2379 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00000408) 2380 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff 2381 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_SHFT 0 2382 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ 2383 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) 2384 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, mask) \ 2385 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) 2386 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, val) \ 2387 out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), val) 2388 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 2389 do {\ 2390 HWIO_INTLOCK(); \ 2391 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)); \ 2392 HWIO_INTFREE();\ 2393 } while (0) 2394 2395 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 2396 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 2397 2398 //// Register WFSS_CE_COMMON_R1_TESTBUS_LOW //// 2399 2400 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) (x+0x0000040c) 2401 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) (x+0x0000040c) 2402 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff 2403 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_SHFT 0 2404 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ 2405 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) 2406 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, mask) \ 2407 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) 2408 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUT(x, val) \ 2409 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), val) 2410 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 2411 do {\ 2412 HWIO_INTLOCK(); \ 2413 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)); \ 2414 HWIO_INTFREE();\ 2415 } while (0) 2416 2417 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 2418 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 2419 2420 //// Register WFSS_CE_COMMON_R1_TESTBUS_HIGH //// 2421 2422 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) (x+0x00000410) 2423 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) (x+0x00000410) 2424 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0x000000ff 2425 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_SHFT 0 2426 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ 2427 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) 2428 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, mask) \ 2429 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) 2430 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUT(x, val) \ 2431 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), val) 2432 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 2433 do {\ 2434 HWIO_INTLOCK(); \ 2435 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)); \ 2436 HWIO_INTFREE();\ 2437 } while (0) 2438 2439 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 2440 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 2441 2442 //// Register WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL //// 2443 2444 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00000414) 2445 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00000414) 2446 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 2447 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 2448 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 2449 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 2450 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 2451 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 2452 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 2453 out_dword( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 2454 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 2455 do {\ 2456 HWIO_INTLOCK(); \ 2457 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 2458 HWIO_INTFREE();\ 2459 } while (0) 2460 2461 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 2462 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 2463 2464 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 2465 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 2466 2467 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 2468 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 2469 2470 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 2471 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 2472 2473 //// Register WFSS_CE_COMMON_R1_END_OF_TEST_CHECK //// 2474 2475 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00000418) 2476 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00000418) 2477 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x00000001 2478 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_SHFT 0 2479 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ 2480 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) 2481 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, mask) \ 2482 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) 2483 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, val) \ 2484 out_dword( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), val) 2485 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 2486 do {\ 2487 HWIO_INTLOCK(); \ 2488 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)); \ 2489 HWIO_INTFREE();\ 2490 } while (0) 2491 2492 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 2493 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 2494 2495 2496 /////////////////////////////////////////////////////////////////////////////////////////////// 2497 // Register Data for Block WFSS_CE_REG 2498 /////////////////////////////////////////////////////////////////////////////////////////////// 2499 2500 2501 #endif 2502 2503