1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _PHYRX_ABORT_REQUEST_INFO_H_ 20 #define _PHYRX_ABORT_REQUEST_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 phyrx_abort_reason[7:0], phy_enters_nap_state[8], phy_enters_defer_state[9], reserved_0[15:10], receive_duration[31:16] 29 // 30 // ################ END SUMMARY ################# 31 32 #define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 33 34 struct phyrx_abort_request_info { 35 uint32_t phyrx_abort_reason : 8, //[7:0] 36 phy_enters_nap_state : 1, //[8] 37 phy_enters_defer_state : 1, //[9] 38 reserved_0 : 6, //[15:10] 39 receive_duration : 16; //[31:16] 40 }; 41 42 /* 43 44 phyrx_abort_reason 45 46 <enum 0 phyrx_err_phy_off> Reception aborted due to 47 receiving a PHY_OFF TLV 48 49 <enum 1 phyrx_err_synth_off> 50 51 <enum 2 phyrx_err_ofdma_timing> 52 53 <enum 3 phyrx_err_ofdma_signal_parity> 54 55 <enum 4 phyrx_err_ofdma_rate_illegal> 56 57 <enum 5 phyrx_err_ofdma_length_illegal> 58 59 <enum 6 phyrx_err_ofdma_restart> 60 61 <enum 7 phyrx_err_ofdma_service> 62 63 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 64 65 66 67 <enum 9 phyrx_err_cck_blokker> 68 69 <enum 10 phyrx_err_cck_timing> 70 71 <enum 11 phyrx_err_cck_header_crc> 72 73 <enum 12 phyrx_err_cck_rate_illegal> 74 75 <enum 13 phyrx_err_cck_length_illegal> 76 77 <enum 14 phyrx_err_cck_restart> 78 79 <enum 15 phyrx_err_cck_service> 80 81 <enum 16 phyrx_err_cck_power_drop> 82 83 84 85 <enum 17 phyrx_err_ht_crc_err> 86 87 <enum 18 phyrx_err_ht_length_illegal> 88 89 <enum 19 phyrx_err_ht_rate_illegal> 90 91 <enum 20 phyrx_err_ht_zlf> 92 93 <enum 21 phyrx_err_false_radar_ext> 94 95 96 97 <enum 22 phyrx_err_green_field> 98 99 100 101 <enum 23 phyrx_err_bw_gt_dyn_bw> 102 103 <enum 24 phyrx_err_leg_ht_mismatch> 104 105 <enum 25 phyrx_err_vht_crc_error> 106 107 <enum 26 phyrx_err_vht_siga_unsupported> 108 109 <enum 27 phyrx_err_vht_lsig_len_invalid> 110 111 <enum 28 phyrx_err_vht_ndp_or_zlf> 112 113 <enum 29 phyrx_err_vht_nsym_lt_zero> 114 115 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 116 117 <enum 31 phyrx_err_vht_rx_skip_group_id0> 118 119 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 120 121 <enum 33 phyrx_err_vht_rx_skip_group_id63> 122 123 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 124 125 <enum 35 phyrx_err_defer_nap> 126 127 <enum 36 phyrx_err_fdomain_timeout> 128 129 <enum 37 phyrx_err_lsig_rel_check> 130 131 <enum 38 phyrx_err_bt_collision> 132 133 <enum 39 phyrx_err_unsupported_mu_feedback> 134 135 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 136 137 <enum 41 phyrx_err_unsupported_cbf> 138 139 140 141 <enum 42 phyrx_err_other> Should not really be used. If 142 needed, ask for documentation update 143 144 145 146 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 147 phyrx_err_he_crc_error > <enum 45 148 phyrx_err_he_sigb_unsupported > <enum 46 149 phyrx_err_he_mu_mode_unsupported > <enum 47 150 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 151 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 152 phyrx_err_he_num_users_unsupported ><enum 51 153 phyrx_err_he_sounding_params_unsupported > 154 155 156 157 <enum 52 phyrx_err_MU_UL_no_power_detected> 158 159 160 161 162 163 164 165 <legal 0 - 52> 166 167 phy_enters_nap_state 168 169 When set, PHY enters PHY NAP state after sending this 170 abort 171 172 173 174 Note that nap and defer state are mutually exclusive. 175 176 177 178 Field put pro-actively in place....usage still to be 179 agreed upon. 180 181 <legal all> 182 183 phy_enters_defer_state 184 185 When set, PHY enters PHY defer state after sending this 186 abort 187 188 189 190 Note that nap and defer state are mutually exclusive. 191 192 193 194 Field put pro-actively in place....usage still to be 195 agreed upon. 196 197 <legal all> 198 199 reserved_0 200 201 <legal 0> 202 203 receive_duration 204 205 The remaining receive duration of this PPDU in the 206 medium (in us). When PHY does not know this duration when 207 this TLV is generated, the field will be set to 0. 208 209 The timing reference point is the reception by the MAC 210 of this TLV. The value shall be accurate to within 2us. 211 212 213 214 In case Phy_enters_nap_state and/or 215 Phy_enters_defer_state is set, there is a possibility that 216 MAC PMM can also decide to go into a low(er) power state. 217 218 <legal all> 219 */ 220 221 222 /* Description PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON 223 224 <enum 0 phyrx_err_phy_off> Reception aborted due to 225 receiving a PHY_OFF TLV 226 227 <enum 1 phyrx_err_synth_off> 228 229 <enum 2 phyrx_err_ofdma_timing> 230 231 <enum 3 phyrx_err_ofdma_signal_parity> 232 233 <enum 4 phyrx_err_ofdma_rate_illegal> 234 235 <enum 5 phyrx_err_ofdma_length_illegal> 236 237 <enum 6 phyrx_err_ofdma_restart> 238 239 <enum 7 phyrx_err_ofdma_service> 240 241 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 242 243 244 245 <enum 9 phyrx_err_cck_blokker> 246 247 <enum 10 phyrx_err_cck_timing> 248 249 <enum 11 phyrx_err_cck_header_crc> 250 251 <enum 12 phyrx_err_cck_rate_illegal> 252 253 <enum 13 phyrx_err_cck_length_illegal> 254 255 <enum 14 phyrx_err_cck_restart> 256 257 <enum 15 phyrx_err_cck_service> 258 259 <enum 16 phyrx_err_cck_power_drop> 260 261 262 263 <enum 17 phyrx_err_ht_crc_err> 264 265 <enum 18 phyrx_err_ht_length_illegal> 266 267 <enum 19 phyrx_err_ht_rate_illegal> 268 269 <enum 20 phyrx_err_ht_zlf> 270 271 <enum 21 phyrx_err_false_radar_ext> 272 273 274 275 <enum 22 phyrx_err_green_field> 276 277 278 279 <enum 23 phyrx_err_bw_gt_dyn_bw> 280 281 <enum 24 phyrx_err_leg_ht_mismatch> 282 283 <enum 25 phyrx_err_vht_crc_error> 284 285 <enum 26 phyrx_err_vht_siga_unsupported> 286 287 <enum 27 phyrx_err_vht_lsig_len_invalid> 288 289 <enum 28 phyrx_err_vht_ndp_or_zlf> 290 291 <enum 29 phyrx_err_vht_nsym_lt_zero> 292 293 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 294 295 <enum 31 phyrx_err_vht_rx_skip_group_id0> 296 297 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 298 299 <enum 33 phyrx_err_vht_rx_skip_group_id63> 300 301 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 302 303 <enum 35 phyrx_err_defer_nap> 304 305 <enum 36 phyrx_err_fdomain_timeout> 306 307 <enum 37 phyrx_err_lsig_rel_check> 308 309 <enum 38 phyrx_err_bt_collision> 310 311 <enum 39 phyrx_err_unsupported_mu_feedback> 312 313 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 314 315 <enum 41 phyrx_err_unsupported_cbf> 316 317 318 319 <enum 42 phyrx_err_other> Should not really be used. If 320 needed, ask for documentation update 321 322 323 324 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 325 phyrx_err_he_crc_error > <enum 45 326 phyrx_err_he_sigb_unsupported > <enum 46 327 phyrx_err_he_mu_mode_unsupported > <enum 47 328 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 329 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 330 phyrx_err_he_num_users_unsupported ><enum 51 331 phyrx_err_he_sounding_params_unsupported > 332 333 334 335 <enum 52 phyrx_err_MU_UL_no_power_detected> 336 337 338 339 340 341 342 343 <legal 0 - 52> 344 */ 345 #define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET 0x00000000 346 #define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB 0 347 #define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK 0x000000ff 348 349 /* Description PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE 350 351 When set, PHY enters PHY NAP state after sending this 352 abort 353 354 355 356 Note that nap and defer state are mutually exclusive. 357 358 359 360 Field put pro-actively in place....usage still to be 361 agreed upon. 362 363 <legal all> 364 */ 365 #define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 366 #define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB 8 367 #define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK 0x00000100 368 369 /* Description PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE 370 371 When set, PHY enters PHY defer state after sending this 372 abort 373 374 375 376 Note that nap and defer state are mutually exclusive. 377 378 379 380 Field put pro-actively in place....usage still to be 381 agreed upon. 382 383 <legal all> 384 */ 385 #define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 386 #define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB 9 387 #define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 388 389 /* Description PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0 390 391 <legal 0> 392 */ 393 #define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 394 #define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 10 395 #define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000fc00 396 397 /* Description PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION 398 399 The remaining receive duration of this PPDU in the 400 medium (in us). When PHY does not know this duration when 401 this TLV is generated, the field will be set to 0. 402 403 The timing reference point is the reception by the MAC 404 of this TLV. The value shall be accurate to within 2us. 405 406 407 408 In case Phy_enters_nap_state and/or 409 Phy_enters_defer_state is set, there is a possibility that 410 MAC PMM can also decide to go into a low(er) power state. 411 412 <legal all> 413 */ 414 #define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 415 #define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB 16 416 #define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK 0xffff0000 417 418 419 #endif // _PHYRX_ABORT_REQUEST_INFO_H_ 420