1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _PHYRX_PKT_END_INFO_H_ 20*5113495bSYour Name #define _PHYRX_PKT_END_INFO_H_ 21*5113495bSYour Name #if !defined(__ASSEMBLER__) 22*5113495bSYour Name #endif 23*5113495bSYour Name 24*5113495bSYour Name #include "rx_location_info.h" 25*5113495bSYour Name #include "rx_timing_offset_info.h" 26*5113495bSYour Name #include "receive_rssi_info.h" 27*5113495bSYour Name 28*5113495bSYour Name // ################ START SUMMARY ################# 29*5113495bSYour Name // 30*5113495bSYour Name // Dword Fields 31*5113495bSYour Name // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27] 32*5113495bSYour Name // 1 phy_timestamp_1_lower_32[31:0] 33*5113495bSYour Name // 2 phy_timestamp_1_upper_32[31:0] 34*5113495bSYour Name // 3 phy_timestamp_2_lower_32[31:0] 35*5113495bSYour Name // 4 phy_timestamp_2_upper_32[31:0] 36*5113495bSYour Name // 5-13 struct rx_location_info rx_location_info_details; 37*5113495bSYour Name // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 38*5113495bSYour Name // 15-30 struct receive_rssi_info post_rssi_info_details; 39*5113495bSYour Name // 31 phy_sw_status_31_0[31:0] 40*5113495bSYour Name // 32 phy_sw_status_63_32[31:0] 41*5113495bSYour Name // 42*5113495bSYour Name // ################ END SUMMARY ################# 43*5113495bSYour Name 44*5113495bSYour Name #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 45*5113495bSYour Name 46*5113495bSYour Name struct phyrx_pkt_end_info { 47*5113495bSYour Name uint32_t phy_internal_nap : 1, //[0] 48*5113495bSYour Name location_info_valid : 1, //[1] 49*5113495bSYour Name timing_info_valid : 1, //[2] 50*5113495bSYour Name rssi_info_valid : 1, //[3] 51*5113495bSYour Name rx_frame_correction_needed : 1, //[4] 52*5113495bSYour Name frameless_frame_received : 1, //[5] 53*5113495bSYour Name reserved_0a : 6, //[11:6] 54*5113495bSYour Name dl_ofdma_info_valid : 1, //[12] 55*5113495bSYour Name dl_ofdma_ru_start_index : 7, //[19:13] 56*5113495bSYour Name dl_ofdma_ru_width : 7, //[26:20] 57*5113495bSYour Name reserved_0b : 5; //[31:27] 58*5113495bSYour Name uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 59*5113495bSYour Name uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 60*5113495bSYour Name uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 61*5113495bSYour Name uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 62*5113495bSYour Name struct rx_location_info rx_location_info_details; 63*5113495bSYour Name struct rx_timing_offset_info rx_timing_offset_info_details; 64*5113495bSYour Name struct receive_rssi_info post_rssi_info_details; 65*5113495bSYour Name uint32_t phy_sw_status_31_0 : 32; //[31:0] 66*5113495bSYour Name uint32_t phy_sw_status_63_32 : 32; //[31:0] 67*5113495bSYour Name }; 68*5113495bSYour Name 69*5113495bSYour Name /* 70*5113495bSYour Name 71*5113495bSYour Name phy_internal_nap 72*5113495bSYour Name 73*5113495bSYour Name When set, PHY RX entered an internal NAP state, as PHY 74*5113495bSYour Name determined that this reception was not destined to this 75*5113495bSYour Name device 76*5113495bSYour Name 77*5113495bSYour Name location_info_valid 78*5113495bSYour Name 79*5113495bSYour Name Indicates that the RX_LOCATION_INFO structure later on 80*5113495bSYour Name in the TLV contains valid info 81*5113495bSYour Name 82*5113495bSYour Name timing_info_valid 83*5113495bSYour Name 84*5113495bSYour Name Indicates that the RX_TIMING_OFFSET_INFO structure later 85*5113495bSYour Name on in the TLV contains valid info 86*5113495bSYour Name 87*5113495bSYour Name rssi_info_valid 88*5113495bSYour Name 89*5113495bSYour Name Indicates that the RECEIVE_RSSI_INFO structure later on 90*5113495bSYour Name in the TLV contains valid info 91*5113495bSYour Name 92*5113495bSYour Name rx_frame_correction_needed 93*5113495bSYour Name 94*5113495bSYour Name When clear, no action is needed in the MAC. 95*5113495bSYour Name 96*5113495bSYour Name 97*5113495bSYour Name 98*5113495bSYour Name When set, the falling edge of the rx_frame happened 4us 99*5113495bSYour Name too late. MAC will need to compensate for this delay in 100*5113495bSYour Name order to maintain proper SIFS timing and/or not to get 101*5113495bSYour Name de-slotted. 102*5113495bSYour Name 103*5113495bSYour Name 104*5113495bSYour Name 105*5113495bSYour Name PHY uses this for very short 11a frames. 106*5113495bSYour Name 107*5113495bSYour Name 108*5113495bSYour Name 109*5113495bSYour Name When set, PHY will have passed this TLV to the MAC up to 110*5113495bSYour Name 8 us into the 'real SIFS' time, and thus within 4us from the 111*5113495bSYour Name falling edge of the rx_frame. 112*5113495bSYour Name 113*5113495bSYour Name 114*5113495bSYour Name 115*5113495bSYour Name <legal all> 116*5113495bSYour Name 117*5113495bSYour Name frameless_frame_received 118*5113495bSYour Name 119*5113495bSYour Name When set, PHY has received the 'frameless frame' . Can 120*5113495bSYour Name be used in the 'MU-RTS -CTS exchange where CTS reception can 121*5113495bSYour Name be problematic. 122*5113495bSYour Name 123*5113495bSYour Name <legal all> 124*5113495bSYour Name 125*5113495bSYour Name reserved_0a 126*5113495bSYour Name 127*5113495bSYour Name <legal 0> 128*5113495bSYour Name 129*5113495bSYour Name dl_ofdma_info_valid 130*5113495bSYour Name 131*5113495bSYour Name When set, the following DL_ofdma_... fields are valid. 132*5113495bSYour Name 133*5113495bSYour Name It provides the MAC insight into which RU was allocated 134*5113495bSYour Name to this device. 135*5113495bSYour Name 136*5113495bSYour Name <legal all> 137*5113495bSYour Name 138*5113495bSYour Name dl_ofdma_ru_start_index 139*5113495bSYour Name 140*5113495bSYour Name RU index number to which User is assigned 141*5113495bSYour Name 142*5113495bSYour Name RU numbering is over the entire BW, starting from 0 143*5113495bSYour Name 144*5113495bSYour Name <legal 0-73> 145*5113495bSYour Name 146*5113495bSYour Name dl_ofdma_ru_width 147*5113495bSYour Name 148*5113495bSYour Name The size of the RU for this user. 149*5113495bSYour Name 150*5113495bSYour Name In units of 1 (26 tone) RU 151*5113495bSYour Name 152*5113495bSYour Name <legal 1-74> 153*5113495bSYour Name 154*5113495bSYour Name reserved_0b 155*5113495bSYour Name 156*5113495bSYour Name <legal 0> 157*5113495bSYour Name 158*5113495bSYour Name phy_timestamp_1_lower_32 159*5113495bSYour Name 160*5113495bSYour Name TODO PHY: cleanup descriptionThe PHY timestamp in the 161*5113495bSYour Name AMPI of the first rising edge of rx_clear_pri after 162*5113495bSYour Name TX_PHY_DESC. . This field should set to 0 by the PHY and 163*5113495bSYour Name should be updated by the AMPI before being forwarded to the 164*5113495bSYour Name rest of the MAC. This field indicates the lower 32 bits of 165*5113495bSYour Name the timestamp 166*5113495bSYour Name 167*5113495bSYour Name phy_timestamp_1_upper_32 168*5113495bSYour Name 169*5113495bSYour Name TODO PHY: cleanup description 170*5113495bSYour Name 171*5113495bSYour Name The PHY timestamp in the AMPI of the first rising edge 172*5113495bSYour Name of rx_clear_pri after TX_PHY_DESC. This field should set to 173*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 174*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 175*5113495bSYour Name upper 32 bits of the timestamp 176*5113495bSYour Name 177*5113495bSYour Name phy_timestamp_2_lower_32 178*5113495bSYour Name 179*5113495bSYour Name TODO PHY: cleanup description 180*5113495bSYour Name 181*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 182*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 183*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 184*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 185*5113495bSYour Name lower 32 bits of the timestamp 186*5113495bSYour Name 187*5113495bSYour Name phy_timestamp_2_upper_32 188*5113495bSYour Name 189*5113495bSYour Name TODO PHY: cleanup description 190*5113495bSYour Name 191*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 192*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 193*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 194*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 195*5113495bSYour Name upper 32 bits of the timestamp 196*5113495bSYour Name 197*5113495bSYour Name struct rx_location_info rx_location_info_details 198*5113495bSYour Name 199*5113495bSYour Name Overview of location related info 200*5113495bSYour Name 201*5113495bSYour Name struct rx_timing_offset_info rx_timing_offset_info_details 202*5113495bSYour Name 203*5113495bSYour Name Overview of timing offset related info 204*5113495bSYour Name 205*5113495bSYour Name struct receive_rssi_info post_rssi_info_details 206*5113495bSYour Name 207*5113495bSYour Name Overview of the post-RSSI values. 208*5113495bSYour Name 209*5113495bSYour Name phy_sw_status_31_0 210*5113495bSYour Name 211*5113495bSYour Name Some PHY micro code status that can be put in here. 212*5113495bSYour Name Details of definition within SW specification 213*5113495bSYour Name 214*5113495bSYour Name This field can be used for debugging, FW - SW message 215*5113495bSYour Name exchange, etc. 216*5113495bSYour Name 217*5113495bSYour Name It could for example be a pointer to a DDR memory 218*5113495bSYour Name location where PHY FW put some debug info. 219*5113495bSYour Name 220*5113495bSYour Name <legal all> 221*5113495bSYour Name 222*5113495bSYour Name phy_sw_status_63_32 223*5113495bSYour Name 224*5113495bSYour Name Some PHY micro code status that can be put in here. 225*5113495bSYour Name Details of definition within SW specification 226*5113495bSYour Name 227*5113495bSYour Name This field can be used for debugging, FW - SW message 228*5113495bSYour Name exchange, etc. 229*5113495bSYour Name 230*5113495bSYour Name It could for example be a pointer to a DDR memory 231*5113495bSYour Name location where PHY FW put some debug info. 232*5113495bSYour Name 233*5113495bSYour Name <legal all> 234*5113495bSYour Name */ 235*5113495bSYour Name 236*5113495bSYour Name 237*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP 238*5113495bSYour Name 239*5113495bSYour Name When set, PHY RX entered an internal NAP state, as PHY 240*5113495bSYour Name determined that this reception was not destined to this 241*5113495bSYour Name device 242*5113495bSYour Name */ 243*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 244*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 245*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 246*5113495bSYour Name 247*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID 248*5113495bSYour Name 249*5113495bSYour Name Indicates that the RX_LOCATION_INFO structure later on 250*5113495bSYour Name in the TLV contains valid info 251*5113495bSYour Name */ 252*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 253*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 254*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 255*5113495bSYour Name 256*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID 257*5113495bSYour Name 258*5113495bSYour Name Indicates that the RX_TIMING_OFFSET_INFO structure later 259*5113495bSYour Name on in the TLV contains valid info 260*5113495bSYour Name */ 261*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 262*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 263*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 264*5113495bSYour Name 265*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID 266*5113495bSYour Name 267*5113495bSYour Name Indicates that the RECEIVE_RSSI_INFO structure later on 268*5113495bSYour Name in the TLV contains valid info 269*5113495bSYour Name */ 270*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 271*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 272*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 273*5113495bSYour Name 274*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED 275*5113495bSYour Name 276*5113495bSYour Name When clear, no action is needed in the MAC. 277*5113495bSYour Name 278*5113495bSYour Name 279*5113495bSYour Name 280*5113495bSYour Name When set, the falling edge of the rx_frame happened 4us 281*5113495bSYour Name too late. MAC will need to compensate for this delay in 282*5113495bSYour Name order to maintain proper SIFS timing and/or not to get 283*5113495bSYour Name de-slotted. 284*5113495bSYour Name 285*5113495bSYour Name 286*5113495bSYour Name 287*5113495bSYour Name PHY uses this for very short 11a frames. 288*5113495bSYour Name 289*5113495bSYour Name 290*5113495bSYour Name 291*5113495bSYour Name When set, PHY will have passed this TLV to the MAC up to 292*5113495bSYour Name 8 us into the 'real SIFS' time, and thus within 4us from the 293*5113495bSYour Name falling edge of the rx_frame. 294*5113495bSYour Name 295*5113495bSYour Name 296*5113495bSYour Name 297*5113495bSYour Name <legal all> 298*5113495bSYour Name */ 299*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 300*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 301*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 302*5113495bSYour Name 303*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED 304*5113495bSYour Name 305*5113495bSYour Name When set, PHY has received the 'frameless frame' . Can 306*5113495bSYour Name be used in the 'MU-RTS -CTS exchange where CTS reception can 307*5113495bSYour Name be problematic. 308*5113495bSYour Name 309*5113495bSYour Name <legal all> 310*5113495bSYour Name */ 311*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 312*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 313*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 314*5113495bSYour Name 315*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_RESERVED_0A 316*5113495bSYour Name 317*5113495bSYour Name <legal 0> 318*5113495bSYour Name */ 319*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 320*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 321*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 322*5113495bSYour Name 323*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID 324*5113495bSYour Name 325*5113495bSYour Name When set, the following DL_ofdma_... fields are valid. 326*5113495bSYour Name 327*5113495bSYour Name It provides the MAC insight into which RU was allocated 328*5113495bSYour Name to this device. 329*5113495bSYour Name 330*5113495bSYour Name <legal all> 331*5113495bSYour Name */ 332*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 333*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 334*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 335*5113495bSYour Name 336*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX 337*5113495bSYour Name 338*5113495bSYour Name RU index number to which User is assigned 339*5113495bSYour Name 340*5113495bSYour Name RU numbering is over the entire BW, starting from 0 341*5113495bSYour Name 342*5113495bSYour Name <legal 0-73> 343*5113495bSYour Name */ 344*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 345*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 346*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 347*5113495bSYour Name 348*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH 349*5113495bSYour Name 350*5113495bSYour Name The size of the RU for this user. 351*5113495bSYour Name 352*5113495bSYour Name In units of 1 (26 tone) RU 353*5113495bSYour Name 354*5113495bSYour Name <legal 1-74> 355*5113495bSYour Name */ 356*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 357*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 358*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 359*5113495bSYour Name 360*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_RESERVED_0B 361*5113495bSYour Name 362*5113495bSYour Name <legal 0> 363*5113495bSYour Name */ 364*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 365*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 366*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 367*5113495bSYour Name 368*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 369*5113495bSYour Name 370*5113495bSYour Name TODO PHY: cleanup descriptionThe PHY timestamp in the 371*5113495bSYour Name AMPI of the first rising edge of rx_clear_pri after 372*5113495bSYour Name TX_PHY_DESC. . This field should set to 0 by the PHY and 373*5113495bSYour Name should be updated by the AMPI before being forwarded to the 374*5113495bSYour Name rest of the MAC. This field indicates the lower 32 bits of 375*5113495bSYour Name the timestamp 376*5113495bSYour Name */ 377*5113495bSYour Name #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 378*5113495bSYour Name #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 379*5113495bSYour Name #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 380*5113495bSYour Name 381*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 382*5113495bSYour Name 383*5113495bSYour Name TODO PHY: cleanup description 384*5113495bSYour Name 385*5113495bSYour Name The PHY timestamp in the AMPI of the first rising edge 386*5113495bSYour Name of rx_clear_pri after TX_PHY_DESC. This field should set to 387*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 388*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 389*5113495bSYour Name upper 32 bits of the timestamp 390*5113495bSYour Name */ 391*5113495bSYour Name #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 392*5113495bSYour Name #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 393*5113495bSYour Name #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 394*5113495bSYour Name 395*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 396*5113495bSYour Name 397*5113495bSYour Name TODO PHY: cleanup description 398*5113495bSYour Name 399*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 400*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 401*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 402*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 403*5113495bSYour Name lower 32 bits of the timestamp 404*5113495bSYour Name */ 405*5113495bSYour Name #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 406*5113495bSYour Name #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 407*5113495bSYour Name #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 408*5113495bSYour Name 409*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 410*5113495bSYour Name 411*5113495bSYour Name TODO PHY: cleanup description 412*5113495bSYour Name 413*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 414*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 415*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 416*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 417*5113495bSYour Name upper 32 bits of the timestamp 418*5113495bSYour Name */ 419*5113495bSYour Name #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 420*5113495bSYour Name #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 421*5113495bSYour Name #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 422*5113495bSYour Name #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000014 423*5113495bSYour Name #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 424*5113495bSYour Name #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 425*5113495bSYour Name #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000018 426*5113495bSYour Name #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 427*5113495bSYour Name #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 428*5113495bSYour Name #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000001c 429*5113495bSYour Name #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 430*5113495bSYour Name #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 431*5113495bSYour Name #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000020 432*5113495bSYour Name #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 433*5113495bSYour Name #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 434*5113495bSYour Name #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000024 435*5113495bSYour Name #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 436*5113495bSYour Name #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 437*5113495bSYour Name #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000028 438*5113495bSYour Name #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 439*5113495bSYour Name #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 440*5113495bSYour Name #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000002c 441*5113495bSYour Name #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 442*5113495bSYour Name #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 443*5113495bSYour Name #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000030 444*5113495bSYour Name #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 445*5113495bSYour Name #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 446*5113495bSYour Name #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000034 447*5113495bSYour Name #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 448*5113495bSYour Name #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 449*5113495bSYour Name #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_OFFSET 0x00000038 450*5113495bSYour Name #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_LSB 0 451*5113495bSYour Name #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_MASK 0xffffffff 452*5113495bSYour Name #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000003c 453*5113495bSYour Name #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 454*5113495bSYour Name #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 455*5113495bSYour Name #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000040 456*5113495bSYour Name #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 457*5113495bSYour Name #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 458*5113495bSYour Name #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000044 459*5113495bSYour Name #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 460*5113495bSYour Name #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 461*5113495bSYour Name #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000048 462*5113495bSYour Name #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 463*5113495bSYour Name #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 464*5113495bSYour Name #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000004c 465*5113495bSYour Name #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 466*5113495bSYour Name #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 467*5113495bSYour Name #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000050 468*5113495bSYour Name #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 469*5113495bSYour Name #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 470*5113495bSYour Name #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000054 471*5113495bSYour Name #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 472*5113495bSYour Name #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 473*5113495bSYour Name #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000058 474*5113495bSYour Name #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 475*5113495bSYour Name #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 476*5113495bSYour Name #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000005c 477*5113495bSYour Name #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 478*5113495bSYour Name #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 479*5113495bSYour Name #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000060 480*5113495bSYour Name #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 481*5113495bSYour Name #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 482*5113495bSYour Name #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000064 483*5113495bSYour Name #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 484*5113495bSYour Name #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 485*5113495bSYour Name #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000068 486*5113495bSYour Name #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 487*5113495bSYour Name #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 488*5113495bSYour Name #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000006c 489*5113495bSYour Name #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 490*5113495bSYour Name #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 491*5113495bSYour Name #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000070 492*5113495bSYour Name #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 493*5113495bSYour Name #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 494*5113495bSYour Name #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000074 495*5113495bSYour Name #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 496*5113495bSYour Name #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 497*5113495bSYour Name #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000078 498*5113495bSYour Name #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 499*5113495bSYour Name #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 500*5113495bSYour Name 501*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 502*5113495bSYour Name 503*5113495bSYour Name Some PHY micro code status that can be put in here. 504*5113495bSYour Name Details of definition within SW specification 505*5113495bSYour Name 506*5113495bSYour Name This field can be used for debugging, FW - SW message 507*5113495bSYour Name exchange, etc. 508*5113495bSYour Name 509*5113495bSYour Name It could for example be a pointer to a DDR memory 510*5113495bSYour Name location where PHY FW put some debug info. 511*5113495bSYour Name 512*5113495bSYour Name <legal all> 513*5113495bSYour Name */ 514*5113495bSYour Name #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 515*5113495bSYour Name #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 516*5113495bSYour Name #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 517*5113495bSYour Name 518*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 519*5113495bSYour Name 520*5113495bSYour Name Some PHY micro code status that can be put in here. 521*5113495bSYour Name Details of definition within SW specification 522*5113495bSYour Name 523*5113495bSYour Name This field can be used for debugging, FW - SW message 524*5113495bSYour Name exchange, etc. 525*5113495bSYour Name 526*5113495bSYour Name It could for example be a pointer to a DDR memory 527*5113495bSYour Name location where PHY FW put some debug info. 528*5113495bSYour Name 529*5113495bSYour Name <legal all> 530*5113495bSYour Name */ 531*5113495bSYour Name #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 532*5113495bSYour Name #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 533*5113495bSYour Name #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 534*5113495bSYour Name 535*5113495bSYour Name 536*5113495bSYour Name #endif // _PHYRX_PKT_END_INFO_H_ 537