1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REO_DESTINATION_RING_H_ 20 #define _REO_DESTINATION_RING_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "buffer_addr_info.h" 25 #include "rx_mpdu_desc_info.h" 26 #include "rx_msdu_desc_info.h" 27 28 // ################ START SUMMARY ################# 29 // 30 // Dword Fields 31 // 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; 32 // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 33 // 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; 34 // 6 rx_reo_queue_desc_addr_31_0[31:0] 35 // 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] 36 // 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], reserved_8a[31:13] 37 // 9 reserved_9a[31:0] 38 // 10 reserved_10a[31:0] 39 // 11 reserved_11a[31:0] 40 // 12 reserved_12a[31:0] 41 // 13 reserved_13a[31:0] 42 // 14 reserved_14a[31:0] 43 // 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] 44 // 45 // ################ END SUMMARY ################# 46 47 #define NUM_OF_DWORDS_REO_DESTINATION_RING 16 48 49 struct reo_destination_ring { 50 struct buffer_addr_info buf_or_link_desc_addr_info; 51 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 52 struct rx_msdu_desc_info rx_msdu_desc_info_details; 53 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 54 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 55 reo_dest_buffer_type : 1, //[8] 56 reo_push_reason : 2, //[10:9] 57 reo_error_code : 5, //[15:11] 58 receive_queue_number : 16; //[31:16] 59 uint32_t soft_reorder_info_valid : 1, //[0] 60 reorder_opcode : 4, //[4:1] 61 reorder_slot_index : 8, //[12:5] 62 reserved_8a : 19; //[31:13] 63 uint32_t reserved_9a : 32; //[31:0] 64 uint32_t reserved_10a : 32; //[31:0] 65 uint32_t reserved_11a : 32; //[31:0] 66 uint32_t reserved_12a : 32; //[31:0] 67 uint32_t reserved_13a : 32; //[31:0] 68 uint32_t reserved_14a : 32; //[31:0] 69 uint32_t reserved_15 : 20, //[19:0] 70 ring_id : 8, //[27:20] 71 looping_count : 4; //[31:28] 72 }; 73 74 /* 75 76 struct buffer_addr_info buf_or_link_desc_addr_info 77 78 Consumer: REO/SW/FW 79 80 Producer: RXDMA 81 82 83 84 Details of the physical address of the a buffer or MSDU 85 link descriptor 86 87 struct rx_mpdu_desc_info rx_mpdu_desc_info_details 88 89 Consumer: REO/SW/FW 90 91 Producer: RXDMA 92 93 94 95 General information related to the MPDU that is passed 96 on from REO entrance ring to the REO destination ring 97 98 struct rx_msdu_desc_info rx_msdu_desc_info_details 99 100 General information related to the MSDU that is passed 101 on from RXDMA all the way to to the REO destination ring. 102 103 rx_reo_queue_desc_addr_31_0 104 105 Consumer: REO 106 107 Producer: RXDMA 108 109 110 111 Address (lower 32 bits) of the REO queue descriptor. 112 113 <legal all> 114 115 rx_reo_queue_desc_addr_39_32 116 117 Consumer: REO 118 119 Producer: RXDMA 120 121 122 123 Address (upper 8 bits) of the REO queue descriptor. 124 125 <legal all> 126 127 reo_dest_buffer_type 128 129 Indicates the type of address provided in the 130 'Buf_or_link_desc_addr_info' 131 132 133 134 <enum 0 MSDU_buf_address> The address of an MSDU buffer 135 136 <enum 1 MSDU_link_desc_address> The address of the MSDU 137 link descriptor. 138 139 140 141 <legal all> 142 143 reo_push_reason 144 145 Indicates why REO pushed the frame to this exit ring 146 147 148 149 <enum 0 reo_error_detected> Reo detected an error an 150 pushed this frame to this queue 151 152 <enum 1 reo_routing_instruction> Reo pushed the frame to 153 this queue per received routing instructions. No error 154 within REO was detected 155 156 157 158 159 160 <legal 0 - 1> 161 162 reo_error_code 163 164 Field only valid when 'Reo_push_reason' set to 165 'reo_error_detected'. 166 167 168 169 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 170 provided in the REO_ENTRANCE ring is set to 0 171 172 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 173 valid bit is NOT set 174 175 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 176 session having been setup. 177 178 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 179 SSN, Retry bit set: duplicate frame 180 181 <enum 4 ba_duplicate> BA session, duplicate frame 182 183 <enum 5 regular_frame_2k_jump> A normal (management/data 184 frame) received with 2K jump in SN 185 186 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 187 in SSN 188 189 <enum 7 regular_frame_OOR> A normal (management/data 190 frame) received with SN falling within the OOR window 191 192 <enum 8 bar_frame_OOR> A bar received with SSN falling 193 within the OOR window 194 195 <enum 9 bar_frame_no_ba_session> A bar received without 196 a BA session 197 198 <enum 10 bar_frame_sn_equals_ssn> A bar received with 199 SSN equal to SN 200 201 <enum 11 pn_check_failed> PN Check Failed packet. 202 203 <enum 12 2k_error_handling_flag_set> Frame is forwarded 204 as a result of the 'Seq_2k_error_detected_flag' been set in 205 the REO Queue descriptor 206 207 <enum 13 pn_error_handling_flag_set> Frame is forwarded 208 as a result of the 'pn_error_detected_flag' been set in the 209 REO Queue descriptor 210 211 <enum 14 queue_descriptor_blocked_set> Frame is 212 forwarded as a result of the queue descriptor(address) being 213 blocked as SW/FW seems to be currently in the process of 214 making updates to this descriptor... 215 216 217 218 <legal 0-14> 219 220 receive_queue_number 221 222 This field indicates the REO MPDU reorder queue ID from 223 which this frame originated. This field is populated from a 224 field with the same name in the RX_REO_QUEUE descriptor. 225 226 <legal all> 227 228 soft_reorder_info_valid 229 230 When set, REO has been instructed to not perform the 231 actual re-ordering of frames for this queue, but just to 232 insert the reorder opcodes 233 234 <legal all> 235 236 reorder_opcode 237 238 Field is valid when 'Soft_reorder_info_valid' is set. 239 This field is always valid for debug purpose as well. 240 241 Details are in the MLD. 242 243 244 245 <enum 0 invalid> 246 247 <enum 1 fwdcur_fwdbuf> 248 249 <enum 2 fwdbuf_fwdcur> 250 251 <enum 3 qcur> 252 253 <enum 4 fwdbuf_qcur> 254 255 <enum 5 fwdbuf_drop> 256 257 <enum 6 fwdall_drop> 258 259 <enum 7 fwdall_qcur> 260 261 <enum 8 reserved_reo_opcode_1> 262 263 <enum 9 dropcur> the error reason code is in 264 reo_error_code field. 265 266 <enum 10 reserved_reo_opcode_2> 267 268 <enum 11 reserved_reo_opcode_3> 269 270 <enum 12 reserved_reo_opcode_4> 271 272 <enum 13 reserved_reo_opcode_5> 273 274 <enum 14 reserved_reo_opcode_6> 275 276 <enum 15 reserved_reo_opcode_7> 277 278 279 280 <legal all> 281 282 reorder_slot_index 283 284 Field only valid when 'Soft_reorder_info_valid' is set. 285 286 287 288 TODO: add description 289 290 291 292 <legal all> 293 294 reserved_8a 295 296 <legal 0> 297 298 reserved_9a 299 300 <legal 0> 301 302 reserved_10a 303 304 <legal 0> 305 306 reserved_11a 307 308 <legal 0> 309 310 reserved_12a 311 312 <legal 0> 313 314 reserved_13a 315 316 <legal 0> 317 318 reserved_14a 319 320 <legal 0> 321 322 reserved_15 323 324 <legal 0> 325 326 ring_id 327 328 The buffer pointer ring ID. 329 330 0 refers to the IDLE ring 331 332 1 - N refers to other rings 333 334 335 336 Helps with debugging when dumping ring contents. 337 338 <legal all> 339 340 looping_count 341 342 A count value that indicates the number of times the 343 producer of entries into this Ring has looped around the 344 ring. 345 346 At initialization time, this value is set to 0. On the 347 first loop, this value is set to 1. After the max value is 348 reached allowed by the number of bits for this field, the 349 count value continues with 0 again. 350 351 In case SW is the consumer of the ring entries, it can 352 use this field to figure out up to where the producer of 353 entries has created new entries. This eliminates the need to 354 check where the head pointer' of the ring is located once 355 the SW starts processing an interrupt indicating that new 356 entries have been put into this ring... 357 358 359 360 Also note that SW if it wants only needs to look at the 361 LSB bit of this count value. 362 363 <legal all> 364 */ 365 366 #define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000000 367 #define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28 368 #define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff 369 #define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 370 #define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28 371 #define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff 372 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008 373 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28 374 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff 375 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c 376 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28 377 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff 378 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000010 379 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28 380 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff 381 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000014 382 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28 383 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff 384 385 /* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 386 387 Consumer: REO 388 389 Producer: RXDMA 390 391 392 393 Address (lower 32 bits) of the REO queue descriptor. 394 395 <legal all> 396 */ 397 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 398 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 399 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 400 401 /* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 402 403 Consumer: REO 404 405 Producer: RXDMA 406 407 408 409 Address (upper 8 bits) of the REO queue descriptor. 410 411 <legal all> 412 */ 413 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c 414 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 415 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 416 417 /* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE 418 419 Indicates the type of address provided in the 420 'Buf_or_link_desc_addr_info' 421 422 423 424 <enum 0 MSDU_buf_address> The address of an MSDU buffer 425 426 <enum 1 MSDU_link_desc_address> The address of the MSDU 427 link descriptor. 428 429 430 431 <legal all> 432 */ 433 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c 434 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 435 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 436 437 /* Description REO_DESTINATION_RING_7_REO_PUSH_REASON 438 439 Indicates why REO pushed the frame to this exit ring 440 441 442 443 <enum 0 reo_error_detected> Reo detected an error an 444 pushed this frame to this queue 445 446 <enum 1 reo_routing_instruction> Reo pushed the frame to 447 this queue per received routing instructions. No error 448 within REO was detected 449 450 451 452 453 454 <legal 0 - 1> 455 */ 456 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c 457 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 458 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 459 460 /* Description REO_DESTINATION_RING_7_REO_ERROR_CODE 461 462 Field only valid when 'Reo_push_reason' set to 463 'reo_error_detected'. 464 465 466 467 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 468 provided in the REO_ENTRANCE ring is set to 0 469 470 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 471 valid bit is NOT set 472 473 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 474 session having been setup. 475 476 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 477 SSN, Retry bit set: duplicate frame 478 479 <enum 4 ba_duplicate> BA session, duplicate frame 480 481 <enum 5 regular_frame_2k_jump> A normal (management/data 482 frame) received with 2K jump in SN 483 484 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 485 in SSN 486 487 <enum 7 regular_frame_OOR> A normal (management/data 488 frame) received with SN falling within the OOR window 489 490 <enum 8 bar_frame_OOR> A bar received with SSN falling 491 within the OOR window 492 493 <enum 9 bar_frame_no_ba_session> A bar received without 494 a BA session 495 496 <enum 10 bar_frame_sn_equals_ssn> A bar received with 497 SSN equal to SN 498 499 <enum 11 pn_check_failed> PN Check Failed packet. 500 501 <enum 12 2k_error_handling_flag_set> Frame is forwarded 502 as a result of the 'Seq_2k_error_detected_flag' been set in 503 the REO Queue descriptor 504 505 <enum 13 pn_error_handling_flag_set> Frame is forwarded 506 as a result of the 'pn_error_detected_flag' been set in the 507 REO Queue descriptor 508 509 <enum 14 queue_descriptor_blocked_set> Frame is 510 forwarded as a result of the queue descriptor(address) being 511 blocked as SW/FW seems to be currently in the process of 512 making updates to this descriptor... 513 514 515 516 <legal 0-14> 517 */ 518 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c 519 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 520 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 521 522 /* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER 523 524 This field indicates the REO MPDU reorder queue ID from 525 which this frame originated. This field is populated from a 526 field with the same name in the RX_REO_QUEUE descriptor. 527 528 <legal all> 529 */ 530 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c 531 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 532 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 533 534 /* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID 535 536 When set, REO has been instructed to not perform the 537 actual re-ordering of frames for this queue, but just to 538 insert the reorder opcodes 539 540 <legal all> 541 */ 542 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 543 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 544 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 545 546 /* Description REO_DESTINATION_RING_8_REORDER_OPCODE 547 548 Field is valid when 'Soft_reorder_info_valid' is set. 549 This field is always valid for debug purpose as well. 550 551 Details are in the MLD. 552 553 554 555 <enum 0 invalid> 556 557 <enum 1 fwdcur_fwdbuf> 558 559 <enum 2 fwdbuf_fwdcur> 560 561 <enum 3 qcur> 562 563 <enum 4 fwdbuf_qcur> 564 565 <enum 5 fwdbuf_drop> 566 567 <enum 6 fwdall_drop> 568 569 <enum 7 fwdall_qcur> 570 571 <enum 8 reserved_reo_opcode_1> 572 573 <enum 9 dropcur> the error reason code is in 574 reo_error_code field. 575 576 <enum 10 reserved_reo_opcode_2> 577 578 <enum 11 reserved_reo_opcode_3> 579 580 <enum 12 reserved_reo_opcode_4> 581 582 <enum 13 reserved_reo_opcode_5> 583 584 <enum 14 reserved_reo_opcode_6> 585 586 <enum 15 reserved_reo_opcode_7> 587 588 589 590 <legal all> 591 */ 592 #define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 593 #define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 594 #define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e 595 596 /* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX 597 598 Field only valid when 'Soft_reorder_info_valid' is set. 599 600 601 602 TODO: add description 603 604 605 606 <legal all> 607 */ 608 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 609 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 610 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 611 612 /* Description REO_DESTINATION_RING_8_RESERVED_8A 613 614 <legal 0> 615 */ 616 #define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 617 #define REO_DESTINATION_RING_8_RESERVED_8A_LSB 13 618 #define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffffe000 619 620 /* Description REO_DESTINATION_RING_9_RESERVED_9A 621 622 <legal 0> 623 */ 624 #define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET 0x00000024 625 #define REO_DESTINATION_RING_9_RESERVED_9A_LSB 0 626 #define REO_DESTINATION_RING_9_RESERVED_9A_MASK 0xffffffff 627 628 /* Description REO_DESTINATION_RING_10_RESERVED_10A 629 630 <legal 0> 631 */ 632 #define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 633 #define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 634 #define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff 635 636 /* Description REO_DESTINATION_RING_11_RESERVED_11A 637 638 <legal 0> 639 */ 640 #define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c 641 #define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 642 #define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff 643 644 /* Description REO_DESTINATION_RING_12_RESERVED_12A 645 646 <legal 0> 647 */ 648 #define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 649 #define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 650 #define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff 651 652 /* Description REO_DESTINATION_RING_13_RESERVED_13A 653 654 <legal 0> 655 */ 656 #define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 657 #define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 658 #define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff 659 660 /* Description REO_DESTINATION_RING_14_RESERVED_14A 661 662 <legal 0> 663 */ 664 #define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 665 #define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 666 #define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff 667 668 /* Description REO_DESTINATION_RING_15_RESERVED_15 669 670 <legal 0> 671 */ 672 #define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c 673 #define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 674 #define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff 675 676 /* Description REO_DESTINATION_RING_15_RING_ID 677 678 The buffer pointer ring ID. 679 680 0 refers to the IDLE ring 681 682 1 - N refers to other rings 683 684 685 686 Helps with debugging when dumping ring contents. 687 688 <legal all> 689 */ 690 #define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c 691 #define REO_DESTINATION_RING_15_RING_ID_LSB 20 692 #define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 693 694 /* Description REO_DESTINATION_RING_15_LOOPING_COUNT 695 696 A count value that indicates the number of times the 697 producer of entries into this Ring has looped around the 698 ring. 699 700 At initialization time, this value is set to 0. On the 701 first loop, this value is set to 1. After the max value is 702 reached allowed by the number of bits for this field, the 703 count value continues with 0 again. 704 705 In case SW is the consumer of the ring entries, it can 706 use this field to figure out up to where the producer of 707 entries has created new entries. This eliminates the need to 708 check where the head pointer' of the ring is located once 709 the SW starts processing an interrupt indicating that new 710 entries have been put into this ring... 711 712 713 714 Also note that SW if it wants only needs to look at the 715 LSB bit of this count value. 716 717 <legal all> 718 */ 719 #define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c 720 #define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 721 #define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 722 723 724 #endif // _REO_DESTINATION_RING_H_ 725