xref: /wlan-driver/fw-api/hw/qca6290/11ax/v2/reo_flush_timeout_list_status.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
20 #define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
21 #if !defined(__ASSEMBLER__)
22 #endif
23 
24 #include "uniform_reo_status_header.h"
25 
26 // ################ START SUMMARY #################
27 //
28 //	Dword	Fields
29 //	0-1	struct uniform_reo_status_header status_header;
30 //	2	error_detected[0], timout_list_empty[1], reserved_2a[31:2]
31 //	3	release_desc_count[15:0], forward_buf_count[31:16]
32 //	4	reserved_4a[31:0]
33 //	5	reserved_5a[31:0]
34 //	6	reserved_6a[31:0]
35 //	7	reserved_7a[31:0]
36 //	8	reserved_8a[31:0]
37 //	9	reserved_9a[31:0]
38 //	10	reserved_10a[31:0]
39 //	11	reserved_11a[31:0]
40 //	12	reserved_12a[31:0]
41 //	13	reserved_13a[31:0]
42 //	14	reserved_14a[31:0]
43 //	15	reserved_15a[31:0]
44 //	16	reserved_16a[31:0]
45 //	17	reserved_17a[31:0]
46 //	18	reserved_18a[31:0]
47 //	19	reserved_19a[31:0]
48 //	20	reserved_20a[31:0]
49 //	21	reserved_21a[31:0]
50 //	22	reserved_22a[31:0]
51 //	23	reserved_23a[31:0]
52 //	24	reserved_24a[27:0], looping_count[31:28]
53 //
54 // ################ END SUMMARY #################
55 
56 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
57 
58 struct reo_flush_timeout_list_status {
59     struct            uniform_reo_status_header                       status_header;
60              uint32_t error_detected                  :  1, //[0]
61                       timout_list_empty               :  1, //[1]
62                       reserved_2a                     : 30; //[31:2]
63              uint32_t release_desc_count              : 16, //[15:0]
64                       forward_buf_count               : 16; //[31:16]
65              uint32_t reserved_4a                     : 32; //[31:0]
66              uint32_t reserved_5a                     : 32; //[31:0]
67              uint32_t reserved_6a                     : 32; //[31:0]
68              uint32_t reserved_7a                     : 32; //[31:0]
69              uint32_t reserved_8a                     : 32; //[31:0]
70              uint32_t reserved_9a                     : 32; //[31:0]
71              uint32_t reserved_10a                    : 32; //[31:0]
72              uint32_t reserved_11a                    : 32; //[31:0]
73              uint32_t reserved_12a                    : 32; //[31:0]
74              uint32_t reserved_13a                    : 32; //[31:0]
75              uint32_t reserved_14a                    : 32; //[31:0]
76              uint32_t reserved_15a                    : 32; //[31:0]
77              uint32_t reserved_16a                    : 32; //[31:0]
78              uint32_t reserved_17a                    : 32; //[31:0]
79              uint32_t reserved_18a                    : 32; //[31:0]
80              uint32_t reserved_19a                    : 32; //[31:0]
81              uint32_t reserved_20a                    : 32; //[31:0]
82              uint32_t reserved_21a                    : 32; //[31:0]
83              uint32_t reserved_22a                    : 32; //[31:0]
84              uint32_t reserved_23a                    : 32; //[31:0]
85              uint32_t reserved_24a                    : 28, //[27:0]
86                       looping_count                   :  4; //[31:28]
87 };
88 
89 /*
90 
91 struct uniform_reo_status_header status_header
92 
93 			Consumer: SW
94 
95 			Producer: REO
96 
97 
98 
99 			Details that can link this status with the original
100 			command. It also contains info on how long REO took to
101 			execute this command.
102 
103 error_detected
104 
105 			0: No error has been detected while executing this
106 			command
107 
108 			1: command not properly executed and returned with an
109 			error
110 
111 
112 
113 			NOTE: Current no error is defined, but field is put in
114 			place to avoid data structure changes in future...
115 
116 timout_list_empty
117 
118 			When set, REO has depleted the timeout list and all
119 			entries are gone.
120 
121 			<legal all>
122 
123 reserved_2a
124 
125 			<legal 0>
126 
127 release_desc_count
128 
129 			Consumer: REO
130 
131 			Producer: SW
132 
133 
134 
135 			The number of link descriptors released
136 
137 			<legal all>
138 
139 forward_buf_count
140 
141 			Consumer: REO
142 
143 			Producer: SW
144 
145 
146 
147 			The number of buffers forwarded to the REO destination
148 			rings
149 
150 			<legal all>
151 
152 reserved_4a
153 
154 			<legal 0>
155 
156 reserved_5a
157 
158 			<legal 0>
159 
160 reserved_6a
161 
162 			<legal 0>
163 
164 reserved_7a
165 
166 			<legal 0>
167 
168 reserved_8a
169 
170 			<legal 0>
171 
172 reserved_9a
173 
174 			<legal 0>
175 
176 reserved_10a
177 
178 			<legal 0>
179 
180 reserved_11a
181 
182 			<legal 0>
183 
184 reserved_12a
185 
186 			<legal 0>
187 
188 reserved_13a
189 
190 			<legal 0>
191 
192 reserved_14a
193 
194 			<legal 0>
195 
196 reserved_15a
197 
198 			<legal 0>
199 
200 reserved_16a
201 
202 			<legal 0>
203 
204 reserved_17a
205 
206 			<legal 0>
207 
208 reserved_18a
209 
210 			<legal 0>
211 
212 reserved_19a
213 
214 			<legal 0>
215 
216 reserved_20a
217 
218 			<legal 0>
219 
220 reserved_21a
221 
222 			<legal 0>
223 
224 reserved_22a
225 
226 			<legal 0>
227 
228 reserved_23a
229 
230 			<legal 0>
231 
232 reserved_24a
233 
234 			<legal 0>
235 
236 looping_count
237 
238 			A count value that indicates the number of times the
239 			producer of entries into this Ring has looped around the
240 			ring.
241 
242 			At initialization time, this value is set to 0. On the
243 			first loop, this value is set to 1. After the max value is
244 			reached allowed by the number of bits for this field, the
245 			count value continues with 0 again.
246 
247 
248 
249 			In case SW is the consumer of the ring entries, it can
250 			use this field to figure out up to where the producer of
251 			entries has created new entries. This eliminates the need to
252 			check where the head pointer' of the ring is located once
253 			the SW starts processing an interrupt indicating that new
254 			entries have been put into this ring...
255 
256 
257 
258 			Also note that SW if it wants only needs to look at the
259 			LSB bit of this count value.
260 
261 			<legal all>
262 */
263 
264 #define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
265 #define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
266 #define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
267 #define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
268 #define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
269 #define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
270 
271 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED
272 
273 			0: No error has been detected while executing this
274 			command
275 
276 			1: command not properly executed and returned with an
277 			error
278 
279 
280 
281 			NOTE: Current no error is defined, but field is put in
282 			place to avoid data structure changes in future...
283 */
284 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET        0x00000008
285 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB           0
286 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK          0x00000001
287 
288 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY
289 
290 			When set, REO has depleted the timeout list and all
291 			entries are gone.
292 
293 			<legal all>
294 */
295 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET     0x00000008
296 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB        1
297 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK       0x00000002
298 
299 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A
300 
301 			<legal 0>
302 */
303 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET           0x00000008
304 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB              2
305 #define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK             0xfffffffc
306 
307 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT
308 
309 			Consumer: REO
310 
311 			Producer: SW
312 
313 
314 
315 			The number of link descriptors released
316 
317 			<legal all>
318 */
319 #define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET    0x0000000c
320 #define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB       0
321 #define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK      0x0000ffff
322 
323 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT
324 
325 			Consumer: REO
326 
327 			Producer: SW
328 
329 
330 
331 			The number of buffers forwarded to the REO destination
332 			rings
333 
334 			<legal all>
335 */
336 #define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET     0x0000000c
337 #define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB        16
338 #define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK       0xffff0000
339 
340 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A
341 
342 			<legal 0>
343 */
344 #define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET           0x00000010
345 #define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB              0
346 #define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK             0xffffffff
347 
348 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A
349 
350 			<legal 0>
351 */
352 #define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET           0x00000014
353 #define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB              0
354 #define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK             0xffffffff
355 
356 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A
357 
358 			<legal 0>
359 */
360 #define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET           0x00000018
361 #define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB              0
362 #define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK             0xffffffff
363 
364 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A
365 
366 			<legal 0>
367 */
368 #define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET           0x0000001c
369 #define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB              0
370 #define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK             0xffffffff
371 
372 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A
373 
374 			<legal 0>
375 */
376 #define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET           0x00000020
377 #define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB              0
378 #define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK             0xffffffff
379 
380 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A
381 
382 			<legal 0>
383 */
384 #define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET           0x00000024
385 #define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB              0
386 #define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK             0xffffffff
387 
388 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A
389 
390 			<legal 0>
391 */
392 #define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET         0x00000028
393 #define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB            0
394 #define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK           0xffffffff
395 
396 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A
397 
398 			<legal 0>
399 */
400 #define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET         0x0000002c
401 #define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB            0
402 #define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK           0xffffffff
403 
404 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A
405 
406 			<legal 0>
407 */
408 #define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET         0x00000030
409 #define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB            0
410 #define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK           0xffffffff
411 
412 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A
413 
414 			<legal 0>
415 */
416 #define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET         0x00000034
417 #define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB            0
418 #define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK           0xffffffff
419 
420 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A
421 
422 			<legal 0>
423 */
424 #define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET         0x00000038
425 #define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB            0
426 #define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK           0xffffffff
427 
428 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A
429 
430 			<legal 0>
431 */
432 #define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET         0x0000003c
433 #define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB            0
434 #define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK           0xffffffff
435 
436 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A
437 
438 			<legal 0>
439 */
440 #define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET         0x00000040
441 #define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB            0
442 #define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK           0xffffffff
443 
444 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A
445 
446 			<legal 0>
447 */
448 #define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET         0x00000044
449 #define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB            0
450 #define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK           0xffffffff
451 
452 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A
453 
454 			<legal 0>
455 */
456 #define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET         0x00000048
457 #define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB            0
458 #define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK           0xffffffff
459 
460 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A
461 
462 			<legal 0>
463 */
464 #define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET         0x0000004c
465 #define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB            0
466 #define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK           0xffffffff
467 
468 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A
469 
470 			<legal 0>
471 */
472 #define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET         0x00000050
473 #define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB            0
474 #define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK           0xffffffff
475 
476 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A
477 
478 			<legal 0>
479 */
480 #define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET         0x00000054
481 #define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB            0
482 #define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK           0xffffffff
483 
484 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A
485 
486 			<legal 0>
487 */
488 #define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET         0x00000058
489 #define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB            0
490 #define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK           0xffffffff
491 
492 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A
493 
494 			<legal 0>
495 */
496 #define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET         0x0000005c
497 #define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB            0
498 #define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK           0xffffffff
499 
500 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A
501 
502 			<legal 0>
503 */
504 #define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET         0x00000060
505 #define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB            0
506 #define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK           0x0fffffff
507 
508 /* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT
509 
510 			A count value that indicates the number of times the
511 			producer of entries into this Ring has looped around the
512 			ring.
513 
514 			At initialization time, this value is set to 0. On the
515 			first loop, this value is set to 1. After the max value is
516 			reached allowed by the number of bits for this field, the
517 			count value continues with 0 again.
518 
519 
520 
521 			In case SW is the consumer of the ring entries, it can
522 			use this field to figure out up to where the producer of
523 			entries has created new entries. This eliminates the need to
524 			check where the head pointer' of the ring is located once
525 			the SW starts processing an interrupt indicating that new
526 			entries have been put into this ring...
527 
528 
529 
530 			Also note that SW if it wants only needs to look at the
531 			LSB bit of this count value.
532 
533 			<legal all>
534 */
535 #define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET        0x00000060
536 #define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB           28
537 #define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK          0xf0000000
538 
539 
540 #endif // _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
541