1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 20 #define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_status_header.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0-1 struct uniform_reo_status_header status_header; 30 // 2 reserved_2a[31:0] 31 // 3 reserved_3a[31:0] 32 // 4 reserved_4a[31:0] 33 // 5 reserved_5a[31:0] 34 // 6 reserved_6a[31:0] 35 // 7 reserved_7a[31:0] 36 // 8 reserved_8a[31:0] 37 // 9 reserved_9a[31:0] 38 // 10 reserved_10a[31:0] 39 // 11 reserved_11a[31:0] 40 // 12 reserved_12a[31:0] 41 // 13 reserved_13a[31:0] 42 // 14 reserved_14a[31:0] 43 // 15 reserved_15a[31:0] 44 // 16 reserved_16a[31:0] 45 // 17 reserved_17a[31:0] 46 // 18 reserved_18a[31:0] 47 // 19 reserved_19a[31:0] 48 // 20 reserved_20a[31:0] 49 // 21 reserved_21a[31:0] 50 // 22 reserved_22a[31:0] 51 // 23 reserved_23a[31:0] 52 // 24 reserved_24a[27:0], looping_count[31:28] 53 // 54 // ################ END SUMMARY ################# 55 56 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25 57 58 struct reo_update_rx_reo_queue_status { 59 struct uniform_reo_status_header status_header; 60 uint32_t reserved_2a : 32; //[31:0] 61 uint32_t reserved_3a : 32; //[31:0] 62 uint32_t reserved_4a : 32; //[31:0] 63 uint32_t reserved_5a : 32; //[31:0] 64 uint32_t reserved_6a : 32; //[31:0] 65 uint32_t reserved_7a : 32; //[31:0] 66 uint32_t reserved_8a : 32; //[31:0] 67 uint32_t reserved_9a : 32; //[31:0] 68 uint32_t reserved_10a : 32; //[31:0] 69 uint32_t reserved_11a : 32; //[31:0] 70 uint32_t reserved_12a : 32; //[31:0] 71 uint32_t reserved_13a : 32; //[31:0] 72 uint32_t reserved_14a : 32; //[31:0] 73 uint32_t reserved_15a : 32; //[31:0] 74 uint32_t reserved_16a : 32; //[31:0] 75 uint32_t reserved_17a : 32; //[31:0] 76 uint32_t reserved_18a : 32; //[31:0] 77 uint32_t reserved_19a : 32; //[31:0] 78 uint32_t reserved_20a : 32; //[31:0] 79 uint32_t reserved_21a : 32; //[31:0] 80 uint32_t reserved_22a : 32; //[31:0] 81 uint32_t reserved_23a : 32; //[31:0] 82 uint32_t reserved_24a : 28, //[27:0] 83 looping_count : 4; //[31:28] 84 }; 85 86 /* 87 88 struct uniform_reo_status_header status_header 89 90 Consumer: SW 91 92 Producer: REO 93 94 95 96 Details that can link this status with the original 97 command. It also contains info on how long REO took to 98 execute this command. 99 100 reserved_2a 101 102 <legal 0> 103 104 reserved_3a 105 106 <legal 0> 107 108 reserved_4a 109 110 <legal 0> 111 112 reserved_5a 113 114 <legal 0> 115 116 reserved_6a 117 118 <legal 0> 119 120 reserved_7a 121 122 <legal 0> 123 124 reserved_8a 125 126 <legal 0> 127 128 reserved_9a 129 130 <legal 0> 131 132 reserved_10a 133 134 <legal 0> 135 136 reserved_11a 137 138 <legal 0> 139 140 reserved_12a 141 142 <legal 0> 143 144 reserved_13a 145 146 <legal 0> 147 148 reserved_14a 149 150 <legal 0> 151 152 reserved_15a 153 154 <legal 0> 155 156 reserved_16a 157 158 <legal 0> 159 160 reserved_17a 161 162 <legal 0> 163 164 reserved_18a 165 166 <legal 0> 167 168 reserved_19a 169 170 <legal 0> 171 172 reserved_20a 173 174 <legal 0> 175 176 reserved_21a 177 178 <legal 0> 179 180 reserved_22a 181 182 <legal 0> 183 184 reserved_23a 185 186 <legal 0> 187 188 reserved_24a 189 190 <legal 0> 191 192 looping_count 193 194 A count value that indicates the number of times the 195 producer of entries into this Ring has looped around the 196 ring. 197 198 At initialization time, this value is set to 0. On the 199 first loop, this value is set to 1. After the max value is 200 reached allowed by the number of bits for this field, the 201 count value continues with 0 again. 202 203 204 205 In case SW is the consumer of the ring entries, it can 206 use this field to figure out up to where the producer of 207 entries has created new entries. This eliminates the need to 208 check where the head pointer' of the ring is located once 209 the SW starts processing an interrupt indicating that new 210 entries have been put into this ring... 211 212 213 214 Also note that SW if it wants only needs to look at the 215 LSB bit of this count value. 216 217 <legal all> 218 */ 219 220 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000 221 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 222 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff 223 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004 224 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 225 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff 226 227 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A 228 229 <legal 0> 230 */ 231 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 232 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0 233 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff 234 235 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A 236 237 <legal 0> 238 */ 239 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c 240 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0 241 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff 242 243 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A 244 245 <legal 0> 246 */ 247 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 248 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0 249 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff 250 251 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A 252 253 <legal 0> 254 */ 255 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 256 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0 257 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff 258 259 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A 260 261 <legal 0> 262 */ 263 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 264 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0 265 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff 266 267 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A 268 269 <legal 0> 270 */ 271 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c 272 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0 273 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff 274 275 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A 276 277 <legal 0> 278 */ 279 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 280 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0 281 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff 282 283 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A 284 285 <legal 0> 286 */ 287 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 288 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0 289 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff 290 291 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A 292 293 <legal 0> 294 */ 295 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 296 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0 297 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff 298 299 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A 300 301 <legal 0> 302 */ 303 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c 304 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0 305 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff 306 307 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A 308 309 <legal 0> 310 */ 311 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 312 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0 313 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff 314 315 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A 316 317 <legal 0> 318 */ 319 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 320 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0 321 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff 322 323 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A 324 325 <legal 0> 326 */ 327 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 328 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0 329 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff 330 331 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A 332 333 <legal 0> 334 */ 335 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c 336 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0 337 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff 338 339 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A 340 341 <legal 0> 342 */ 343 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 344 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0 345 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff 346 347 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A 348 349 <legal 0> 350 */ 351 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 352 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0 353 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff 354 355 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A 356 357 <legal 0> 358 */ 359 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 360 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0 361 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff 362 363 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A 364 365 <legal 0> 366 */ 367 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c 368 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0 369 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff 370 371 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A 372 373 <legal 0> 374 */ 375 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 376 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0 377 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff 378 379 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A 380 381 <legal 0> 382 */ 383 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 384 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0 385 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff 386 387 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A 388 389 <legal 0> 390 */ 391 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 392 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0 393 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff 394 395 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A 396 397 <legal 0> 398 */ 399 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c 400 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0 401 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff 402 403 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A 404 405 <legal 0> 406 */ 407 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 408 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0 409 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff 410 411 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT 412 413 A count value that indicates the number of times the 414 producer of entries into this Ring has looped around the 415 ring. 416 417 At initialization time, this value is set to 0. On the 418 first loop, this value is set to 1. After the max value is 419 reached allowed by the number of bits for this field, the 420 count value continues with 0 again. 421 422 423 424 In case SW is the consumer of the ring entries, it can 425 use this field to figure out up to where the producer of 426 entries has created new entries. This eliminates the need to 427 check where the head pointer' of the ring is located once 428 the SW starts processing an interrupt indicating that new 429 entries have been put into this ring... 430 431 432 433 Also note that SW if it wants only needs to look at the 434 LSB bit of this count value. 435 436 <legal all> 437 */ 438 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 439 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 440 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 441 442 443 #endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 444