1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _RX_MPDU_END_H_ 20 #define _RX_MPDU_END_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 29 // 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] 30 // 31 // ################ END SUMMARY ################# 32 33 #define NUM_OF_DWORDS_RX_MPDU_END 2 34 35 struct rx_mpdu_end { 36 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 37 sw_frame_group_id : 7, //[8:2] 38 reserved_0 : 7, //[15:9] 39 phy_ppdu_id : 16; //[31:16] 40 uint32_t reserved_1a : 11, //[10:0] 41 unsup_ktype_short_frame : 1, //[11] 42 rx_in_tx_decrypt_byp : 1, //[12] 43 overflow_err : 1, //[13] 44 mpdu_length_err : 1, //[14] 45 tkip_mic_err : 1, //[15] 46 decrypt_err : 1, //[16] 47 unencrypted_frame_err : 1, //[17] 48 pn_fields_contain_valid_info : 1, //[18] 49 fcs_err : 1, //[19] 50 msdu_length_err : 1, //[20] 51 rxdma0_destination_ring : 2, //[22:21] 52 rxdma1_destination_ring : 2, //[24:23] 53 decrypt_status_code : 3, //[27:25] 54 rx_bitmap_not_updated : 1, //[28] 55 reserved_1b : 3; //[31:29] 56 }; 57 58 /* 59 60 rxpcu_mpdu_filter_in_category 61 62 Field indicates what the reason was that this MPDU frame 63 was allowed to come into the receive path by RXPCU 64 65 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 66 frame filter programming of rxpcu 67 68 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 69 regular frame filter and would have been dropped, were it 70 not for the frame fitting into the 'monitor_client' 71 category. 72 73 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 74 regular frame filter and also did not pass the 75 rxpcu_monitor_client filter. It would have been dropped 76 accept that it did pass the 'monitor_other' category. 77 78 <legal 0-2> 79 80 sw_frame_group_id 81 82 SW processes frames based on certain classifications. 83 This field indicates to what sw classification this MPDU is 84 mapped. 85 86 The classification is given in priority order 87 88 89 90 <enum 0 sw_frame_group_NDP_frame> 91 92 93 94 <enum 1 sw_frame_group_Multicast_data> 95 96 <enum 2 sw_frame_group_Unicast_data> 97 98 <enum 3 sw_frame_group_Null_data > This includes mpdus 99 of type Data Null as well as QoS Data Null 100 101 102 103 <enum 4 sw_frame_group_mgmt_0000 > 104 105 <enum 5 sw_frame_group_mgmt_0001 > 106 107 <enum 6 sw_frame_group_mgmt_0010 > 108 109 <enum 7 sw_frame_group_mgmt_0011 > 110 111 <enum 8 sw_frame_group_mgmt_0100 > 112 113 <enum 9 sw_frame_group_mgmt_0101 > 114 115 <enum 10 sw_frame_group_mgmt_0110 > 116 117 <enum 11 sw_frame_group_mgmt_0111 > 118 119 <enum 12 sw_frame_group_mgmt_1000 > 120 121 <enum 13 sw_frame_group_mgmt_1001 > 122 123 <enum 14 sw_frame_group_mgmt_1010 > 124 125 <enum 15 sw_frame_group_mgmt_1011 > 126 127 <enum 16 sw_frame_group_mgmt_1100 > 128 129 <enum 17 sw_frame_group_mgmt_1101 > 130 131 <enum 18 sw_frame_group_mgmt_1110 > 132 133 <enum 19 sw_frame_group_mgmt_1111 > 134 135 136 137 <enum 20 sw_frame_group_ctrl_0000 > 138 139 <enum 21 sw_frame_group_ctrl_0001 > 140 141 <enum 22 sw_frame_group_ctrl_0010 > 142 143 <enum 23 sw_frame_group_ctrl_0011 > 144 145 <enum 24 sw_frame_group_ctrl_0100 > 146 147 <enum 25 sw_frame_group_ctrl_0101 > 148 149 <enum 26 sw_frame_group_ctrl_0110 > 150 151 <enum 27 sw_frame_group_ctrl_0111 > 152 153 <enum 28 sw_frame_group_ctrl_1000 > 154 155 <enum 29 sw_frame_group_ctrl_1001 > 156 157 <enum 30 sw_frame_group_ctrl_1010 > 158 159 <enum 31 sw_frame_group_ctrl_1011 > 160 161 <enum 32 sw_frame_group_ctrl_1100 > 162 163 <enum 33 sw_frame_group_ctrl_1101 > 164 165 <enum 34 sw_frame_group_ctrl_1110 > 166 167 <enum 35 sw_frame_group_ctrl_1111 > 168 169 170 171 <enum 36 sw_frame_group_unsupported> This covers type 3 172 and protocol version != 0 173 174 175 176 177 178 179 <legal 0-37> 180 181 reserved_0 182 183 <legal 0> 184 185 phy_ppdu_id 186 187 A ppdu counter value that PHY increments for every PPDU 188 received. The counter value wraps around 189 190 <legal all> 191 192 reserved_1a 193 194 <legal 0> 195 196 unsup_ktype_short_frame 197 198 This bit will be '1' when WEP or TKIP or WAPI key type 199 is received for 11ah short frame. Crypto will bypass the 200 received packet without decryption to RxOLE after setting 201 this bit. 202 203 rx_in_tx_decrypt_byp 204 205 Indicates that RX packet is not decrypted as Crypto is 206 busy with TX packet processing. 207 208 overflow_err 209 210 RXPCU Receive FIFO ran out of space to receive the full 211 MPDU. Therefor this MPDU is terminated early and is thus 212 corrupted. 213 214 215 216 This MPDU will not be ACKed. 217 218 RXPCU might still be able to correctly receive the 219 following MPDUs in the PPDU if enough fifo space became 220 available in time 221 222 mpdu_length_err 223 224 Set by RXPCU if the expected MPDU length does not 225 correspond with the actually received number of bytes in the 226 MPDU. 227 228 tkip_mic_err 229 230 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 231 for this MPDU 232 233 decrypt_err 234 235 Set by RX CRYPTO when CRYPTO detected a decrypt error 236 for this MPDU or CRYPTO received an encrypted frame, but did 237 not get a valid corresponding key id in the peer entry. 238 239 unencrypted_frame_err 240 241 Set by RX CRYPTO when CRYPTO detected an unencrypted 242 frame while in the peer entry field 243 'All_frames_shall_be_encrypted' is set. 244 245 pn_fields_contain_valid_info 246 247 Set by RX CRYPTO to indicate that there is a valid PN 248 field present in this MPDU 249 250 fcs_err 251 252 Set by RXPCU when there is an FCS error detected for 253 this MPDU 254 255 NOTE that when this field is set, all other (error) 256 field settings should be ignored as modules could have made 257 wrong decisions based on the corrupted data. 258 259 msdu_length_err 260 261 Set by RXOLE when there is an msdu length error detected 262 in at least 1 of the MSDUs embedded within the MPDU 263 264 rxdma0_destination_ring 265 266 The ring to which RXDMA0 shall push the frame, assuming 267 no MPDU level errors are detected. In case of MPDU level 268 errors, RXDMA0 might change the RXDMA0 destination 269 270 271 272 <enum 0 rxdma_release_ring > RXDMA0 shall push the 273 frame to the Release ring. Effectively this means the frame 274 needs to be dropped. 275 276 277 278 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 279 the FW ring 280 281 282 283 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 284 the SW ring 285 286 287 288 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 289 to the REO entrance ring 290 291 292 293 <legal all> 294 295 rxdma1_destination_ring 296 297 The ring to which RXDMA1 shall push the frame, assuming 298 no MPDU level errors are detected. In case of MPDU level 299 errors, RXDMA1 might change the RXDMA destination 300 301 302 303 <enum 0 rxdma_release_ring > RXDMA1 shall push the 304 frame to the Release ring. Effectively this means the frame 305 needs to be dropped. 306 307 308 309 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 310 the FW ring 311 312 313 314 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 315 the SW ring 316 317 318 319 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 320 to the REO entrance ring 321 322 323 324 <legal all> 325 326 decrypt_status_code 327 328 Field provides insight into the decryption performed 329 330 331 332 <enum 0 decrypt_ok> Frame had protection enabled and 333 decrypted properly 334 335 <enum 1 decrypt_unprotected_frame > Frame is unprotected 336 and hence bypassed 337 338 <enum 2 decrypt_data_err > Frame has protection enabled 339 and could not be properly decrypted due to MIC/ICV mismatch 340 etc. 341 342 <enum 3 decrypt_key_invalid > Frame has protection 343 enabled but the key that was required to decrypt this frame 344 was not valid 345 346 <enum 4 decrypt_peer_entry_invalid > Frame has 347 protection enabled but the key that was required to decrypt 348 this frame was not valid 349 350 <enum 5 decrypt_other > Reserved for other indications 351 352 353 354 <legal 0 - 5> 355 356 rx_bitmap_not_updated 357 358 Frame is received, but RXPCU could not update the 359 receive bitmap due to (temporary) fifo contraints. 360 361 <legal all> 362 363 reserved_1b 364 365 <legal 0> 366 */ 367 368 369 /* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 370 371 Field indicates what the reason was that this MPDU frame 372 was allowed to come into the receive path by RXPCU 373 374 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 375 frame filter programming of rxpcu 376 377 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 378 regular frame filter and would have been dropped, were it 379 not for the frame fitting into the 'monitor_client' 380 category. 381 382 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 383 regular frame filter and also did not pass the 384 rxpcu_monitor_client filter. It would have been dropped 385 accept that it did pass the 'monitor_other' category. 386 387 <legal 0-2> 388 */ 389 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 390 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 391 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 392 393 /* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID 394 395 SW processes frames based on certain classifications. 396 This field indicates to what sw classification this MPDU is 397 mapped. 398 399 The classification is given in priority order 400 401 402 403 <enum 0 sw_frame_group_NDP_frame> 404 405 406 407 <enum 1 sw_frame_group_Multicast_data> 408 409 <enum 2 sw_frame_group_Unicast_data> 410 411 <enum 3 sw_frame_group_Null_data > This includes mpdus 412 of type Data Null as well as QoS Data Null 413 414 415 416 <enum 4 sw_frame_group_mgmt_0000 > 417 418 <enum 5 sw_frame_group_mgmt_0001 > 419 420 <enum 6 sw_frame_group_mgmt_0010 > 421 422 <enum 7 sw_frame_group_mgmt_0011 > 423 424 <enum 8 sw_frame_group_mgmt_0100 > 425 426 <enum 9 sw_frame_group_mgmt_0101 > 427 428 <enum 10 sw_frame_group_mgmt_0110 > 429 430 <enum 11 sw_frame_group_mgmt_0111 > 431 432 <enum 12 sw_frame_group_mgmt_1000 > 433 434 <enum 13 sw_frame_group_mgmt_1001 > 435 436 <enum 14 sw_frame_group_mgmt_1010 > 437 438 <enum 15 sw_frame_group_mgmt_1011 > 439 440 <enum 16 sw_frame_group_mgmt_1100 > 441 442 <enum 17 sw_frame_group_mgmt_1101 > 443 444 <enum 18 sw_frame_group_mgmt_1110 > 445 446 <enum 19 sw_frame_group_mgmt_1111 > 447 448 449 450 <enum 20 sw_frame_group_ctrl_0000 > 451 452 <enum 21 sw_frame_group_ctrl_0001 > 453 454 <enum 22 sw_frame_group_ctrl_0010 > 455 456 <enum 23 sw_frame_group_ctrl_0011 > 457 458 <enum 24 sw_frame_group_ctrl_0100 > 459 460 <enum 25 sw_frame_group_ctrl_0101 > 461 462 <enum 26 sw_frame_group_ctrl_0110 > 463 464 <enum 27 sw_frame_group_ctrl_0111 > 465 466 <enum 28 sw_frame_group_ctrl_1000 > 467 468 <enum 29 sw_frame_group_ctrl_1001 > 469 470 <enum 30 sw_frame_group_ctrl_1010 > 471 472 <enum 31 sw_frame_group_ctrl_1011 > 473 474 <enum 32 sw_frame_group_ctrl_1100 > 475 476 <enum 33 sw_frame_group_ctrl_1101 > 477 478 <enum 34 sw_frame_group_ctrl_1110 > 479 480 <enum 35 sw_frame_group_ctrl_1111 > 481 482 483 484 <enum 36 sw_frame_group_unsupported> This covers type 3 485 and protocol version != 0 486 487 488 489 490 491 492 <legal 0-37> 493 */ 494 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 495 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 496 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 497 498 /* Description RX_MPDU_END_0_RESERVED_0 499 500 <legal 0> 501 */ 502 #define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 503 #define RX_MPDU_END_0_RESERVED_0_LSB 9 504 #define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 505 506 /* Description RX_MPDU_END_0_PHY_PPDU_ID 507 508 A ppdu counter value that PHY increments for every PPDU 509 received. The counter value wraps around 510 511 <legal all> 512 */ 513 #define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 514 #define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 515 #define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 516 517 /* Description RX_MPDU_END_1_RESERVED_1A 518 519 <legal 0> 520 */ 521 #define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 522 #define RX_MPDU_END_1_RESERVED_1A_LSB 0 523 #define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff 524 525 /* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME 526 527 This bit will be '1' when WEP or TKIP or WAPI key type 528 is received for 11ah short frame. Crypto will bypass the 529 received packet without decryption to RxOLE after setting 530 this bit. 531 */ 532 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 533 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 534 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 535 536 /* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP 537 538 Indicates that RX packet is not decrypted as Crypto is 539 busy with TX packet processing. 540 */ 541 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 542 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 543 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 544 545 /* Description RX_MPDU_END_1_OVERFLOW_ERR 546 547 RXPCU Receive FIFO ran out of space to receive the full 548 MPDU. Therefor this MPDU is terminated early and is thus 549 corrupted. 550 551 552 553 This MPDU will not be ACKed. 554 555 RXPCU might still be able to correctly receive the 556 following MPDUs in the PPDU if enough fifo space became 557 available in time 558 */ 559 #define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 560 #define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 561 #define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 562 563 /* Description RX_MPDU_END_1_MPDU_LENGTH_ERR 564 565 Set by RXPCU if the expected MPDU length does not 566 correspond with the actually received number of bytes in the 567 MPDU. 568 */ 569 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 570 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 571 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 572 573 /* Description RX_MPDU_END_1_TKIP_MIC_ERR 574 575 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 576 for this MPDU 577 */ 578 #define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 579 #define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 580 #define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 581 582 /* Description RX_MPDU_END_1_DECRYPT_ERR 583 584 Set by RX CRYPTO when CRYPTO detected a decrypt error 585 for this MPDU or CRYPTO received an encrypted frame, but did 586 not get a valid corresponding key id in the peer entry. 587 */ 588 #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 589 #define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 590 #define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 591 592 /* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR 593 594 Set by RX CRYPTO when CRYPTO detected an unencrypted 595 frame while in the peer entry field 596 'All_frames_shall_be_encrypted' is set. 597 */ 598 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 599 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 600 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 601 602 /* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO 603 604 Set by RX CRYPTO to indicate that there is a valid PN 605 field present in this MPDU 606 */ 607 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 608 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 609 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 610 611 /* Description RX_MPDU_END_1_FCS_ERR 612 613 Set by RXPCU when there is an FCS error detected for 614 this MPDU 615 616 NOTE that when this field is set, all other (error) 617 field settings should be ignored as modules could have made 618 wrong decisions based on the corrupted data. 619 */ 620 #define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 621 #define RX_MPDU_END_1_FCS_ERR_LSB 19 622 #define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 623 624 /* Description RX_MPDU_END_1_MSDU_LENGTH_ERR 625 626 Set by RXOLE when there is an msdu length error detected 627 in at least 1 of the MSDUs embedded within the MPDU 628 */ 629 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 630 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 631 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 632 633 /* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING 634 635 The ring to which RXDMA0 shall push the frame, assuming 636 no MPDU level errors are detected. In case of MPDU level 637 errors, RXDMA0 might change the RXDMA0 destination 638 639 640 641 <enum 0 rxdma_release_ring > RXDMA0 shall push the 642 frame to the Release ring. Effectively this means the frame 643 needs to be dropped. 644 645 646 647 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 648 the FW ring 649 650 651 652 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 653 the SW ring 654 655 656 657 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 658 to the REO entrance ring 659 660 661 662 <legal all> 663 */ 664 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 665 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 666 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 667 668 /* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING 669 670 The ring to which RXDMA1 shall push the frame, assuming 671 no MPDU level errors are detected. In case of MPDU level 672 errors, RXDMA1 might change the RXDMA destination 673 674 675 676 <enum 0 rxdma_release_ring > RXDMA1 shall push the 677 frame to the Release ring. Effectively this means the frame 678 needs to be dropped. 679 680 681 682 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 683 the FW ring 684 685 686 687 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 688 the SW ring 689 690 691 692 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 693 to the REO entrance ring 694 695 696 697 <legal all> 698 */ 699 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 700 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 701 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 702 703 /* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE 704 705 Field provides insight into the decryption performed 706 707 708 709 <enum 0 decrypt_ok> Frame had protection enabled and 710 decrypted properly 711 712 <enum 1 decrypt_unprotected_frame > Frame is unprotected 713 and hence bypassed 714 715 <enum 2 decrypt_data_err > Frame has protection enabled 716 and could not be properly decrypted due to MIC/ICV mismatch 717 etc. 718 719 <enum 3 decrypt_key_invalid > Frame has protection 720 enabled but the key that was required to decrypt this frame 721 was not valid 722 723 <enum 4 decrypt_peer_entry_invalid > Frame has 724 protection enabled but the key that was required to decrypt 725 this frame was not valid 726 727 <enum 5 decrypt_other > Reserved for other indications 728 729 730 731 <legal 0 - 5> 732 */ 733 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 734 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 735 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 736 737 /* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED 738 739 Frame is received, but RXPCU could not update the 740 receive bitmap due to (temporary) fifo contraints. 741 742 <legal all> 743 */ 744 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 745 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 746 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 747 748 /* Description RX_MPDU_END_1_RESERVED_1B 749 750 <legal 0> 751 */ 752 #define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 753 #define RX_MPDU_END_1_RESERVED_1B_LSB 29 754 #define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 755 756 757 #endif // _RX_MPDU_END_H_ 758