1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _RX_MPDU_INFO_H_ 20 #define _RX_MPDU_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "rxpt_classify_info.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16] 30 // 1 ast_index[15:0], sw_peer_id[31:16] 31 // 2 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], reserved_2a[15:10], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] 32 // 3 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], wep_key_width_for_variable_key[7:6], mesh_sta[8], bssid_hit[9], bssid_number[13:10], tid[17:14], reserved_3a[31:18] 33 // 4 pn_31_0[31:0] 34 // 5 pn_63_32[31:0] 35 // 6 pn_95_64[31:0] 36 // 7 pn_127_96[31:0] 37 // 8 peer_meta_data[31:0] 38 // 9 struct rxpt_classify_info rxpt_classify_info_details; 39 // 10 rx_reo_queue_desc_addr_31_0[31:0] 40 // 11 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26] 41 // 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30] 42 // 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], reserved_13[31:30] 43 // 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] 44 // 15 mac_addr_ad1_31_0[31:0] 45 // 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] 46 // 17 mac_addr_ad2_47_16[31:0] 47 // 18 mac_addr_ad3_31_0[31:0] 48 // 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] 49 // 20 mac_addr_ad4_31_0[31:0] 50 // 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] 51 // 22 mpdu_ht_control_field[31:0] 52 // 53 // ################ END SUMMARY ################# 54 55 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 56 57 struct rx_mpdu_info { 58 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 59 sw_frame_group_id : 7, //[8:2] 60 ndp_frame : 1, //[9] 61 phy_err : 1, //[10] 62 phy_err_during_mpdu_header : 1, //[11] 63 protocol_version_err : 1, //[12] 64 ast_based_lookup_valid : 1, //[13] 65 reserved_0a : 2, //[15:14] 66 phy_ppdu_id : 16; //[31:16] 67 uint32_t ast_index : 16, //[15:0] 68 sw_peer_id : 16; //[31:16] 69 uint32_t mpdu_frame_control_valid : 1, //[0] 70 mpdu_duration_valid : 1, //[1] 71 mac_addr_ad1_valid : 1, //[2] 72 mac_addr_ad2_valid : 1, //[3] 73 mac_addr_ad3_valid : 1, //[4] 74 mac_addr_ad4_valid : 1, //[5] 75 mpdu_sequence_control_valid : 1, //[6] 76 mpdu_qos_control_valid : 1, //[7] 77 mpdu_ht_control_valid : 1, //[8] 78 frame_encryption_info_valid : 1, //[9] 79 reserved_2a : 6, //[15:10] 80 fr_ds : 1, //[16] 81 to_ds : 1, //[17] 82 encrypted : 1, //[18] 83 mpdu_retry : 1, //[19] 84 mpdu_sequence_number : 12; //[31:20] 85 uint32_t epd_en : 1, //[0] 86 all_frames_shall_be_encrypted : 1, //[1] 87 encrypt_type : 4, //[5:2] 88 wep_key_width_for_variable_key : 2, //[7:6] 89 mesh_sta : 1, //[8] 90 bssid_hit : 1, //[9] 91 bssid_number : 4, //[13:10] 92 tid : 4, //[17:14] 93 reserved_3a : 14; //[31:18] 94 uint32_t pn_31_0 : 32; //[31:0] 95 uint32_t pn_63_32 : 32; //[31:0] 96 uint32_t pn_95_64 : 32; //[31:0] 97 uint32_t pn_127_96 : 32; //[31:0] 98 uint32_t peer_meta_data : 32; //[31:0] 99 struct rxpt_classify_info rxpt_classify_info_details; 100 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 101 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 102 receive_queue_number : 16, //[23:8] 103 pre_delim_err_warning : 1, //[24] 104 first_delim_err : 1, //[25] 105 reserved_11 : 6; //[31:26] 106 uint32_t key_id_octet : 8, //[7:0] 107 new_peer_entry : 1, //[8] 108 decrypt_needed : 1, //[9] 109 decap_type : 2, //[11:10] 110 rx_insert_vlan_c_tag_padding : 1, //[12] 111 rx_insert_vlan_s_tag_padding : 1, //[13] 112 strip_vlan_c_tag_decap : 1, //[14] 113 strip_vlan_s_tag_decap : 1, //[15] 114 pre_delim_count : 12, //[27:16] 115 ampdu_flag : 1, //[28] 116 bar_frame : 1, //[29] 117 reserved_12 : 2; //[31:30] 118 uint32_t mpdu_length : 14, //[13:0] 119 first_mpdu : 1, //[14] 120 mcast_bcast : 1, //[15] 121 ast_index_not_found : 1, //[16] 122 ast_index_timeout : 1, //[17] 123 power_mgmt : 1, //[18] 124 non_qos : 1, //[19] 125 null_data : 1, //[20] 126 mgmt_type : 1, //[21] 127 ctrl_type : 1, //[22] 128 more_data : 1, //[23] 129 eosp : 1, //[24] 130 fragment_flag : 1, //[25] 131 order : 1, //[26] 132 u_apsd_trigger : 1, //[27] 133 encrypt_required : 1, //[28] 134 directed : 1, //[29] 135 reserved_13 : 2; //[31:30] 136 uint32_t mpdu_frame_control_field : 16, //[15:0] 137 mpdu_duration_field : 16; //[31:16] 138 uint32_t mac_addr_ad1_31_0 : 32; //[31:0] 139 uint32_t mac_addr_ad1_47_32 : 16, //[15:0] 140 mac_addr_ad2_15_0 : 16; //[31:16] 141 uint32_t mac_addr_ad2_47_16 : 32; //[31:0] 142 uint32_t mac_addr_ad3_31_0 : 32; //[31:0] 143 uint32_t mac_addr_ad3_47_32 : 16, //[15:0] 144 mpdu_sequence_control_field : 16; //[31:16] 145 uint32_t mac_addr_ad4_31_0 : 32; //[31:0] 146 uint32_t mac_addr_ad4_47_32 : 16, //[15:0] 147 mpdu_qos_control_field : 16; //[31:16] 148 uint32_t mpdu_ht_control_field : 32; //[31:0] 149 }; 150 151 /* 152 153 rxpcu_mpdu_filter_in_category 154 155 Field indicates what the reason was that this MPDU frame 156 was allowed to come into the receive path by RXPCU 157 158 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 159 frame filter programming of rxpcu 160 161 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 162 regular frame filter and would have been dropped, were it 163 not for the frame fitting into the 'monitor_client' 164 category. 165 166 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 167 regular frame filter and also did not pass the 168 rxpcu_monitor_client filter. It would have been dropped 169 accept that it did pass the 'monitor_other' category. 170 171 172 173 Note: for ndp frame, if it was expected because the 174 preceding NDPA was filter_pass, the setting 175 rxpcu_filter_pass will be used. This setting will also be 176 used for every ndp frame in case Promiscuous mode is 177 enabled. 178 179 180 181 In case promiscuous is not enabled, and an NDP is not 182 preceded by a NPDA filter pass frame, the only other setting 183 that could appear here for the NDP is rxpcu_monitor_other. 184 185 (rxpcu has a configuration bit specifically for this 186 scenario) 187 188 189 190 Note: for 191 192 <legal 0-2> 193 194 sw_frame_group_id 195 196 SW processes frames based on certain classifications. 197 This field indicates to what sw classification this MPDU is 198 mapped. 199 200 The classification is given in priority order 201 202 203 204 <enum 0 sw_frame_group_NDP_frame> Note: The 205 corresponding Rxpcu_Mpdu_filter_in_category can be 206 rxpcu_filter_pass or rxpcu_monitor_other 207 208 209 210 <enum 1 sw_frame_group_Multicast_data> 211 212 <enum 2 sw_frame_group_Unicast_data> 213 214 <enum 3 sw_frame_group_Null_data > This includes mpdus 215 of type Data Null as well as QoS Data Null 216 217 218 219 <enum 4 sw_frame_group_mgmt_0000 > 220 221 <enum 5 sw_frame_group_mgmt_0001 > 222 223 <enum 6 sw_frame_group_mgmt_0010 > 224 225 <enum 7 sw_frame_group_mgmt_0011 > 226 227 <enum 8 sw_frame_group_mgmt_0100 > 228 229 <enum 9 sw_frame_group_mgmt_0101 > 230 231 <enum 10 sw_frame_group_mgmt_0110 > 232 233 <enum 11 sw_frame_group_mgmt_0111 > 234 235 <enum 12 sw_frame_group_mgmt_1000 > 236 237 <enum 13 sw_frame_group_mgmt_1001 > 238 239 <enum 14 sw_frame_group_mgmt_1010 > 240 241 <enum 15 sw_frame_group_mgmt_1011 > 242 243 <enum 16 sw_frame_group_mgmt_1100 > 244 245 <enum 17 sw_frame_group_mgmt_1101 > 246 247 <enum 18 sw_frame_group_mgmt_1110 > 248 249 <enum 19 sw_frame_group_mgmt_1111 > 250 251 252 253 <enum 20 sw_frame_group_ctrl_0000 > 254 255 <enum 21 sw_frame_group_ctrl_0001 > 256 257 <enum 22 sw_frame_group_ctrl_0010 > 258 259 <enum 23 sw_frame_group_ctrl_0011 > 260 261 <enum 24 sw_frame_group_ctrl_0100 > 262 263 <enum 25 sw_frame_group_ctrl_0101 > 264 265 <enum 26 sw_frame_group_ctrl_0110 > 266 267 <enum 27 sw_frame_group_ctrl_0111 > 268 269 <enum 28 sw_frame_group_ctrl_1000 > 270 271 <enum 29 sw_frame_group_ctrl_1001 > 272 273 <enum 30 sw_frame_group_ctrl_1010 > 274 275 <enum 31 sw_frame_group_ctrl_1011 > 276 277 <enum 32 sw_frame_group_ctrl_1100 > 278 279 <enum 33 sw_frame_group_ctrl_1101 > 280 281 <enum 34 sw_frame_group_ctrl_1110 > 282 283 <enum 35 sw_frame_group_ctrl_1111 > 284 285 286 287 <enum 36 sw_frame_group_unsupported> This covers type 3 288 and protocol version != 0 289 290 Note: The corresponding Rxpcu_Mpdu_filter_in_category 291 can only be rxpcu_monitor_other 292 293 294 295 296 Note: The corresponding Rxpcu_Mpdu_filter_in_category 297 can be rxpcu_filter_pass 298 299 300 301 <legal 0-37> 302 303 ndp_frame 304 305 When set, the received frame was an NDP frame, and thus 306 there will be no MPDU data. 307 308 <legal all> 309 310 phy_err 311 312 When set, a PHY error was received before MAC received 313 any data, and thus there will be no MPDU data. 314 315 <legal all> 316 317 phy_err_during_mpdu_header 318 319 When set, a PHY error was received before MAC received 320 the complete MPDU header which was needed for proper 321 decoding 322 323 <legal all> 324 325 protocol_version_err 326 327 Set when RXPCU detected a version error in the Frame 328 control field 329 330 <legal all> 331 332 ast_based_lookup_valid 333 334 When set, AST based lookup for this frame has found a 335 valid result. 336 337 338 339 Note that for NDP frame this will never be set 340 341 <legal all> 342 343 reserved_0a 344 345 <legal 0> 346 347 phy_ppdu_id 348 349 A ppdu counter value that PHY increments for every PPDU 350 received. The counter value wraps around 351 352 <legal all> 353 354 ast_index 355 356 This field indicates the index of the AST entry 357 corresponding to this MPDU. It is provided by the GSE module 358 instantiated in RXPCU. 359 360 A value of 0xFFFF indicates an invalid AST index, 361 meaning that No AST entry was found or NO AST search was 362 performed 363 364 365 366 In case of ndp or phy_err, this field will be set to 367 0xFFFF 368 369 <legal all> 370 371 sw_peer_id 372 373 In case of ndp or phy_err or AST_based_lookup_valid == 374 0, this field will be set to 0 375 376 377 378 This field indicates a unique peer identifier. It is set 379 equal to field 'sw_peer_id' from the AST entry 380 381 382 383 <legal all> 384 385 mpdu_frame_control_valid 386 387 When set, the field Mpdu_Frame_control_field has valid 388 information 389 390 391 392 393 <legal all> 394 395 mpdu_duration_valid 396 397 When set, the field Mpdu_duration_field has valid 398 information 399 400 401 402 403 <legal all> 404 405 mac_addr_ad1_valid 406 407 When set, the fields mac_addr_ad1_..... have valid 408 information 409 410 411 412 413 <legal all> 414 415 mac_addr_ad2_valid 416 417 When set, the fields mac_addr_ad2_..... have valid 418 information 419 420 421 422 423 424 425 426 <legal all> 427 428 mac_addr_ad3_valid 429 430 When set, the fields mac_addr_ad3_..... have valid 431 information 432 433 434 435 436 437 438 439 <legal all> 440 441 mac_addr_ad4_valid 442 443 When set, the fields mac_addr_ad4_..... have valid 444 information 445 446 447 448 449 450 451 452 <legal all> 453 454 mpdu_sequence_control_valid 455 456 When set, the fields mpdu_sequence_control_field and 457 mpdu_sequence_number have valid information as well as field 458 459 460 461 For MPDUs without a sequence control field, this field 462 will not be set. 463 464 465 466 467 <legal all> 468 469 mpdu_qos_control_valid 470 471 When set, the field mpdu_qos_control_field has valid 472 information 473 474 475 476 For MPDUs without a QoS control field, this field will 477 not be set. 478 479 480 481 482 <legal all> 483 484 mpdu_ht_control_valid 485 486 When set, the field mpdu_HT_control_field has valid 487 information 488 489 490 491 For MPDUs without a HT control field, this field will 492 not be set. 493 494 495 496 497 <legal all> 498 499 frame_encryption_info_valid 500 501 When set, the encryption related info fields, like IV 502 and PN are valid 503 504 505 506 For MPDUs that are not encrypted, this will not be set. 507 508 509 510 511 <legal all> 512 513 reserved_2a 514 515 <legal 0> 516 517 fr_ds 518 519 Field only valid when Mpdu_frame_control_valid is set 520 521 522 523 Set if the from DS bit is set in the frame control. 524 525 <legal all> 526 527 to_ds 528 529 Field only valid when Mpdu_frame_control_valid is set 530 531 532 533 Set if the to DS bit is set in the frame control. 534 535 <legal all> 536 537 encrypted 538 539 Field only valid when Mpdu_frame_control_valid is set. 540 541 542 543 Protected bit from the frame control. 544 545 <legal all> 546 547 mpdu_retry 548 549 Field only valid when Mpdu_frame_control_valid is set. 550 551 552 553 Retry bit from the frame control. Only valid when 554 first_msdu is set. 555 556 <legal all> 557 558 mpdu_sequence_number 559 560 Field only valid when Mpdu_sequence_control_valid is 561 set. 562 563 564 565 The sequence number from the 802.11 header. 566 567 <legal all> 568 569 epd_en 570 571 Field only valid when AST_based_lookup_valid == 1. 572 573 574 575 576 577 In case of ndp or phy_err or AST_based_lookup_valid == 578 0, this field will be set to 0 579 580 581 582 If set to one use EPD instead of LPD 583 584 585 586 587 <legal all> 588 589 all_frames_shall_be_encrypted 590 591 In case of ndp or phy_err or AST_based_lookup_valid == 592 0, this field will be set to 0 593 594 595 596 When set, all frames (data only ?) shall be encrypted. 597 If not, RX CRYPTO shall set an error flag. 598 599 <legal all> 600 601 encrypt_type 602 603 In case of ndp or phy_err or AST_based_lookup_valid == 604 0, this field will be set to 0 605 606 607 608 Indicates type of decrypt cipher used (as defined in the 609 peer entry) 610 611 612 613 <enum 0 wep_40> WEP 40-bit 614 615 <enum 1 wep_104> WEP 104-bit 616 617 <enum 2 tkip_no_mic> TKIP without MIC 618 619 <enum 3 wep_128> WEP 128-bit 620 621 <enum 4 tkip_with_mic> TKIP with MIC 622 623 <enum 5 wapi> WAPI 624 625 <enum 6 aes_ccmp_128> AES CCMP 128 626 627 <enum 7 no_cipher> No crypto 628 629 <enum 8 aes_ccmp_256> AES CCMP 256 630 631 <enum 9 aes_gcmp_128> AES CCMP 128 632 633 <enum 10 aes_gcmp_256> AES CCMP 256 634 635 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 636 637 638 639 <enum 12 wep_varied_width> WEP encryption. As for WEP 640 per keyid the key bit width can vary, the key bit width for 641 this MPDU will be indicated in field 642 wep_key_width_for_variable key 643 644 <legal 0-12> 645 646 wep_key_width_for_variable_key 647 648 Field only valid when key_type is set to 649 wep_varied_width. 650 651 652 653 This field indicates the size of the wep key for this 654 MPDU. 655 656 657 658 <enum 0 wep_varied_width_40> WEP 40-bit 659 660 <enum 1 wep_varied_width_104> WEP 104-bit 661 662 <enum 2 wep_varied_width_128> WEP 128-bit 663 664 665 666 <legal 0-2> 667 668 mesh_sta 669 670 In case of ndp or phy_err or AST_based_lookup_valid == 671 0, this field will be set to 0 672 673 674 675 When set, this is a Mesh (11s) STA 676 677 <legal all> 678 679 bssid_hit 680 681 In case of ndp or phy_err or AST_based_lookup_valid == 682 0, this field will be set to 0 683 684 685 686 When set, the BSSID of the incoming frame matched one of 687 the 8 BSSID register values 688 689 690 691 <legal all> 692 693 bssid_number 694 695 Field only valid when bssid_hit is set. 696 697 698 699 This number indicates which one out of the 8 BSSID 700 register values matched the incoming frame 701 702 <legal all> 703 704 tid 705 706 Field only valid when mpdu_qos_control_valid is set 707 708 709 710 The TID field in the QoS control field 711 712 <legal all> 713 714 reserved_3a 715 716 <legal 0> 717 718 pn_31_0 719 720 721 722 723 724 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 725 is valid. 726 727 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 728 WEPSeed[1], pn1}. Only pn[47:0] is valid. 729 730 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 731 pn1, pn0}. Only pn[47:0] is valid. 732 733 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 734 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 735 pn0}. pn[127:0] are valid. 736 737 738 739 740 pn_63_32 741 742 743 744 745 Bits [63:32] of the PN number. See description for 746 pn_31_0. 747 748 749 750 751 pn_95_64 752 753 754 755 756 Bits [95:64] of the PN number. See description for 757 pn_31_0. 758 759 760 761 762 pn_127_96 763 764 765 766 767 Bits [127:96] of the PN number. See description for 768 pn_31_0. 769 770 771 772 773 peer_meta_data 774 775 In case of ndp or phy_err or AST_based_lookup_valid == 776 0, this field will be set to 0 777 778 779 780 Meta data that SW has programmed in the Peer table entry 781 of the transmitting STA. 782 783 <legal all> 784 785 struct rxpt_classify_info rxpt_classify_info_details 786 787 In case of ndp or phy_err or AST_based_lookup_valid == 788 0, this field will be set to 0 789 790 791 792 RXOLE related classification info 793 794 <legal all 795 796 rx_reo_queue_desc_addr_31_0 797 798 In case of ndp or phy_err or AST_based_lookup_valid == 799 0, this field will be set to 0 800 801 802 803 Address (lower 32 bits) of the REO queue descriptor. 804 805 806 807 If no Peer entry lookup happened for this frame, the 808 value wil be set to 0, and the frame shall never be pushed 809 to REO entrance ring. 810 811 <legal all> 812 813 rx_reo_queue_desc_addr_39_32 814 815 In case of ndp or phy_err or AST_based_lookup_valid == 816 0, this field will be set to 0 817 818 819 820 Address (upper 8 bits) of the REO queue descriptor. 821 822 823 824 If no Peer entry lookup happened for this frame, the 825 value wil be set to 0, and the frame shall never be pushed 826 to REO entrance ring. 827 828 <legal all> 829 830 receive_queue_number 831 832 In case of ndp or phy_err or AST_based_lookup_valid == 833 0, this field will be set to 0 834 835 836 837 Indicates the MPDU queue ID to which this MPDU link 838 descriptor belongs 839 840 Used for tracking and debugging 841 842 <legal all> 843 844 pre_delim_err_warning 845 846 Indicates that a delimiter FCS error was found in 847 between the Previous MPDU and this MPDU. 848 849 850 851 Note that this is just a warning, and does not mean that 852 this MPDU is corrupted in any way. If it is, there will be 853 other errors indicated such as FCS or decrypt errors 854 855 856 857 In case of ndp or phy_err, this field will indicate at 858 least one of delimiters located after the last MPDU in the 859 previous PPDU has been corrupted. 860 861 first_delim_err 862 863 Indicates that the first delimiter had a FCS failure. 864 Only valid when first_mpdu and first_msdu are set. 865 866 867 868 869 reserved_11 870 871 <legal 0> 872 873 key_id_octet 874 875 876 877 878 The key ID octet from the IV. 879 880 881 882 In case of ndp or phy_err or AST_based_lookup_valid == 883 0, this field will be set to 0 884 885 <legal all> 886 887 new_peer_entry 888 889 In case of ndp or phy_err or AST_based_lookup_valid == 890 0, this field will be set to 0 891 892 893 894 Set if new RX_PEER_ENTRY TLV follows. If clear, 895 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 896 uses old peer entry or not decrypt. 897 898 <legal all> 899 900 decrypt_needed 901 902 In case of ndp or phy_err or AST_based_lookup_valid == 903 0, this field will be set to 0 904 905 906 907 Set if decryption is needed. 908 909 910 911 Note: 912 913 When RXPCU sets bit 'ast_index_not_found' and/or 914 ast_index_timeout', RXPCU will also ensure that this bit is 915 NOT set 916 917 CRYPTO for that reason only needs to evaluate this bit 918 and non of the other ones. 919 920 <legal all> 921 922 decap_type 923 924 In case of ndp or phy_err or AST_based_lookup_valid == 925 0, this field will be set to 0 926 927 928 929 Used by the OLE during decapsulation. 930 931 932 933 Indicates the decapsulation that HW will perform: 934 935 936 937 <enum 0 RAW> No encapsulation 938 939 <enum 1 Native_WiFi> 940 941 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 942 SNAP/LLC) 943 944 <enum 3 802_3> Indicate Ethernet 945 946 947 948 <legal all> 949 950 rx_insert_vlan_c_tag_padding 951 952 In case of ndp or phy_err or AST_based_lookup_valid == 953 0, this field will be set to 0 954 955 956 957 Insert 4 byte of all zeros as VLAN tag if the rx payload 958 does not have VLAN. Used during decapsulation. 959 960 <legal all> 961 962 rx_insert_vlan_s_tag_padding 963 964 In case of ndp or phy_err or AST_based_lookup_valid == 965 0, this field will be set to 0 966 967 968 969 Insert 4 byte of all zeros as double VLAN tag if the rx 970 payload does not have VLAN. Used during 971 972 <legal all> 973 974 strip_vlan_c_tag_decap 975 976 In case of ndp or phy_err or AST_based_lookup_valid == 977 0, this field will be set to 0 978 979 980 981 Strip the VLAN during decapsulation. Used by the OLE. 982 983 <legal all> 984 985 strip_vlan_s_tag_decap 986 987 In case of ndp or phy_err or AST_based_lookup_valid == 988 0, this field will be set to 0 989 990 991 992 Strip the double VLAN during decapsulation. Used by 993 the OLE. 994 995 <legal all> 996 997 pre_delim_count 998 999 The number of delimiters before this MPDU. 1000 1001 1002 1003 Note that this number is cleared at PPDU start. 1004 1005 1006 1007 If this MPDU is the first received MPDU in the PPDU and 1008 this MPDU gets filtered-in, this field will indicate the 1009 number of delimiters located after the last MPDU in the 1010 previous PPDU. 1011 1012 1013 1014 If this MPDU is located after the first received MPDU in 1015 an PPDU, this field will indicate the number of delimiters 1016 located between the previous MPDU and this MPDU. 1017 1018 1019 1020 In case of ndp or phy_err, this field will indicate the 1021 number of delimiters located after the last MPDU in the 1022 previous PPDU. 1023 1024 <legal all> 1025 1026 ampdu_flag 1027 1028 When set, received frame was part of an A-MPDU. 1029 1030 1031 1032 1033 <legal all> 1034 1035 bar_frame 1036 1037 In case of ndp or phy_err or AST_based_lookup_valid == 1038 0, this field will be set to 0 1039 1040 1041 1042 When set, received frame is a BAR frame 1043 1044 <legal all> 1045 1046 reserved_12 1047 1048 <legal 0>. 1049 1050 mpdu_length 1051 1052 In case of ndp or phy_err this field will be set to 0 1053 1054 1055 1056 MPDU length before decapsulation. 1057 1058 <legal all> 1059 1060 first_mpdu 1061 1062 See definition in RX attention descriptor 1063 1064 1065 1066 In case of ndp or phy_err, this field will be set. Note 1067 however that there will not actually be any data contents in 1068 the MPDU. 1069 1070 <legal all> 1071 1072 mcast_bcast 1073 1074 In case of ndp or phy_err or Phy_err_during_mpdu_header 1075 this field will be set to 0 1076 1077 1078 1079 See definition in RX attention descriptor 1080 1081 <legal all> 1082 1083 ast_index_not_found 1084 1085 In case of ndp or phy_err or Phy_err_during_mpdu_header 1086 this field will be set to 0 1087 1088 1089 1090 See definition in RX attention descriptor 1091 1092 <legal all> 1093 1094 ast_index_timeout 1095 1096 In case of ndp or phy_err or Phy_err_during_mpdu_header 1097 this field will be set to 0 1098 1099 1100 1101 See definition in RX attention descriptor 1102 1103 <legal all> 1104 1105 power_mgmt 1106 1107 In case of ndp or phy_err or Phy_err_during_mpdu_header 1108 this field will be set to 0 1109 1110 1111 1112 See definition in RX attention descriptor 1113 1114 <legal all> 1115 1116 non_qos 1117 1118 In case of ndp or phy_err or Phy_err_during_mpdu_header 1119 this field will be set to 1 1120 1121 1122 1123 See definition in RX attention descriptor 1124 1125 <legal all> 1126 1127 null_data 1128 1129 In case of ndp or phy_err or Phy_err_during_mpdu_header 1130 this field will be set to 0 1131 1132 1133 1134 See definition in RX attention descriptor 1135 1136 <legal all> 1137 1138 mgmt_type 1139 1140 In case of ndp or phy_err or Phy_err_during_mpdu_header 1141 this field will be set to 0 1142 1143 1144 1145 See definition in RX attention descriptor 1146 1147 <legal all> 1148 1149 ctrl_type 1150 1151 In case of ndp or phy_err or Phy_err_during_mpdu_header 1152 this field will be set to 0 1153 1154 1155 1156 See definition in RX attention descriptor 1157 1158 <legal all> 1159 1160 more_data 1161 1162 In case of ndp or phy_err or Phy_err_during_mpdu_header 1163 this field will be set to 0 1164 1165 1166 1167 See definition in RX attention descriptor 1168 1169 <legal all> 1170 1171 eosp 1172 1173 In case of ndp or phy_err or Phy_err_during_mpdu_header 1174 this field will be set to 0 1175 1176 1177 1178 See definition in RX attention descriptor 1179 1180 <legal all> 1181 1182 fragment_flag 1183 1184 In case of ndp or phy_err or Phy_err_during_mpdu_header 1185 this field will be set to 0 1186 1187 1188 1189 See definition in RX attention descriptor 1190 1191 <legal all> 1192 1193 order 1194 1195 In case of ndp or phy_err or Phy_err_during_mpdu_header 1196 this field will be set to 0 1197 1198 1199 1200 See definition in RX attention descriptor 1201 1202 1203 1204 <legal all> 1205 1206 u_apsd_trigger 1207 1208 In case of ndp or phy_err or Phy_err_during_mpdu_header 1209 this field will be set to 0 1210 1211 1212 1213 See definition in RX attention descriptor 1214 1215 <legal all> 1216 1217 encrypt_required 1218 1219 In case of ndp or phy_err or Phy_err_during_mpdu_header 1220 this field will be set to 0 1221 1222 1223 1224 See definition in RX attention descriptor 1225 1226 <legal all> 1227 1228 directed 1229 1230 In case of ndp or phy_err or Phy_err_during_mpdu_header 1231 this field will be set to 0 1232 1233 1234 1235 See definition in RX attention descriptor 1236 1237 <legal all> 1238 1239 reserved_13 1240 1241 <legal 0> 1242 1243 mpdu_frame_control_field 1244 1245 Field only valid when Mpdu_frame_control_valid is set 1246 1247 1248 1249 The frame control field of this received MPDU. 1250 1251 1252 1253 Field only valid when Ndp_frame and phy_err are NOT set 1254 1255 1256 1257 Bytes 0 + 1 of the received MPDU 1258 1259 <legal all> 1260 1261 mpdu_duration_field 1262 1263 Field only valid when Mpdu_duration_valid is set 1264 1265 1266 1267 The duration field of this received MPDU. 1268 1269 <legal all> 1270 1271 mac_addr_ad1_31_0 1272 1273 Field only valid when mac_addr_ad1_valid is set 1274 1275 1276 1277 The Least Significant 4 bytes of the Received Frames MAC 1278 Address AD1 1279 1280 <legal all> 1281 1282 mac_addr_ad1_47_32 1283 1284 Field only valid when mac_addr_ad1_valid is set 1285 1286 1287 1288 The 2 most significant bytes of the Received Frames MAC 1289 Address AD1 1290 1291 <legal all> 1292 1293 mac_addr_ad2_15_0 1294 1295 Field only valid when mac_addr_ad2_valid is set 1296 1297 1298 1299 The Least Significant 2 bytes of the Received Frames MAC 1300 Address AD2 1301 1302 <legal all> 1303 1304 mac_addr_ad2_47_16 1305 1306 Field only valid when mac_addr_ad2_valid is set 1307 1308 1309 1310 The 4 most significant bytes of the Received Frames MAC 1311 Address AD2 1312 1313 <legal all> 1314 1315 mac_addr_ad3_31_0 1316 1317 Field only valid when mac_addr_ad3_valid is set 1318 1319 1320 1321 The Least Significant 4 bytes of the Received Frames MAC 1322 Address AD3 1323 1324 <legal all> 1325 1326 mac_addr_ad3_47_32 1327 1328 Field only valid when mac_addr_ad3_valid is set 1329 1330 1331 1332 The 2 most significant bytes of the Received Frames MAC 1333 Address AD3 1334 1335 <legal all> 1336 1337 mpdu_sequence_control_field 1338 1339 1340 1341 1342 The sequence control field of the MPDU 1343 1344 <legal all> 1345 1346 mac_addr_ad4_31_0 1347 1348 Field only valid when mac_addr_ad4_valid is set 1349 1350 1351 1352 The Least Significant 4 bytes of the Received Frames MAC 1353 Address AD4 1354 1355 <legal all> 1356 1357 mac_addr_ad4_47_32 1358 1359 Field only valid when mac_addr_ad4_valid is set 1360 1361 1362 1363 The 2 most significant bytes of the Received Frames MAC 1364 Address AD4 1365 1366 <legal all> 1367 1368 mpdu_qos_control_field 1369 1370 Field only valid when mpdu_qos_control_valid is set 1371 1372 1373 1374 The sequence control field of the MPDU 1375 1376 <legal all> 1377 1378 mpdu_ht_control_field 1379 1380 Field only valid when mpdu_qos_control_valid is set 1381 1382 1383 1384 The HT control field of the MPDU 1385 1386 <legal all> 1387 */ 1388 1389 1390 /* Description RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY 1391 1392 Field indicates what the reason was that this MPDU frame 1393 was allowed to come into the receive path by RXPCU 1394 1395 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 1396 frame filter programming of rxpcu 1397 1398 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 1399 regular frame filter and would have been dropped, were it 1400 not for the frame fitting into the 'monitor_client' 1401 category. 1402 1403 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 1404 regular frame filter and also did not pass the 1405 rxpcu_monitor_client filter. It would have been dropped 1406 accept that it did pass the 'monitor_other' category. 1407 1408 1409 1410 Note: for ndp frame, if it was expected because the 1411 preceding NDPA was filter_pass, the setting 1412 rxpcu_filter_pass will be used. This setting will also be 1413 used for every ndp frame in case Promiscuous mode is 1414 enabled. 1415 1416 1417 1418 In case promiscuous is not enabled, and an NDP is not 1419 preceded by a NPDA filter pass frame, the only other setting 1420 that could appear here for the NDP is rxpcu_monitor_other. 1421 1422 (rxpcu has a configuration bit specifically for this 1423 scenario) 1424 1425 1426 1427 Note: for 1428 1429 <legal 0-2> 1430 */ 1431 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 1432 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 1433 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 1434 1435 /* Description RX_MPDU_INFO_0_SW_FRAME_GROUP_ID 1436 1437 SW processes frames based on certain classifications. 1438 This field indicates to what sw classification this MPDU is 1439 mapped. 1440 1441 The classification is given in priority order 1442 1443 1444 1445 <enum 0 sw_frame_group_NDP_frame> Note: The 1446 corresponding Rxpcu_Mpdu_filter_in_category can be 1447 rxpcu_filter_pass or rxpcu_monitor_other 1448 1449 1450 1451 <enum 1 sw_frame_group_Multicast_data> 1452 1453 <enum 2 sw_frame_group_Unicast_data> 1454 1455 <enum 3 sw_frame_group_Null_data > This includes mpdus 1456 of type Data Null as well as QoS Data Null 1457 1458 1459 1460 <enum 4 sw_frame_group_mgmt_0000 > 1461 1462 <enum 5 sw_frame_group_mgmt_0001 > 1463 1464 <enum 6 sw_frame_group_mgmt_0010 > 1465 1466 <enum 7 sw_frame_group_mgmt_0011 > 1467 1468 <enum 8 sw_frame_group_mgmt_0100 > 1469 1470 <enum 9 sw_frame_group_mgmt_0101 > 1471 1472 <enum 10 sw_frame_group_mgmt_0110 > 1473 1474 <enum 11 sw_frame_group_mgmt_0111 > 1475 1476 <enum 12 sw_frame_group_mgmt_1000 > 1477 1478 <enum 13 sw_frame_group_mgmt_1001 > 1479 1480 <enum 14 sw_frame_group_mgmt_1010 > 1481 1482 <enum 15 sw_frame_group_mgmt_1011 > 1483 1484 <enum 16 sw_frame_group_mgmt_1100 > 1485 1486 <enum 17 sw_frame_group_mgmt_1101 > 1487 1488 <enum 18 sw_frame_group_mgmt_1110 > 1489 1490 <enum 19 sw_frame_group_mgmt_1111 > 1491 1492 1493 1494 <enum 20 sw_frame_group_ctrl_0000 > 1495 1496 <enum 21 sw_frame_group_ctrl_0001 > 1497 1498 <enum 22 sw_frame_group_ctrl_0010 > 1499 1500 <enum 23 sw_frame_group_ctrl_0011 > 1501 1502 <enum 24 sw_frame_group_ctrl_0100 > 1503 1504 <enum 25 sw_frame_group_ctrl_0101 > 1505 1506 <enum 26 sw_frame_group_ctrl_0110 > 1507 1508 <enum 27 sw_frame_group_ctrl_0111 > 1509 1510 <enum 28 sw_frame_group_ctrl_1000 > 1511 1512 <enum 29 sw_frame_group_ctrl_1001 > 1513 1514 <enum 30 sw_frame_group_ctrl_1010 > 1515 1516 <enum 31 sw_frame_group_ctrl_1011 > 1517 1518 <enum 32 sw_frame_group_ctrl_1100 > 1519 1520 <enum 33 sw_frame_group_ctrl_1101 > 1521 1522 <enum 34 sw_frame_group_ctrl_1110 > 1523 1524 <enum 35 sw_frame_group_ctrl_1111 > 1525 1526 1527 1528 <enum 36 sw_frame_group_unsupported> This covers type 3 1529 and protocol version != 0 1530 1531 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1532 can only be rxpcu_monitor_other 1533 1534 1535 1536 1537 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1538 can be rxpcu_filter_pass 1539 1540 1541 1542 <legal 0-37> 1543 */ 1544 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 1545 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB 2 1546 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 1547 1548 /* Description RX_MPDU_INFO_0_NDP_FRAME 1549 1550 When set, the received frame was an NDP frame, and thus 1551 there will be no MPDU data. 1552 1553 <legal all> 1554 */ 1555 #define RX_MPDU_INFO_0_NDP_FRAME_OFFSET 0x00000000 1556 #define RX_MPDU_INFO_0_NDP_FRAME_LSB 9 1557 #define RX_MPDU_INFO_0_NDP_FRAME_MASK 0x00000200 1558 1559 /* Description RX_MPDU_INFO_0_PHY_ERR 1560 1561 When set, a PHY error was received before MAC received 1562 any data, and thus there will be no MPDU data. 1563 1564 <legal all> 1565 */ 1566 #define RX_MPDU_INFO_0_PHY_ERR_OFFSET 0x00000000 1567 #define RX_MPDU_INFO_0_PHY_ERR_LSB 10 1568 #define RX_MPDU_INFO_0_PHY_ERR_MASK 0x00000400 1569 1570 /* Description RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER 1571 1572 When set, a PHY error was received before MAC received 1573 the complete MPDU header which was needed for proper 1574 decoding 1575 1576 <legal all> 1577 */ 1578 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000000 1579 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB 11 1580 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 1581 1582 /* Description RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR 1583 1584 Set when RXPCU detected a version error in the Frame 1585 control field 1586 1587 <legal all> 1588 */ 1589 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET 0x00000000 1590 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB 12 1591 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK 0x00001000 1592 1593 /* Description RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID 1594 1595 When set, AST based lookup for this frame has found a 1596 valid result. 1597 1598 1599 1600 Note that for NDP frame this will never be set 1601 1602 <legal all> 1603 */ 1604 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET 0x00000000 1605 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB 13 1606 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK 0x00002000 1607 1608 /* Description RX_MPDU_INFO_0_RESERVED_0A 1609 1610 <legal 0> 1611 */ 1612 #define RX_MPDU_INFO_0_RESERVED_0A_OFFSET 0x00000000 1613 #define RX_MPDU_INFO_0_RESERVED_0A_LSB 14 1614 #define RX_MPDU_INFO_0_RESERVED_0A_MASK 0x0000c000 1615 1616 /* Description RX_MPDU_INFO_0_PHY_PPDU_ID 1617 1618 A ppdu counter value that PHY increments for every PPDU 1619 received. The counter value wraps around 1620 1621 <legal all> 1622 */ 1623 #define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 1624 #define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB 16 1625 #define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK 0xffff0000 1626 1627 /* Description RX_MPDU_INFO_1_AST_INDEX 1628 1629 This field indicates the index of the AST entry 1630 corresponding to this MPDU. It is provided by the GSE module 1631 instantiated in RXPCU. 1632 1633 A value of 0xFFFF indicates an invalid AST index, 1634 meaning that No AST entry was found or NO AST search was 1635 performed 1636 1637 1638 1639 In case of ndp or phy_err, this field will be set to 1640 0xFFFF 1641 1642 <legal all> 1643 */ 1644 #define RX_MPDU_INFO_1_AST_INDEX_OFFSET 0x00000004 1645 #define RX_MPDU_INFO_1_AST_INDEX_LSB 0 1646 #define RX_MPDU_INFO_1_AST_INDEX_MASK 0x0000ffff 1647 1648 /* Description RX_MPDU_INFO_1_SW_PEER_ID 1649 1650 In case of ndp or phy_err or AST_based_lookup_valid == 1651 0, this field will be set to 0 1652 1653 1654 1655 This field indicates a unique peer identifier. It is set 1656 equal to field 'sw_peer_id' from the AST entry 1657 1658 1659 1660 <legal all> 1661 */ 1662 #define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET 0x00000004 1663 #define RX_MPDU_INFO_1_SW_PEER_ID_LSB 16 1664 #define RX_MPDU_INFO_1_SW_PEER_ID_MASK 0xffff0000 1665 1666 /* Description RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID 1667 1668 When set, the field Mpdu_Frame_control_field has valid 1669 information 1670 1671 1672 1673 1674 <legal all> 1675 */ 1676 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000008 1677 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB 0 1678 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 1679 1680 /* Description RX_MPDU_INFO_2_MPDU_DURATION_VALID 1681 1682 When set, the field Mpdu_duration_field has valid 1683 information 1684 1685 1686 1687 1688 <legal all> 1689 */ 1690 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET 0x00000008 1691 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB 1 1692 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK 0x00000002 1693 1694 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID 1695 1696 When set, the fields mac_addr_ad1_..... have valid 1697 information 1698 1699 1700 1701 1702 <legal all> 1703 */ 1704 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET 0x00000008 1705 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB 2 1706 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK 0x00000004 1707 1708 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID 1709 1710 When set, the fields mac_addr_ad2_..... have valid 1711 information 1712 1713 1714 1715 1716 1717 1718 1719 <legal all> 1720 */ 1721 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET 0x00000008 1722 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB 3 1723 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK 0x00000008 1724 1725 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID 1726 1727 When set, the fields mac_addr_ad3_..... have valid 1728 information 1729 1730 1731 1732 1733 1734 1735 1736 <legal all> 1737 */ 1738 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET 0x00000008 1739 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB 4 1740 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK 0x00000010 1741 1742 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID 1743 1744 When set, the fields mac_addr_ad4_..... have valid 1745 information 1746 1747 1748 1749 1750 1751 1752 1753 <legal all> 1754 */ 1755 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET 0x00000008 1756 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB 5 1757 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK 0x00000020 1758 1759 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID 1760 1761 When set, the fields mpdu_sequence_control_field and 1762 mpdu_sequence_number have valid information as well as field 1763 1764 1765 1766 For MPDUs without a sequence control field, this field 1767 will not be set. 1768 1769 1770 1771 1772 <legal all> 1773 */ 1774 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000008 1775 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1776 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1777 1778 /* Description RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID 1779 1780 When set, the field mpdu_qos_control_field has valid 1781 information 1782 1783 1784 1785 For MPDUs without a QoS control field, this field will 1786 not be set. 1787 1788 1789 1790 1791 <legal all> 1792 */ 1793 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 1794 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB 7 1795 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1796 1797 /* Description RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID 1798 1799 When set, the field mpdu_HT_control_field has valid 1800 information 1801 1802 1803 1804 For MPDUs without a HT control field, this field will 1805 not be set. 1806 1807 1808 1809 1810 <legal all> 1811 */ 1812 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET 0x00000008 1813 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB 8 1814 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1815 1816 /* Description RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID 1817 1818 When set, the encryption related info fields, like IV 1819 and PN are valid 1820 1821 1822 1823 For MPDUs that are not encrypted, this will not be set. 1824 1825 1826 1827 1828 <legal all> 1829 */ 1830 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000008 1831 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1832 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1833 1834 /* Description RX_MPDU_INFO_2_RESERVED_2A 1835 1836 <legal 0> 1837 */ 1838 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 1839 #define RX_MPDU_INFO_2_RESERVED_2A_LSB 10 1840 #define RX_MPDU_INFO_2_RESERVED_2A_MASK 0x0000fc00 1841 1842 /* Description RX_MPDU_INFO_2_FR_DS 1843 1844 Field only valid when Mpdu_frame_control_valid is set 1845 1846 1847 1848 Set if the from DS bit is set in the frame control. 1849 1850 <legal all> 1851 */ 1852 #define RX_MPDU_INFO_2_FR_DS_OFFSET 0x00000008 1853 #define RX_MPDU_INFO_2_FR_DS_LSB 16 1854 #define RX_MPDU_INFO_2_FR_DS_MASK 0x00010000 1855 1856 /* Description RX_MPDU_INFO_2_TO_DS 1857 1858 Field only valid when Mpdu_frame_control_valid is set 1859 1860 1861 1862 Set if the to DS bit is set in the frame control. 1863 1864 <legal all> 1865 */ 1866 #define RX_MPDU_INFO_2_TO_DS_OFFSET 0x00000008 1867 #define RX_MPDU_INFO_2_TO_DS_LSB 17 1868 #define RX_MPDU_INFO_2_TO_DS_MASK 0x00020000 1869 1870 /* Description RX_MPDU_INFO_2_ENCRYPTED 1871 1872 Field only valid when Mpdu_frame_control_valid is set. 1873 1874 1875 1876 Protected bit from the frame control. 1877 1878 <legal all> 1879 */ 1880 #define RX_MPDU_INFO_2_ENCRYPTED_OFFSET 0x00000008 1881 #define RX_MPDU_INFO_2_ENCRYPTED_LSB 18 1882 #define RX_MPDU_INFO_2_ENCRYPTED_MASK 0x00040000 1883 1884 /* Description RX_MPDU_INFO_2_MPDU_RETRY 1885 1886 Field only valid when Mpdu_frame_control_valid is set. 1887 1888 1889 1890 Retry bit from the frame control. Only valid when 1891 first_msdu is set. 1892 1893 <legal all> 1894 */ 1895 #define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET 0x00000008 1896 #define RX_MPDU_INFO_2_MPDU_RETRY_LSB 19 1897 #define RX_MPDU_INFO_2_MPDU_RETRY_MASK 0x00080000 1898 1899 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER 1900 1901 Field only valid when Mpdu_sequence_control_valid is 1902 set. 1903 1904 1905 1906 The sequence number from the 802.11 header. 1907 1908 <legal all> 1909 */ 1910 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 1911 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB 20 1912 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1913 1914 /* Description RX_MPDU_INFO_3_EPD_EN 1915 1916 Field only valid when AST_based_lookup_valid == 1. 1917 1918 1919 1920 1921 1922 In case of ndp or phy_err or AST_based_lookup_valid == 1923 0, this field will be set to 0 1924 1925 1926 1927 If set to one use EPD instead of LPD 1928 1929 1930 1931 1932 <legal all> 1933 */ 1934 #define RX_MPDU_INFO_3_EPD_EN_OFFSET 0x0000000c 1935 #define RX_MPDU_INFO_3_EPD_EN_LSB 0 1936 #define RX_MPDU_INFO_3_EPD_EN_MASK 0x00000001 1937 1938 /* Description RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED 1939 1940 In case of ndp or phy_err or AST_based_lookup_valid == 1941 0, this field will be set to 0 1942 1943 1944 1945 When set, all frames (data only ?) shall be encrypted. 1946 If not, RX CRYPTO shall set an error flag. 1947 1948 <legal all> 1949 */ 1950 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000c 1951 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 1952 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 1953 1954 /* Description RX_MPDU_INFO_3_ENCRYPT_TYPE 1955 1956 In case of ndp or phy_err or AST_based_lookup_valid == 1957 0, this field will be set to 0 1958 1959 1960 1961 Indicates type of decrypt cipher used (as defined in the 1962 peer entry) 1963 1964 1965 1966 <enum 0 wep_40> WEP 40-bit 1967 1968 <enum 1 wep_104> WEP 104-bit 1969 1970 <enum 2 tkip_no_mic> TKIP without MIC 1971 1972 <enum 3 wep_128> WEP 128-bit 1973 1974 <enum 4 tkip_with_mic> TKIP with MIC 1975 1976 <enum 5 wapi> WAPI 1977 1978 <enum 6 aes_ccmp_128> AES CCMP 128 1979 1980 <enum 7 no_cipher> No crypto 1981 1982 <enum 8 aes_ccmp_256> AES CCMP 256 1983 1984 <enum 9 aes_gcmp_128> AES CCMP 128 1985 1986 <enum 10 aes_gcmp_256> AES CCMP 256 1987 1988 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 1989 1990 1991 1992 <enum 12 wep_varied_width> WEP encryption. As for WEP 1993 per keyid the key bit width can vary, the key bit width for 1994 this MPDU will be indicated in field 1995 wep_key_width_for_variable key 1996 1997 <legal 0-12> 1998 */ 1999 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET 0x0000000c 2000 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB 2 2001 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK 0x0000003c 2002 2003 /* Description RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 2004 2005 Field only valid when key_type is set to 2006 wep_varied_width. 2007 2008 2009 2010 This field indicates the size of the wep key for this 2011 MPDU. 2012 2013 2014 2015 <enum 0 wep_varied_width_40> WEP 40-bit 2016 2017 <enum 1 wep_varied_width_104> WEP 104-bit 2018 2019 <enum 2 wep_varied_width_128> WEP 128-bit 2020 2021 2022 2023 <legal 0-2> 2024 */ 2025 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000c 2026 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 2027 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 2028 2029 /* Description RX_MPDU_INFO_3_MESH_STA 2030 2031 In case of ndp or phy_err or AST_based_lookup_valid == 2032 0, this field will be set to 0 2033 2034 2035 2036 When set, this is a Mesh (11s) STA 2037 2038 <legal all> 2039 */ 2040 #define RX_MPDU_INFO_3_MESH_STA_OFFSET 0x0000000c 2041 #define RX_MPDU_INFO_3_MESH_STA_LSB 8 2042 #define RX_MPDU_INFO_3_MESH_STA_MASK 0x00000100 2043 2044 /* Description RX_MPDU_INFO_3_BSSID_HIT 2045 2046 In case of ndp or phy_err or AST_based_lookup_valid == 2047 0, this field will be set to 0 2048 2049 2050 2051 When set, the BSSID of the incoming frame matched one of 2052 the 8 BSSID register values 2053 2054 2055 2056 <legal all> 2057 */ 2058 #define RX_MPDU_INFO_3_BSSID_HIT_OFFSET 0x0000000c 2059 #define RX_MPDU_INFO_3_BSSID_HIT_LSB 9 2060 #define RX_MPDU_INFO_3_BSSID_HIT_MASK 0x00000200 2061 2062 /* Description RX_MPDU_INFO_3_BSSID_NUMBER 2063 2064 Field only valid when bssid_hit is set. 2065 2066 2067 2068 This number indicates which one out of the 8 BSSID 2069 register values matched the incoming frame 2070 2071 <legal all> 2072 */ 2073 #define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET 0x0000000c 2074 #define RX_MPDU_INFO_3_BSSID_NUMBER_LSB 10 2075 #define RX_MPDU_INFO_3_BSSID_NUMBER_MASK 0x00003c00 2076 2077 /* Description RX_MPDU_INFO_3_TID 2078 2079 Field only valid when mpdu_qos_control_valid is set 2080 2081 2082 2083 The TID field in the QoS control field 2084 2085 <legal all> 2086 */ 2087 #define RX_MPDU_INFO_3_TID_OFFSET 0x0000000c 2088 #define RX_MPDU_INFO_3_TID_LSB 14 2089 #define RX_MPDU_INFO_3_TID_MASK 0x0003c000 2090 2091 /* Description RX_MPDU_INFO_3_RESERVED_3A 2092 2093 <legal 0> 2094 */ 2095 #define RX_MPDU_INFO_3_RESERVED_3A_OFFSET 0x0000000c 2096 #define RX_MPDU_INFO_3_RESERVED_3A_LSB 18 2097 #define RX_MPDU_INFO_3_RESERVED_3A_MASK 0xfffc0000 2098 2099 /* Description RX_MPDU_INFO_4_PN_31_0 2100 2101 2102 2103 2104 2105 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 2106 is valid. 2107 2108 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 2109 WEPSeed[1], pn1}. Only pn[47:0] is valid. 2110 2111 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 2112 pn1, pn0}. Only pn[47:0] is valid. 2113 2114 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 2115 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 2116 pn0}. pn[127:0] are valid. 2117 2118 2119 2120 */ 2121 #define RX_MPDU_INFO_4_PN_31_0_OFFSET 0x00000010 2122 #define RX_MPDU_INFO_4_PN_31_0_LSB 0 2123 #define RX_MPDU_INFO_4_PN_31_0_MASK 0xffffffff 2124 2125 /* Description RX_MPDU_INFO_5_PN_63_32 2126 2127 2128 2129 2130 Bits [63:32] of the PN number. See description for 2131 pn_31_0. 2132 2133 2134 2135 */ 2136 #define RX_MPDU_INFO_5_PN_63_32_OFFSET 0x00000014 2137 #define RX_MPDU_INFO_5_PN_63_32_LSB 0 2138 #define RX_MPDU_INFO_5_PN_63_32_MASK 0xffffffff 2139 2140 /* Description RX_MPDU_INFO_6_PN_95_64 2141 2142 2143 2144 2145 Bits [95:64] of the PN number. See description for 2146 pn_31_0. 2147 2148 2149 2150 */ 2151 #define RX_MPDU_INFO_6_PN_95_64_OFFSET 0x00000018 2152 #define RX_MPDU_INFO_6_PN_95_64_LSB 0 2153 #define RX_MPDU_INFO_6_PN_95_64_MASK 0xffffffff 2154 2155 /* Description RX_MPDU_INFO_7_PN_127_96 2156 2157 2158 2159 2160 Bits [127:96] of the PN number. See description for 2161 pn_31_0. 2162 2163 2164 2165 */ 2166 #define RX_MPDU_INFO_7_PN_127_96_OFFSET 0x0000001c 2167 #define RX_MPDU_INFO_7_PN_127_96_LSB 0 2168 #define RX_MPDU_INFO_7_PN_127_96_MASK 0xffffffff 2169 2170 /* Description RX_MPDU_INFO_8_PEER_META_DATA 2171 2172 In case of ndp or phy_err or AST_based_lookup_valid == 2173 0, this field will be set to 0 2174 2175 2176 2177 Meta data that SW has programmed in the Peer table entry 2178 of the transmitting STA. 2179 2180 <legal all> 2181 */ 2182 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 2183 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 2184 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 2185 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_OFFSET 0x00000024 2186 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_LSB 0 2187 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_MASK 0xffffffff 2188 2189 /* Description RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0 2190 2191 In case of ndp or phy_err or AST_based_lookup_valid == 2192 0, this field will be set to 0 2193 2194 2195 2196 Address (lower 32 bits) of the REO queue descriptor. 2197 2198 2199 2200 If no Peer entry lookup happened for this frame, the 2201 value wil be set to 0, and the frame shall never be pushed 2202 to REO entrance ring. 2203 2204 <legal all> 2205 */ 2206 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000028 2207 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 2208 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 2209 2210 /* Description RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32 2211 2212 In case of ndp or phy_err or AST_based_lookup_valid == 2213 0, this field will be set to 0 2214 2215 2216 2217 Address (upper 8 bits) of the REO queue descriptor. 2218 2219 2220 2221 If no Peer entry lookup happened for this frame, the 2222 value wil be set to 0, and the frame shall never be pushed 2223 to REO entrance ring. 2224 2225 <legal all> 2226 */ 2227 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000002c 2228 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 2229 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 2230 2231 /* Description RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER 2232 2233 In case of ndp or phy_err or AST_based_lookup_valid == 2234 0, this field will be set to 0 2235 2236 2237 2238 Indicates the MPDU queue ID to which this MPDU link 2239 descriptor belongs 2240 2241 Used for tracking and debugging 2242 2243 <legal all> 2244 */ 2245 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000002c 2246 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB 8 2247 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 2248 2249 /* Description RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING 2250 2251 Indicates that a delimiter FCS error was found in 2252 between the Previous MPDU and this MPDU. 2253 2254 2255 2256 Note that this is just a warning, and does not mean that 2257 this MPDU is corrupted in any way. If it is, there will be 2258 other errors indicated such as FCS or decrypt errors 2259 2260 2261 2262 In case of ndp or phy_err, this field will indicate at 2263 least one of delimiters located after the last MPDU in the 2264 previous PPDU has been corrupted. 2265 */ 2266 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c 2267 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB 24 2268 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK 0x01000000 2269 2270 /* Description RX_MPDU_INFO_11_FIRST_DELIM_ERR 2271 2272 Indicates that the first delimiter had a FCS failure. 2273 Only valid when first_mpdu and first_msdu are set. 2274 2275 2276 2277 */ 2278 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET 0x0000002c 2279 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB 25 2280 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK 0x02000000 2281 2282 /* Description RX_MPDU_INFO_11_RESERVED_11 2283 2284 <legal 0> 2285 */ 2286 #define RX_MPDU_INFO_11_RESERVED_11_OFFSET 0x0000002c 2287 #define RX_MPDU_INFO_11_RESERVED_11_LSB 26 2288 #define RX_MPDU_INFO_11_RESERVED_11_MASK 0xfc000000 2289 2290 /* Description RX_MPDU_INFO_12_KEY_ID_OCTET 2291 2292 2293 2294 2295 The key ID octet from the IV. 2296 2297 2298 2299 In case of ndp or phy_err or AST_based_lookup_valid == 2300 0, this field will be set to 0 2301 2302 <legal all> 2303 */ 2304 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 2305 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 2306 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 2307 2308 /* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY 2309 2310 In case of ndp or phy_err or AST_based_lookup_valid == 2311 0, this field will be set to 0 2312 2313 2314 2315 Set if new RX_PEER_ENTRY TLV follows. If clear, 2316 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 2317 uses old peer entry or not decrypt. 2318 2319 <legal all> 2320 */ 2321 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 2322 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 2323 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 2324 2325 /* Description RX_MPDU_INFO_12_DECRYPT_NEEDED 2326 2327 In case of ndp or phy_err or AST_based_lookup_valid == 2328 0, this field will be set to 0 2329 2330 2331 2332 Set if decryption is needed. 2333 2334 2335 2336 Note: 2337 2338 When RXPCU sets bit 'ast_index_not_found' and/or 2339 ast_index_timeout', RXPCU will also ensure that this bit is 2340 NOT set 2341 2342 CRYPTO for that reason only needs to evaluate this bit 2343 and non of the other ones. 2344 2345 <legal all> 2346 */ 2347 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 2348 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 2349 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 2350 2351 /* Description RX_MPDU_INFO_12_DECAP_TYPE 2352 2353 In case of ndp or phy_err or AST_based_lookup_valid == 2354 0, this field will be set to 0 2355 2356 2357 2358 Used by the OLE during decapsulation. 2359 2360 2361 2362 Indicates the decapsulation that HW will perform: 2363 2364 2365 2366 <enum 0 RAW> No encapsulation 2367 2368 <enum 1 Native_WiFi> 2369 2370 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 2371 SNAP/LLC) 2372 2373 <enum 3 802_3> Indicate Ethernet 2374 2375 2376 2377 <legal all> 2378 */ 2379 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 2380 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 2381 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 2382 2383 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING 2384 2385 In case of ndp or phy_err or AST_based_lookup_valid == 2386 0, this field will be set to 0 2387 2388 2389 2390 Insert 4 byte of all zeros as VLAN tag if the rx payload 2391 does not have VLAN. Used during decapsulation. 2392 2393 <legal all> 2394 */ 2395 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 2396 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 2397 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 2398 2399 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING 2400 2401 In case of ndp or phy_err or AST_based_lookup_valid == 2402 0, this field will be set to 0 2403 2404 2405 2406 Insert 4 byte of all zeros as double VLAN tag if the rx 2407 payload does not have VLAN. Used during 2408 2409 <legal all> 2410 */ 2411 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 2412 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 2413 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 2414 2415 /* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP 2416 2417 In case of ndp or phy_err or AST_based_lookup_valid == 2418 0, this field will be set to 0 2419 2420 2421 2422 Strip the VLAN during decapsulation. Used by the OLE. 2423 2424 <legal all> 2425 */ 2426 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 2427 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 2428 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 2429 2430 /* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP 2431 2432 In case of ndp or phy_err or AST_based_lookup_valid == 2433 0, this field will be set to 0 2434 2435 2436 2437 Strip the double VLAN during decapsulation. Used by 2438 the OLE. 2439 2440 <legal all> 2441 */ 2442 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 2443 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 2444 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 2445 2446 /* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT 2447 2448 The number of delimiters before this MPDU. 2449 2450 2451 2452 Note that this number is cleared at PPDU start. 2453 2454 2455 2456 If this MPDU is the first received MPDU in the PPDU and 2457 this MPDU gets filtered-in, this field will indicate the 2458 number of delimiters located after the last MPDU in the 2459 previous PPDU. 2460 2461 2462 2463 If this MPDU is located after the first received MPDU in 2464 an PPDU, this field will indicate the number of delimiters 2465 located between the previous MPDU and this MPDU. 2466 2467 2468 2469 In case of ndp or phy_err, this field will indicate the 2470 number of delimiters located after the last MPDU in the 2471 previous PPDU. 2472 2473 <legal all> 2474 */ 2475 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 2476 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 2477 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 2478 2479 /* Description RX_MPDU_INFO_12_AMPDU_FLAG 2480 2481 When set, received frame was part of an A-MPDU. 2482 2483 2484 2485 2486 <legal all> 2487 */ 2488 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 2489 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 2490 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 2491 2492 /* Description RX_MPDU_INFO_12_BAR_FRAME 2493 2494 In case of ndp or phy_err or AST_based_lookup_valid == 2495 0, this field will be set to 0 2496 2497 2498 2499 When set, received frame is a BAR frame 2500 2501 <legal all> 2502 */ 2503 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 2504 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 2505 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 2506 2507 /* Description RX_MPDU_INFO_12_RESERVED_12 2508 2509 <legal 0>. 2510 */ 2511 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 2512 #define RX_MPDU_INFO_12_RESERVED_12_LSB 30 2513 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0xc0000000 2514 2515 /* Description RX_MPDU_INFO_13_MPDU_LENGTH 2516 2517 In case of ndp or phy_err this field will be set to 0 2518 2519 2520 2521 MPDU length before decapsulation. 2522 2523 <legal all> 2524 */ 2525 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 2526 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 2527 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 2528 2529 /* Description RX_MPDU_INFO_13_FIRST_MPDU 2530 2531 See definition in RX attention descriptor 2532 2533 2534 2535 In case of ndp or phy_err, this field will be set. Note 2536 however that there will not actually be any data contents in 2537 the MPDU. 2538 2539 <legal all> 2540 */ 2541 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 2542 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 2543 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 2544 2545 /* Description RX_MPDU_INFO_13_MCAST_BCAST 2546 2547 In case of ndp or phy_err or Phy_err_during_mpdu_header 2548 this field will be set to 0 2549 2550 2551 2552 See definition in RX attention descriptor 2553 2554 <legal all> 2555 */ 2556 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 2557 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 2558 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 2559 2560 /* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND 2561 2562 In case of ndp or phy_err or Phy_err_during_mpdu_header 2563 this field will be set to 0 2564 2565 2566 2567 See definition in RX attention descriptor 2568 2569 <legal all> 2570 */ 2571 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 2572 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 2573 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 2574 2575 /* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT 2576 2577 In case of ndp or phy_err or Phy_err_during_mpdu_header 2578 this field will be set to 0 2579 2580 2581 2582 See definition in RX attention descriptor 2583 2584 <legal all> 2585 */ 2586 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 2587 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 2588 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 2589 2590 /* Description RX_MPDU_INFO_13_POWER_MGMT 2591 2592 In case of ndp or phy_err or Phy_err_during_mpdu_header 2593 this field will be set to 0 2594 2595 2596 2597 See definition in RX attention descriptor 2598 2599 <legal all> 2600 */ 2601 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 2602 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 2603 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 2604 2605 /* Description RX_MPDU_INFO_13_NON_QOS 2606 2607 In case of ndp or phy_err or Phy_err_during_mpdu_header 2608 this field will be set to 1 2609 2610 2611 2612 See definition in RX attention descriptor 2613 2614 <legal all> 2615 */ 2616 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 2617 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 2618 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 2619 2620 /* Description RX_MPDU_INFO_13_NULL_DATA 2621 2622 In case of ndp or phy_err or Phy_err_during_mpdu_header 2623 this field will be set to 0 2624 2625 2626 2627 See definition in RX attention descriptor 2628 2629 <legal all> 2630 */ 2631 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 2632 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 2633 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 2634 2635 /* Description RX_MPDU_INFO_13_MGMT_TYPE 2636 2637 In case of ndp or phy_err or Phy_err_during_mpdu_header 2638 this field will be set to 0 2639 2640 2641 2642 See definition in RX attention descriptor 2643 2644 <legal all> 2645 */ 2646 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 2647 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 2648 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 2649 2650 /* Description RX_MPDU_INFO_13_CTRL_TYPE 2651 2652 In case of ndp or phy_err or Phy_err_during_mpdu_header 2653 this field will be set to 0 2654 2655 2656 2657 See definition in RX attention descriptor 2658 2659 <legal all> 2660 */ 2661 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 2662 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 2663 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 2664 2665 /* Description RX_MPDU_INFO_13_MORE_DATA 2666 2667 In case of ndp or phy_err or Phy_err_during_mpdu_header 2668 this field will be set to 0 2669 2670 2671 2672 See definition in RX attention descriptor 2673 2674 <legal all> 2675 */ 2676 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 2677 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 2678 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 2679 2680 /* Description RX_MPDU_INFO_13_EOSP 2681 2682 In case of ndp or phy_err or Phy_err_during_mpdu_header 2683 this field will be set to 0 2684 2685 2686 2687 See definition in RX attention descriptor 2688 2689 <legal all> 2690 */ 2691 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 2692 #define RX_MPDU_INFO_13_EOSP_LSB 24 2693 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 2694 2695 /* Description RX_MPDU_INFO_13_FRAGMENT_FLAG 2696 2697 In case of ndp or phy_err or Phy_err_during_mpdu_header 2698 this field will be set to 0 2699 2700 2701 2702 See definition in RX attention descriptor 2703 2704 <legal all> 2705 */ 2706 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 2707 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 2708 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 2709 2710 /* Description RX_MPDU_INFO_13_ORDER 2711 2712 In case of ndp or phy_err or Phy_err_during_mpdu_header 2713 this field will be set to 0 2714 2715 2716 2717 See definition in RX attention descriptor 2718 2719 2720 2721 <legal all> 2722 */ 2723 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 2724 #define RX_MPDU_INFO_13_ORDER_LSB 26 2725 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 2726 2727 /* Description RX_MPDU_INFO_13_U_APSD_TRIGGER 2728 2729 In case of ndp or phy_err or Phy_err_during_mpdu_header 2730 this field will be set to 0 2731 2732 2733 2734 See definition in RX attention descriptor 2735 2736 <legal all> 2737 */ 2738 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 2739 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 2740 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 2741 2742 /* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED 2743 2744 In case of ndp or phy_err or Phy_err_during_mpdu_header 2745 this field will be set to 0 2746 2747 2748 2749 See definition in RX attention descriptor 2750 2751 <legal all> 2752 */ 2753 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 2754 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 2755 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 2756 2757 /* Description RX_MPDU_INFO_13_DIRECTED 2758 2759 In case of ndp or phy_err or Phy_err_during_mpdu_header 2760 this field will be set to 0 2761 2762 2763 2764 See definition in RX attention descriptor 2765 2766 <legal all> 2767 */ 2768 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 2769 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 2770 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 2771 2772 /* Description RX_MPDU_INFO_13_RESERVED_13 2773 2774 <legal 0> 2775 */ 2776 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 2777 #define RX_MPDU_INFO_13_RESERVED_13_LSB 30 2778 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0xc0000000 2779 2780 /* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD 2781 2782 Field only valid when Mpdu_frame_control_valid is set 2783 2784 2785 2786 The frame control field of this received MPDU. 2787 2788 2789 2790 Field only valid when Ndp_frame and phy_err are NOT set 2791 2792 2793 2794 Bytes 0 + 1 of the received MPDU 2795 2796 <legal all> 2797 */ 2798 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 2799 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 2800 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 2801 2802 /* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD 2803 2804 Field only valid when Mpdu_duration_valid is set 2805 2806 2807 2808 The duration field of this received MPDU. 2809 2810 <legal all> 2811 */ 2812 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 2813 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 2814 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 2815 2816 /* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 2817 2818 Field only valid when mac_addr_ad1_valid is set 2819 2820 2821 2822 The Least Significant 4 bytes of the Received Frames MAC 2823 Address AD1 2824 2825 <legal all> 2826 */ 2827 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 2828 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 2829 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 2830 2831 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 2832 2833 Field only valid when mac_addr_ad1_valid is set 2834 2835 2836 2837 The 2 most significant bytes of the Received Frames MAC 2838 Address AD1 2839 2840 <legal all> 2841 */ 2842 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 2843 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 2844 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 2845 2846 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 2847 2848 Field only valid when mac_addr_ad2_valid is set 2849 2850 2851 2852 The Least Significant 2 bytes of the Received Frames MAC 2853 Address AD2 2854 2855 <legal all> 2856 */ 2857 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 2858 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 2859 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 2860 2861 /* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 2862 2863 Field only valid when mac_addr_ad2_valid is set 2864 2865 2866 2867 The 4 most significant bytes of the Received Frames MAC 2868 Address AD2 2869 2870 <legal all> 2871 */ 2872 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 2873 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 2874 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 2875 2876 /* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 2877 2878 Field only valid when mac_addr_ad3_valid is set 2879 2880 2881 2882 The Least Significant 4 bytes of the Received Frames MAC 2883 Address AD3 2884 2885 <legal all> 2886 */ 2887 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 2888 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 2889 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 2890 2891 /* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 2892 2893 Field only valid when mac_addr_ad3_valid is set 2894 2895 2896 2897 The 2 most significant bytes of the Received Frames MAC 2898 Address AD3 2899 2900 <legal all> 2901 */ 2902 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 2903 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 2904 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 2905 2906 /* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD 2907 2908 2909 2910 2911 The sequence control field of the MPDU 2912 2913 <legal all> 2914 */ 2915 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 2916 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 2917 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 2918 2919 /* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 2920 2921 Field only valid when mac_addr_ad4_valid is set 2922 2923 2924 2925 The Least Significant 4 bytes of the Received Frames MAC 2926 Address AD4 2927 2928 <legal all> 2929 */ 2930 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 2931 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 2932 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 2933 2934 /* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 2935 2936 Field only valid when mac_addr_ad4_valid is set 2937 2938 2939 2940 The 2 most significant bytes of the Received Frames MAC 2941 Address AD4 2942 2943 <legal all> 2944 */ 2945 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 2946 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 2947 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 2948 2949 /* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD 2950 2951 Field only valid when mpdu_qos_control_valid is set 2952 2953 2954 2955 The sequence control field of the MPDU 2956 2957 <legal all> 2958 */ 2959 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 2960 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 2961 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 2962 2963 /* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD 2964 2965 Field only valid when mpdu_qos_control_valid is set 2966 2967 2968 2969 The HT control field of the MPDU 2970 2971 <legal all> 2972 */ 2973 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 2974 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 2975 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 2976 2977 2978 #endif // _RX_MPDU_INFO_H_ 2979