1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _TCL_STATUS_RING_H_ 20 #define _TCL_STATUS_RING_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], index_search_en[7], msdu_cnt_n[31:8] 29 // 1 msdu_byte_cnt_n[31:0] 30 // 2 msdu_timestmp_n[31:0] 31 // 3 cmd_meta_data_31_0[31:0] 32 // 4 cmd_meta_data_63_32[31:0] 33 // 5 hash_indx_val[19:0], cache_set_num[23:20], reserved_5a[31:24] 34 // 6 reserved_6a[31:0] 35 // 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] 36 // 37 // ################ END SUMMARY ################# 38 39 #define NUM_OF_DWORDS_TCL_STATUS_RING 8 40 41 struct tcl_status_ring { 42 uint32_t gse_ctrl : 4, //[3:0] 43 ase_fse_sel : 1, //[4] 44 cache_op_res : 2, //[6:5] 45 index_search_en : 1, //[7] 46 msdu_cnt_n : 24; //[31:8] 47 uint32_t msdu_byte_cnt_n : 32; //[31:0] 48 uint32_t msdu_timestmp_n : 32; //[31:0] 49 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 50 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 51 uint32_t hash_indx_val : 20, //[19:0] 52 cache_set_num : 4, //[23:20] 53 reserved_5a : 8; //[31:24] 54 uint32_t reserved_6a : 32; //[31:0] 55 uint32_t reserved_7a : 20, //[19:0] 56 ring_id : 8, //[27:20] 57 looping_count : 4; //[31:28] 58 }; 59 60 /* 61 62 gse_ctrl 63 64 GSE control operations. This includes cache operations 65 and table entry statistics read/clear operation. 66 67 <enum 0 rd_stat> Report or Read statistics 68 69 <enum 1 srch_dis> Search disable. Report only Hash 70 71 <enum 2 Wr_bk_single> Write Back single entry 72 73 <enum 3 wr_bk_all> Write Back entire cache entry 74 75 <enum 4 inval_single> Invalidate single cache entry 76 77 <enum 5 inval_all> Invalidate entire cache 78 79 <enum 6 wr_bk_inval_single> Write back and Invalidate 80 single entry in cache 81 82 <enum 7 wr_bk_inval_all> write back and invalidate 83 entire cache 84 85 <enum 8 clr_stat_single> Clear statistics for single 86 entry 87 88 <legal 0-8> 89 90 Rest of the values reserved. 91 92 For all single entry control operations (write back, 93 Invalidate or both)Statistics will be reported 94 95 ase_fse_sel 96 97 Search Engine for which operation is done. 98 99 1'b0: Address Search Engine Result 100 101 1'b1: Flow Search Engine result 102 103 cache_op_res 104 105 Cache operation result. Following are results of cache 106 operation. 107 108 <enum 0 op_done> Operation successful 109 110 <enum 1 not_fnd> Entry not found in Table 111 112 <enum 2 timeout_er> Timeout Error 113 114 <legal 0-2> 115 116 index_search_en 117 118 When this bit is set to 1 control_buffer_addr[19:0] will 119 be considered as index of the AST or Flow table and GSE 120 commands will be executed accordingly on the entry pointed 121 by the index. 122 123 This feature is disabled by setting this bit to 0. 124 125 <enum 0 index_based_cmd_disable> 126 127 <enum 1 index_based_cmd_enable> 128 129 130 131 <legal all> 132 133 msdu_cnt_n 134 135 MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and 136 4'b1000 137 138 msdu_byte_cnt_n 139 140 MSDU byte count for entry 1. Valid when GSE_CTRL is 141 4'b0111 and 4'b1000 142 143 msdu_timestmp_n 144 145 MSDU timestamp for entry 1. Valid when GSE_CTRL is 146 4'b0111 and 4'b1000 147 148 cmd_meta_data_31_0 149 150 Meta data from input ring 151 152 <legal all> 153 154 cmd_meta_data_63_32 155 156 Meta data from input ring 157 158 <legal all> 159 160 hash_indx_val 161 162 163 Hash value of the entry in table in case of search 164 failed or search disable. 165 166 <legal all> 167 168 cache_set_num 169 170 Cache set number copied from TCL_GSE_CMD 171 172 reserved_5a 173 174 <legal 0> 175 176 reserved_6a 177 178 <legal 0> 179 180 reserved_7a 181 182 <legal 0> 183 184 ring_id 185 186 The buffer pointer ring ID. 187 188 189 190 Helps with debugging when dumping ring contents. 191 192 <legal all> 193 194 looping_count 195 196 A count value that indicates the number of times the 197 producer of entries into the Ring has looped around the 198 ring. 199 200 At initialization time, this value is set to 0. On the 201 first loop, this value is set to 1. After the max value is 202 reached allowed by the number of bits for this field, the 203 count value continues with 0 again. 204 205 206 207 In case SW is the consumer of the ring entries, it can 208 use this field to figure out up to where the producer of 209 entries has created new entries. This eliminates the need to 210 check where the head pointer' of the ring is located once 211 the SW starts processing an interrupt indicating that new 212 entries have been put into this ring... 213 214 215 216 Also note that SW if it wants only needs to look at the 217 LSB bit of this count value. 218 219 <legal all> 220 */ 221 222 223 /* Description TCL_STATUS_RING_0_GSE_CTRL 224 225 GSE control operations. This includes cache operations 226 and table entry statistics read/clear operation. 227 228 <enum 0 rd_stat> Report or Read statistics 229 230 <enum 1 srch_dis> Search disable. Report only Hash 231 232 <enum 2 Wr_bk_single> Write Back single entry 233 234 <enum 3 wr_bk_all> Write Back entire cache entry 235 236 <enum 4 inval_single> Invalidate single cache entry 237 238 <enum 5 inval_all> Invalidate entire cache 239 240 <enum 6 wr_bk_inval_single> Write back and Invalidate 241 single entry in cache 242 243 <enum 7 wr_bk_inval_all> write back and invalidate 244 entire cache 245 246 <enum 8 clr_stat_single> Clear statistics for single 247 entry 248 249 <legal 0-8> 250 251 Rest of the values reserved. 252 253 For all single entry control operations (write back, 254 Invalidate or both)Statistics will be reported 255 */ 256 #define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 257 #define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 258 #define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f 259 260 /* Description TCL_STATUS_RING_0_ASE_FSE_SEL 261 262 Search Engine for which operation is done. 263 264 1'b0: Address Search Engine Result 265 266 1'b1: Flow Search Engine result 267 */ 268 #define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 269 #define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 270 #define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 271 272 /* Description TCL_STATUS_RING_0_CACHE_OP_RES 273 274 Cache operation result. Following are results of cache 275 operation. 276 277 <enum 0 op_done> Operation successful 278 279 <enum 1 not_fnd> Entry not found in Table 280 281 <enum 2 timeout_er> Timeout Error 282 283 <legal 0-2> 284 */ 285 #define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 286 #define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 287 #define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 288 289 /* Description TCL_STATUS_RING_0_INDEX_SEARCH_EN 290 291 When this bit is set to 1 control_buffer_addr[19:0] will 292 be considered as index of the AST or Flow table and GSE 293 commands will be executed accordingly on the entry pointed 294 by the index. 295 296 This feature is disabled by setting this bit to 0. 297 298 <enum 0 index_based_cmd_disable> 299 300 <enum 1 index_based_cmd_enable> 301 302 303 304 <legal all> 305 */ 306 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000 307 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7 308 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080 309 310 /* Description TCL_STATUS_RING_0_MSDU_CNT_N 311 312 MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and 313 4'b1000 314 */ 315 #define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 316 #define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 317 #define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 318 319 /* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N 320 321 MSDU byte count for entry 1. Valid when GSE_CTRL is 322 4'b0111 and 4'b1000 323 */ 324 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 325 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 326 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff 327 328 /* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N 329 330 MSDU timestamp for entry 1. Valid when GSE_CTRL is 331 4'b0111 and 4'b1000 332 */ 333 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 334 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 335 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff 336 337 /* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0 338 339 Meta data from input ring 340 341 <legal all> 342 */ 343 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c 344 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 345 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff 346 347 /* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32 348 349 Meta data from input ring 350 351 <legal all> 352 */ 353 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 354 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 355 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff 356 357 /* Description TCL_STATUS_RING_5_HASH_INDX_VAL 358 359 360 Hash value of the entry in table in case of search 361 failed or search disable. 362 363 <legal all> 364 */ 365 #define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 366 #define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 367 #define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff 368 369 /* Description TCL_STATUS_RING_5_CACHE_SET_NUM 370 371 Cache set number copied from TCL_GSE_CMD 372 */ 373 #define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014 374 #define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20 375 #define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000 376 377 /* Description TCL_STATUS_RING_5_RESERVED_5A 378 379 <legal 0> 380 */ 381 #define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 382 #define TCL_STATUS_RING_5_RESERVED_5A_LSB 24 383 #define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000 384 385 /* Description TCL_STATUS_RING_6_RESERVED_6A 386 387 <legal 0> 388 */ 389 #define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 390 #define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 391 #define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff 392 393 /* Description TCL_STATUS_RING_7_RESERVED_7A 394 395 <legal 0> 396 */ 397 #define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c 398 #define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 399 #define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff 400 401 /* Description TCL_STATUS_RING_7_RING_ID 402 403 The buffer pointer ring ID. 404 405 406 407 Helps with debugging when dumping ring contents. 408 409 <legal all> 410 */ 411 #define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c 412 #define TCL_STATUS_RING_7_RING_ID_LSB 20 413 #define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 414 415 /* Description TCL_STATUS_RING_7_LOOPING_COUNT 416 417 A count value that indicates the number of times the 418 producer of entries into the Ring has looped around the 419 ring. 420 421 At initialization time, this value is set to 0. On the 422 first loop, this value is set to 1. After the max value is 423 reached allowed by the number of bits for this field, the 424 count value continues with 0 again. 425 426 427 428 In case SW is the consumer of the ring entries, it can 429 use this field to figure out up to where the producer of 430 entries has created new entries. This eliminates the need to 431 check where the head pointer' of the ring is located once 432 the SW starts processing an interrupt indicating that new 433 entries have been put into this ring... 434 435 436 437 Also note that SW if it wants only needs to look at the 438 LSB bit of this count value. 439 440 <legal all> 441 */ 442 #define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 443 #define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 444 #define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 445 446 447 #endif // _TCL_STATUS_RING_H_ 448