1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 12/1/2017 22 // User Name:gunjans 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __WCSS_SEQ_BASE_H__ 29 #define __WCSS_SEQ_BASE_H__ 30 31 #ifdef SCALE_INCLUDES 32 #include "HALhwio.h" 33 #else 34 #include "msmhwio.h" 35 #endif 36 37 #ifndef SOC_WCSS_BASE_ADDR 38 #if ( defined(WCSS_BASE) && ( WCSS_BASE != 0x0 ) ) 39 #error WCSS_BASE incorrectly redefined! 40 #endif 41 #define SOC_WCSS_BASE_ADDR 0x0 42 #else 43 #if ( SOC_WCSS_BASE_ADDR != 0x0 ) 44 #error SOC_WCSS_BASE_ADDR incorrectly redefined! 45 #endif 46 #endif 47 48 /////////////////////////////////////////////////////////////////////////////////////////////// 49 // Instance Relative Offsets from Block wcss 50 /////////////////////////////////////////////////////////////////////////////////////////////// 51 52 #define SEQ_WCSS_ECAHB_OFFSET 0x00008400 53 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 54 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 55 #define SEQ_WCSS_MPSS_OFFSET 0x00200000 56 #define SEQ_WCSS_MPSS_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET 0x00200000 57 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_OFFSET 0x00280000 58 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00281800 59 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET 0x00281c00 60 #define SEQ_WCSS_PHYA_OFFSET 0x00400000 61 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 62 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 63 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 64 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 65 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 66 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 67 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 68 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00481800 69 #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00481c00 70 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC5_REG_MAP_OFFSET 0x00482c00 71 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00484000 72 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 73 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_NPRA1_REG_MAP_OFFSET 0x00490000 74 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 75 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 76 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 77 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00530000 78 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 79 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 80 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 81 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 82 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 83 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 84 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d4c00 85 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x005d5000 86 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x005d5040 87 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x005d5080 88 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x005d50c0 89 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x005d5400 90 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 91 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 92 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6080 93 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d60c0 94 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6100 95 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6140 96 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6200 97 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 98 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 99 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6880 100 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d68c0 101 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6900 102 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6940 103 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a00 104 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x005d7c00 105 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x005d8000 106 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x005d8000 107 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x005d8400 108 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x005d8800 109 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x005d8880 110 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0 111 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x005d8940 112 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x005d8980 113 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000 114 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x005dc000 115 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH1_OFFSET 0x005dc400 116 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH0_OFFSET 0x005dc600 117 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dc800 118 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dc840 119 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dc880 120 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dc8c0 121 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 122 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000 123 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x005e0400 124 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x005e0800 125 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000 126 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300 127 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x005e1600 128 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_2G_CH0_OFFSET 0x005e1640 129 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e2000 130 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x005e2400 131 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x005e2500 132 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x005e2580 133 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x005e2590 134 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x005e2600 135 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x005e26c0 136 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x005e2740 137 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x005e2768 138 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000 139 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000 140 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x005e8400 141 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x005e8800 142 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9180 143 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9480 144 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x005e9600 145 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_5G_CH0_OFFSET 0x005e9640 146 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000 147 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x005ea400 148 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x005ea500 149 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x005ea580 150 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x005ea590 151 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x005ea600 152 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x005ea6c0 153 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x005ea740 154 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x005ea768 155 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000 156 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x005f0000 157 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x005f0400 158 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x005f0800 159 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x005f1000 160 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300 161 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x005f1600 162 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_2G_CH1_OFFSET 0x005f1640 163 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000 164 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x005f2400 165 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x005f2500 166 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x005f2580 167 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x005f2590 168 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x005f2600 169 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x005f26c0 170 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x005f2740 171 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x005f2768 172 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x005f4000 173 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000 174 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x005f8400 175 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x005f8800 176 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x005f9180 177 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9480 178 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x005f9600 179 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_5G_CH1_OFFSET 0x005f9640 180 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x005fa000 181 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x005fa400 182 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x005fa500 183 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x005fa580 184 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x005fa590 185 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x005fa600 186 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x005fa6c0 187 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x005fa740 188 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x005fa768 189 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x005fc000 190 #define SEQ_WCSS_PHYB_OFFSET 0x00600000 191 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00600000 192 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00680000 193 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00680400 194 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00680800 195 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00680c00 196 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00681000 197 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00681400 198 #define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00681800 199 #define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00681c00 200 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET 0x00682c00 201 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00684000 202 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00688000 203 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00700000 204 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00720000 205 #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00728000 206 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00730000 207 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x007a0000 208 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x007c0000 209 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x007d4000 210 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000 211 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4300 212 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4800 213 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x007d4c00 214 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x007d5000 215 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x007d5040 216 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x007d5080 217 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x007d50c0 218 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x007d5400 219 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 220 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 221 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6080 222 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d60c0 223 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6100 224 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6140 225 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x007d6200 226 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 227 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 228 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d6880 229 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d68c0 230 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6900 231 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6940 232 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a00 233 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x007d7c00 234 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_OFFSET 0x007d8000 235 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_MC_OFFSET 0x007d8000 236 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_RX_OFFSET 0x007d8400 237 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x007d8800 238 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x007d8880 239 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x007d88c0 240 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x007d8940 241 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x007d8980 242 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET 0x007dc000 243 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x007dc000 244 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH1_OFFSET 0x007dc400 245 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH0_OFFSET 0x007dc600 246 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x007dc800 247 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x007dc840 248 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x007dc880 249 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x007dc8c0 250 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x007e0000 251 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x007e0000 252 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x007e0400 253 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x007e0800 254 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x007e1000 255 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x007e1300 256 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x007e1600 257 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_2G_CH0_OFFSET 0x007e1640 258 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x007e2000 259 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x007e2400 260 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x007e2500 261 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x007e2580 262 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x007e2590 263 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x007e2600 264 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x007e26c0 265 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x007e2740 266 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x007e2768 267 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x007e4000 268 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x007e8000 269 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x007e8400 270 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x007e8800 271 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x007e9180 272 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x007e9480 273 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x007e9600 274 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_5G_CH0_OFFSET 0x007e9640 275 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x007ea000 276 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x007ea400 277 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x007ea500 278 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x007ea580 279 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x007ea590 280 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x007ea600 281 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x007ea6c0 282 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x007ea740 283 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x007ea768 284 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x007ec000 285 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x007f0000 286 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x007f0400 287 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x007f0800 288 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x007f1000 289 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x007f1300 290 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x007f1600 291 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_2G_CH1_OFFSET 0x007f1640 292 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x007f2000 293 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x007f2400 294 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x007f2500 295 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x007f2580 296 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x007f2590 297 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x007f2600 298 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x007f26c0 299 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x007f2740 300 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x007f2768 301 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x007f4000 302 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x007f8000 303 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x007f8400 304 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x007f8800 305 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x007f9180 306 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x007f9480 307 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x007f9600 308 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_5G_CH1_OFFSET 0x007f9640 309 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x007fa000 310 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x007fa400 311 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x007fa500 312 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x007fa580 313 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x007fa590 314 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x007fa600 315 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x007fa6c0 316 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x007fa740 317 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x007fa768 318 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x007fc000 319 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 320 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 321 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 322 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 323 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 324 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 325 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 326 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 327 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 328 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 329 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 330 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 331 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 332 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 333 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 334 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 335 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 336 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 337 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 338 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 339 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 340 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 341 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 342 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 343 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 344 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 345 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 346 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 347 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 348 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 349 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 350 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 351 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 352 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 353 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 354 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 355 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 356 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 357 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 358 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 359 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 360 #define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET 0x00a4a000 361 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 362 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 363 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 364 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 365 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 366 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 367 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 368 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 369 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 370 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 371 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 372 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 373 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 374 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 375 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 376 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 377 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 378 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 379 #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 380 #define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET 0x00ab9000 381 #define SEQ_WCSS_WMAC1_OFFSET 0x00b00000 382 #define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00b00000 383 #define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00b03000 384 #define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00b06000 385 #define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00b09000 386 #define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00b0c000 387 #define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00b0f000 388 #define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00b12000 389 #define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00b15000 390 #define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 391 #define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00b1b000 392 #define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00b1e000 393 #define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 394 #define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00b24000 395 #define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00b27000 396 #define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00b2a000 397 #define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00b30000 398 #define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00b33000 399 #define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00b36000 400 #define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00b39000 401 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 402 #define SEQ_WCSS_WCMN_OFFSET 0x00b50000 403 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 404 #define SEQ_WCSS_PMM_OFFSET 0x00b70000 405 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 406 #define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 407 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 408 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 409 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000 410 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 411 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 412 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000 413 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280 414 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000 415 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000 416 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280 417 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000 418 #define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000 419 #define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000 420 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000 421 #define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00ba0000 422 #define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000 423 #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_10T_8CH_OFFSET 0x00bb1000 424 #define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000 425 #define SEQ_WCSS_DBG_PHYA_CPU0_M3_AHB_AP_OFFSET 0x00bbe000 426 #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000 427 #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_10T_8CH_OFFSET 0x00bc1000 428 #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000 429 #define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x00bce000 430 #define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00bf0000 431 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf1000 432 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 433 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 434 #define SEQ_WCSS_CC_OFFSET 0x00c30000 435 #define SEQ_WCSS_ACMT_OFFSET 0x00c40000 436 #define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 437 #define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 438 #define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 439 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000 440 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000 441 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 442 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000 443 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000 444 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000 445 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 446 447 448 /////////////////////////////////////////////////////////////////////////////////////////////// 449 // Instance Relative Offsets from Block mpss_top 450 /////////////////////////////////////////////////////////////////////////////////////////////// 451 452 #define SEQ_MPSS_TOP_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET 0x00000000 453 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_OFFSET 0x00080000 454 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00081800 455 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET 0x00081c00 456 457 458 /////////////////////////////////////////////////////////////////////////////////////////////// 459 // Instance Relative Offsets from Block wfax_top 460 /////////////////////////////////////////////////////////////////////////////////////////////// 461 462 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 463 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 464 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 465 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 466 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 467 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 468 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 469 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 470 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 471 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC5_REG_MAP_OFFSET 0x00082c00 472 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000 473 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000 474 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_NPRA1_REG_MAP_OFFSET 0x00090000 475 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 476 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000 477 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 478 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00130000 479 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 480 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000 481 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000 482 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 483 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 484 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 485 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00 486 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x001d5000 487 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x001d5040 488 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x001d5080 489 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x001d50c0 490 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400 491 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 492 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 493 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080 494 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0 495 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100 496 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140 497 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200 498 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 499 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 500 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880 501 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0 502 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900 503 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940 504 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00 505 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00 506 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x001d8000 507 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x001d8000 508 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x001d8400 509 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x001d8800 510 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x001d8880 511 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x001d88c0 512 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x001d8940 513 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x001d8980 514 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x001dc000 515 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x001dc000 516 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH1_OFFSET 0x001dc400 517 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH0_OFFSET 0x001dc600 518 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x001dc800 519 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dc840 520 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x001dc880 521 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x001dc8c0 522 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000 523 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x001e0000 524 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400 525 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800 526 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000 527 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300 528 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x001e1600 529 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_2G_CH0_OFFSET 0x001e1640 530 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000 531 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400 532 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x001e2500 533 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580 534 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x001e2590 535 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x001e2600 536 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x001e26c0 537 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x001e2740 538 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x001e2768 539 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x001e4000 540 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x001e8000 541 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400 542 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800 543 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9180 544 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9480 545 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x001e9600 546 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_5G_CH0_OFFSET 0x001e9640 547 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000 548 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400 549 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x001ea500 550 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580 551 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x001ea590 552 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x001ea600 553 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x001ea6c0 554 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x001ea740 555 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x001ea768 556 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x001ec000 557 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x001f0000 558 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400 559 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800 560 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000 561 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300 562 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x001f1600 563 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_2G_CH1_OFFSET 0x001f1640 564 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000 565 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400 566 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x001f2500 567 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580 568 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x001f2590 569 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x001f2600 570 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x001f26c0 571 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x001f2740 572 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x001f2768 573 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000 574 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000 575 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400 576 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800 577 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9180 578 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9480 579 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x001f9600 580 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_5G_CH1_OFFSET 0x001f9640 581 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000 582 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400 583 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x001fa500 584 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580 585 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x001fa590 586 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x001fa600 587 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x001fa6c0 588 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x001fa740 589 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x001fa768 590 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x001fc000 591 592 593 /////////////////////////////////////////////////////////////////////////////////////////////// 594 // Instance Relative Offsets from Block rfa_from_wsi 595 /////////////////////////////////////////////////////////////////////////////////////////////// 596 597 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 598 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 599 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 600 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 601 #define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00014c00 602 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_BS_OFFSET 0x00015000 603 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_BIST_OFFSET 0x00015040 604 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_PC_OFFSET 0x00015080 605 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_AC_OFFSET 0x000150c0 606 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00015400 607 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 608 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 609 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016080 610 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000160c0 611 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016100 612 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00016140 613 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016200 614 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 615 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 616 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016880 617 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000168c0 618 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016900 619 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016940 620 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a00 621 #define SEQ_RFA_FROM_WSI_RFA_CMN_DRM_REG_OFFSET 0x00017c00 622 #define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET 0x00018000 623 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET 0x00018000 624 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET 0x00018400 625 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BS_OFFSET 0x00018800 626 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00018880 627 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000188c0 628 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET 0x00018940 629 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET 0x00018980 630 #define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 631 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH2_OFFSET 0x0001c000 632 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH1_OFFSET 0x0001c400 633 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH0_OFFSET 0x0001c600 634 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001c800 635 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001c840 636 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001c880 637 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001c8c0 638 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 639 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000 640 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x00020400 641 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x00020800 642 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000 643 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300 644 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x00021600 645 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_2G_CH0_OFFSET 0x00021640 646 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00022000 647 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x00022400 648 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x00022500 649 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x00022580 650 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x00022590 651 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x00022600 652 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x000226c0 653 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x00022740 654 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x00022768 655 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000 656 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000 657 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x00028400 658 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x00028800 659 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029180 660 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029480 661 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x00029600 662 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_5G_CH0_OFFSET 0x00029640 663 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000 664 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x0002a400 665 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x0002a500 666 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x0002a580 667 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x0002a590 668 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x0002a600 669 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x0002a6c0 670 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x0002a740 671 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x0002a768 672 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000 673 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00030000 674 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x00030400 675 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x00030800 676 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00031000 677 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00031300 678 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x00031600 679 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_2G_CH1_OFFSET 0x00031640 680 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00032000 681 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x00032400 682 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x00032500 683 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x00032580 684 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x00032590 685 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x00032600 686 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x000326c0 687 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x00032740 688 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x00032768 689 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00034000 690 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00038000 691 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00038400 692 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x00038800 693 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00039180 694 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00039480 695 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x00039600 696 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_5G_CH1_OFFSET 0x00039640 697 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0003a000 698 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x0003a400 699 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x0003a500 700 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x0003a580 701 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x0003a590 702 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x0003a600 703 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x0003a6c0 704 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x0003a740 705 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x0003a768 706 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0003c000 707 708 709 /////////////////////////////////////////////////////////////////////////////////////////////// 710 // Instance Relative Offsets from Block rfa_cmn 711 /////////////////////////////////////////////////////////////////////////////////////////////// 712 713 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 714 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 715 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 716 #define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00000c00 717 #define SEQ_RFA_CMN_BBPLL_BS_OFFSET 0x00001000 718 #define SEQ_RFA_CMN_BBPLL_BIST_OFFSET 0x00001040 719 #define SEQ_RFA_CMN_BBPLL_PC_OFFSET 0x00001080 720 #define SEQ_RFA_CMN_BBPLL_AC_OFFSET 0x000010c0 721 #define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00001400 722 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 723 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 724 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002080 725 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000020c0 726 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002100 727 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00002140 728 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002200 729 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 730 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 731 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002880 732 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000028c0 733 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002900 734 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002940 735 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a00 736 #define SEQ_RFA_CMN_DRM_REG_OFFSET 0x00003c00 737 738 739 /////////////////////////////////////////////////////////////////////////////////////////////// 740 // Instance Relative Offsets from Block rfa_fm 741 /////////////////////////////////////////////////////////////////////////////////////////////// 742 743 #define SEQ_RFA_FM_FM_MC_OFFSET 0x00000000 744 #define SEQ_RFA_FM_FM_RX_OFFSET 0x00000400 745 #define SEQ_RFA_FM_FM_SYNTH_BS_OFFSET 0x00000800 746 #define SEQ_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00000880 747 #define SEQ_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000008c0 748 #define SEQ_RFA_FM_FM_SYNTH_PC_OFFSET 0x00000940 749 #define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET 0x00000980 750 751 752 /////////////////////////////////////////////////////////////////////////////////////////////// 753 // Instance Relative Offsets from Block rfa_bt 754 /////////////////////////////////////////////////////////////////////////////////////////////// 755 756 #define SEQ_RFA_BT_BT_CH2_OFFSET 0x00000000 757 #define SEQ_RFA_BT_BT_CH1_OFFSET 0x00000400 758 #define SEQ_RFA_BT_BT_CH0_OFFSET 0x00000600 759 #define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00000800 760 #define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00000840 761 #define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00000880 762 #define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x000008c0 763 764 765 /////////////////////////////////////////////////////////////////////////////////////////////// 766 // Instance Relative Offsets from Block rfa_wl 767 /////////////////////////////////////////////////////////////////////////////////////////////// 768 769 #define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000 770 #define SEQ_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x00000400 771 #define SEQ_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x00000800 772 #define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000 773 #define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300 774 #define SEQ_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x00001600 775 #define SEQ_RFA_WL_WL_LO_2G_CH0_OFFSET 0x00001640 776 #define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00002000 777 #define SEQ_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x00002400 778 #define SEQ_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x00002500 779 #define SEQ_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x00002580 780 #define SEQ_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x00002590 781 #define SEQ_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x00002600 782 #define SEQ_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x000026c0 783 #define SEQ_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x00002740 784 #define SEQ_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x00002768 785 #define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000 786 #define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000 787 #define SEQ_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x00008400 788 #define SEQ_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x00008800 789 #define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009180 790 #define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009480 791 #define SEQ_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x00009600 792 #define SEQ_RFA_WL_WL_LO_5G_CH0_OFFSET 0x00009640 793 #define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000 794 #define SEQ_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x0000a400 795 #define SEQ_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x0000a500 796 #define SEQ_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x0000a580 797 #define SEQ_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x0000a590 798 #define SEQ_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x0000a600 799 #define SEQ_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x0000a6c0 800 #define SEQ_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x0000a740 801 #define SEQ_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x0000a768 802 #define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000 803 #define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00010000 804 #define SEQ_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x00010400 805 #define SEQ_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x00010800 806 #define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00011000 807 #define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00011300 808 #define SEQ_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x00011600 809 #define SEQ_RFA_WL_WL_LO_2G_CH1_OFFSET 0x00011640 810 #define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00012000 811 #define SEQ_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x00012400 812 #define SEQ_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x00012500 813 #define SEQ_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x00012580 814 #define SEQ_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x00012590 815 #define SEQ_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x00012600 816 #define SEQ_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x000126c0 817 #define SEQ_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x00012740 818 #define SEQ_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x00012768 819 #define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00014000 820 #define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00018000 821 #define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00018400 822 #define SEQ_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x00018800 823 #define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00019180 824 #define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00019480 825 #define SEQ_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x00019600 826 #define SEQ_RFA_WL_WL_LO_5G_CH1_OFFSET 0x00019640 827 #define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0001a000 828 #define SEQ_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x0001a400 829 #define SEQ_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x0001a500 830 #define SEQ_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x0001a580 831 #define SEQ_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x0001a590 832 #define SEQ_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x0001a600 833 #define SEQ_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x0001a6c0 834 #define SEQ_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x0001a740 835 #define SEQ_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x0001a768 836 #define SEQ_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0001c000 837 838 839 /////////////////////////////////////////////////////////////////////////////////////////////// 840 // Instance Relative Offsets from Block wfax_top_b 841 /////////////////////////////////////////////////////////////////////////////////////////////// 842 843 #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 844 #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 845 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 846 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 847 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 848 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 849 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 850 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00081800 851 #define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00081c00 852 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET 0x00082c00 853 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 854 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 855 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 856 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 857 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 858 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00130000 859 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 860 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 861 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 862 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 863 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 864 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 865 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00 866 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x001d5000 867 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x001d5040 868 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x001d5080 869 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x001d50c0 870 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400 871 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 872 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 873 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080 874 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0 875 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100 876 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140 877 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200 878 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 879 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 880 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880 881 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0 882 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900 883 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940 884 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00 885 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00 886 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_OFFSET 0x001d8000 887 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_MC_OFFSET 0x001d8000 888 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_RX_OFFSET 0x001d8400 889 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x001d8800 890 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x001d8880 891 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x001d88c0 892 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x001d8940 893 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x001d8980 894 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET 0x001dc000 895 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x001dc000 896 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH1_OFFSET 0x001dc400 897 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH0_OFFSET 0x001dc600 898 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x001dc800 899 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dc840 900 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x001dc880 901 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x001dc8c0 902 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 903 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x001e0000 904 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400 905 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800 906 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000 907 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300 908 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x001e1600 909 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_2G_CH0_OFFSET 0x001e1640 910 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000 911 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400 912 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x001e2500 913 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580 914 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x001e2590 915 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x001e2600 916 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x001e26c0 917 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x001e2740 918 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x001e2768 919 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x001e4000 920 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x001e8000 921 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400 922 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800 923 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9180 924 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9480 925 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x001e9600 926 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_5G_CH0_OFFSET 0x001e9640 927 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000 928 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400 929 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x001ea500 930 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580 931 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x001ea590 932 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x001ea600 933 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x001ea6c0 934 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x001ea740 935 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x001ea768 936 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x001ec000 937 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x001f0000 938 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400 939 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800 940 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000 941 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300 942 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x001f1600 943 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_2G_CH1_OFFSET 0x001f1640 944 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000 945 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400 946 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x001f2500 947 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580 948 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x001f2590 949 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x001f2600 950 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x001f26c0 951 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x001f2740 952 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x001f2768 953 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000 954 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000 955 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400 956 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800 957 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9180 958 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9480 959 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x001f9600 960 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_5G_CH1_OFFSET 0x001f9640 961 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000 962 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400 963 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x001fa500 964 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580 965 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x001fa590 966 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x001fa600 967 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x001fa6c0 968 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x001fa740 969 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x001fa768 970 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x001fc000 971 972 973 /////////////////////////////////////////////////////////////////////////////////////////////// 974 // Instance Relative Offsets from Block umac_top_reg 975 /////////////////////////////////////////////////////////////////////////////////////////////// 976 977 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 978 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 979 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 980 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 981 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 982 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 983 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 984 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 985 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 986 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 987 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 988 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 989 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 990 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 991 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 992 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 993 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 994 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 995 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 996 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 997 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 998 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 999 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 1000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 1001 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 1002 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 1003 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 1004 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 1005 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 1006 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 1007 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 1008 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 1009 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 1010 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 1011 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 1012 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 1013 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 1014 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 1015 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 1016 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 1017 #define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0004a000 1018 1019 1020 /////////////////////////////////////////////////////////////////////////////////////////////// 1021 // Instance Relative Offsets from Block wfss_ce_reg 1022 /////////////////////////////////////////////////////////////////////////////////////////////// 1023 1024 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 1025 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 1026 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 1027 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 1028 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 1029 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 1030 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 1031 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 1032 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 1033 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 1034 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 1035 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 1036 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 1037 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 1038 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 1039 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 1040 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 1041 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 1042 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 1043 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 1044 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 1045 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 1046 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 1047 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 1048 #define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 1049 1050 1051 /////////////////////////////////////////////////////////////////////////////////////////////// 1052 // Instance Relative Offsets from Block cxc_top_reg 1053 /////////////////////////////////////////////////////////////////////////////////////////////// 1054 1055 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 1056 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 1057 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 1058 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 1059 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 1060 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 1061 1062 1063 /////////////////////////////////////////////////////////////////////////////////////////////// 1064 // Instance Relative Offsets from Block wmac_top_reg 1065 /////////////////////////////////////////////////////////////////////////////////////////////// 1066 1067 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 1068 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 1069 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 1070 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 1071 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 1072 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 1073 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 1074 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 1075 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 1076 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 1077 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 1078 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 1079 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 1080 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 1081 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 1082 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 1083 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 1084 #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 1085 #define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET 0x00039000 1086 1087 1088 /////////////////////////////////////////////////////////////////////////////////////////////// 1089 // Instance Relative Offsets from Block wcssdbg_napier 1090 /////////////////////////////////////////////////////////////////////////////////////////////// 1091 1092 #define SEQ_WCSSDBG_NAPIER_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 1093 #define SEQ_WCSSDBG_NAPIER_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 1094 #define SEQ_WCSSDBG_NAPIER_TSGEN_CXTSGEN_OFFSET 0x00002000 1095 #define SEQ_WCSSDBG_NAPIER_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 1096 #define SEQ_WCSSDBG_NAPIER_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 1097 #define SEQ_WCSSDBG_NAPIER_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 1098 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 1099 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 1100 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 1101 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 1102 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 1103 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 1104 #define SEQ_WCSSDBG_NAPIER_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 1105 #define SEQ_WCSSDBG_NAPIER_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 1106 #define SEQ_WCSSDBG_NAPIER_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 1107 #define SEQ_WCSSDBG_NAPIER_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000 1108 #define SEQ_WCSSDBG_NAPIER_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 1109 #define SEQ_WCSSDBG_NAPIER_PHYA_CTI_QC_CTI_10T_8CH_OFFSET 0x00021000 1110 #define SEQ_WCSSDBG_NAPIER_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 1111 #define SEQ_WCSSDBG_NAPIER_PHYA_CPU0_M3_AHB_AP_OFFSET 0x0002e000 1112 #define SEQ_WCSSDBG_NAPIER_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 1113 #define SEQ_WCSSDBG_NAPIER_PHYB_CTI_QC_CTI_10T_8CH_OFFSET 0x00031000 1114 #define SEQ_WCSSDBG_NAPIER_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 1115 #define SEQ_WCSSDBG_NAPIER_PHYB_CPU0_M3_AHB_AP_OFFSET 0x0003e000 1116 #define SEQ_WCSSDBG_NAPIER_UMAC_CPU_M3_AHB_AP_OFFSET 0x00060000 1117 #define SEQ_WCSSDBG_NAPIER_BUS_TIMEOUT_OFFSET 0x00061000 1118 1119 1120 /////////////////////////////////////////////////////////////////////////////////////////////// 1121 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 1122 /////////////////////////////////////////////////////////////////////////////////////////////// 1123 1124 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 1125 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 1126 1127 1128 /////////////////////////////////////////////////////////////////////////////////////////////// 1129 // Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd 1130 /////////////////////////////////////////////////////////////////////////////////////////////// 1131 1132 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280 1133 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 1134 1135 1136 /////////////////////////////////////////////////////////////////////////////////////////////// 1137 // Instance Relative Offsets from Block qdsp6ss_public 1138 /////////////////////////////////////////////////////////////////////////////////////////////// 1139 1140 #define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET 0x00000000 1141 1142 1143 /////////////////////////////////////////////////////////////////////////////////////////////// 1144 // Instance Relative Offsets from Block qdsp6ss_private 1145 /////////////////////////////////////////////////////////////////////////////////////////////// 1146 1147 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET 0x00000000 1148 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET 0x00010000 1149 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 1150 #define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 1151 #define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 1152 #define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 1153 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET 0x00030000 1154 1155 1156 #endif 1157 1158