1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 10/27/2016 22 // User Name:kanalas 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __MAC_TCL_REG_SEQ_REG_H__ 29 #define __MAC_TCL_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "mac_tcl_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block MAC_TCL_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register TCL_R0_SW2TCL1_RING_CTRL //// 45 46 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) 47 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) 48 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 49 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 50 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ 51 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) 52 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ 53 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 54 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ 55 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) 56 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 64 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 65 66 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 67 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 68 69 //// Register TCL_R0_SW2TCL2_RING_CTRL //// 70 71 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) 72 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) 73 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 74 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 75 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ 76 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) 77 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ 78 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 79 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ 80 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) 81 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ 82 do {\ 83 HWIO_INTLOCK(); \ 84 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ 85 HWIO_INTFREE();\ 86 } while (0) 87 88 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 89 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 90 91 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 92 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 93 94 //// Register TCL_R0_SW2TCL3_RING_CTRL //// 95 96 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) 97 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) 98 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 99 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 100 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ 101 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) 102 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ 103 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 104 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ 105 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) 106 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ 107 do {\ 108 HWIO_INTLOCK(); \ 109 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ 110 HWIO_INTFREE();\ 111 } while (0) 112 113 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 114 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 115 116 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 117 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 118 119 //// Register TCL_R0_FW2TCL1_RING_CTRL //// 120 121 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) 122 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) 123 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 124 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 125 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ 126 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) 127 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ 128 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 129 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ 130 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) 131 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 132 do {\ 133 HWIO_INTLOCK(); \ 134 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ 135 HWIO_INTFREE();\ 136 } while (0) 137 138 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 139 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 140 141 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 142 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 143 144 //// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// 145 146 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) 147 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) 148 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0003ffe0 149 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 5 150 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ 151 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) 152 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ 153 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) 154 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val) \ 155 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val) 156 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val) \ 157 do {\ 158 HWIO_INTLOCK(); \ 159 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \ 160 HWIO_INTFREE();\ 161 } while (0) 162 163 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 164 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 165 166 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 167 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 168 169 //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// 170 171 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) 172 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) 173 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x00001fff 174 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 175 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ 176 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) 177 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ 178 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 179 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ 180 out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) 181 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ 182 do {\ 183 HWIO_INTLOCK(); \ 184 out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ 185 HWIO_INTFREE();\ 186 } while (0) 187 188 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_BMSK 0x00001000 189 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_SHFT 0xc 190 191 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 192 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb 193 194 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 195 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa 196 197 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 198 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 199 200 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 201 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 202 203 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_BMSK 0x00000080 204 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_SHFT 0x7 205 206 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 207 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 208 209 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 210 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 211 212 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 213 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 214 215 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 216 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 217 218 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 219 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 220 221 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 222 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 223 224 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 225 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 226 227 //// Register TCL_R0_TCL2TQM_RING_CTRL //// 228 229 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) 230 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) 231 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x00000fff 232 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 233 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ 234 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) 235 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ 236 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 237 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ 238 out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) 239 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ 240 do {\ 241 HWIO_INTLOCK(); \ 242 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ 243 HWIO_INTFREE();\ 244 } while (0) 245 246 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 247 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 248 249 //// Register TCL_R0_TCL2FW_RING_CTRL //// 250 251 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) 252 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) 253 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff 254 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 255 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ 256 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) 257 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ 258 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 259 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ 260 out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) 261 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ 262 do {\ 263 HWIO_INTLOCK(); \ 264 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ 265 HWIO_INTFREE();\ 266 } while (0) 267 268 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 269 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 270 271 //// Register TCL_R0_TCL_STATUS1_RING_CTRL //// 272 273 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) 274 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) 275 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff 276 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 277 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ 278 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) 279 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ 280 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 281 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ 282 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) 283 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ 284 do {\ 285 HWIO_INTLOCK(); \ 286 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ 287 HWIO_INTFREE();\ 288 } while (0) 289 290 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 291 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 292 293 //// Register TCL_R0_TCL_STATUS2_RING_CTRL //// 294 295 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) 296 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) 297 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff 298 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 299 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ 300 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) 301 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ 302 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 303 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ 304 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) 305 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ 306 do {\ 307 HWIO_INTLOCK(); \ 308 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ 309 HWIO_INTFREE();\ 310 } while (0) 311 312 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 313 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 314 315 //// Register TCL_R0_GEN_CTRL //// 316 317 #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) 318 #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) 319 #define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffff7ffd 320 #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 321 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ 322 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) 323 #define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ 324 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 325 #define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ 326 out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) 327 #define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ 328 do {\ 329 HWIO_INTLOCK(); \ 330 out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ 331 HWIO_INTFREE();\ 332 } while (0) 333 334 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 335 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 336 337 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 338 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe 339 340 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 341 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd 342 343 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 344 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc 345 346 #define HWIO_TCL_R0_GEN_CTRL_MAC_ID_BMSK 0x00000e00 347 #define HWIO_TCL_R0_GEN_CTRL_MAC_ID_SHFT 0x9 348 349 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 350 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 351 352 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 353 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 354 355 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 356 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 357 358 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 359 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 360 361 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 362 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 363 364 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 365 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 366 367 #define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_BMSK 0x00000004 368 #define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_SHFT 0x2 369 370 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 371 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 372 373 //// Register TCL_R0_DSCP_TID1_MAP_0 //// 374 375 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x) (x+0x0000002c) 376 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_PHYS(x) (x+0x0000002c) 377 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK 0x3fffffff 378 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_SHFT 0 379 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x) \ 380 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK) 381 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_INM(x, mask) \ 382 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask) 383 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUT(x, val) \ 384 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), val) 385 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUTM(x, mask, val) \ 386 do {\ 387 HWIO_INTLOCK(); \ 388 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)); \ 389 HWIO_INTFREE();\ 390 } while (0) 391 392 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_BMSK 0x38000000 393 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT 0x1b 394 395 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_BMSK 0x07000000 396 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT 0x18 397 398 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_BMSK 0x00e00000 399 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT 0x15 400 401 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_BMSK 0x001c0000 402 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT 0x12 403 404 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_BMSK 0x00038000 405 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT 0xf 406 407 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_BMSK 0x00007000 408 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT 0xc 409 410 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_BMSK 0x00000e00 411 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT 0x9 412 413 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_BMSK 0x000001c0 414 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT 0x6 415 416 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_BMSK 0x00000038 417 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT 0x3 418 419 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_BMSK 0x00000007 420 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_SHFT 0x0 421 422 //// Register TCL_R0_DSCP_TID1_MAP_1 //// 423 424 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x) (x+0x00000030) 425 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_PHYS(x) (x+0x00000030) 426 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK 0x3fffffff 427 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_SHFT 0 428 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x) \ 429 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK) 430 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_INM(x, mask) \ 431 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask) 432 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUT(x, val) \ 433 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), val) 434 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUTM(x, mask, val) \ 435 do {\ 436 HWIO_INTLOCK(); \ 437 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)); \ 438 HWIO_INTFREE();\ 439 } while (0) 440 441 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_BMSK 0x38000000 442 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_SHFT 0x1b 443 444 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_BMSK 0x07000000 445 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_SHFT 0x18 446 447 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_BMSK 0x00e00000 448 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_SHFT 0x15 449 450 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_BMSK 0x001c0000 451 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_SHFT 0x12 452 453 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_BMSK 0x00038000 454 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_SHFT 0xf 455 456 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_BMSK 0x00007000 457 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_SHFT 0xc 458 459 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_BMSK 0x00000e00 460 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_SHFT 0x9 461 462 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_BMSK 0x000001c0 463 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_SHFT 0x6 464 465 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_BMSK 0x00000038 466 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_SHFT 0x3 467 468 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_BMSK 0x00000007 469 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_SHFT 0x0 470 471 //// Register TCL_R0_DSCP_TID1_MAP_2 //// 472 473 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x) (x+0x00000034) 474 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_PHYS(x) (x+0x00000034) 475 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK 0x3fffffff 476 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_SHFT 0 477 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x) \ 478 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK) 479 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_INM(x, mask) \ 480 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask) 481 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUT(x, val) \ 482 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), val) 483 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUTM(x, mask, val) \ 484 do {\ 485 HWIO_INTLOCK(); \ 486 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)); \ 487 HWIO_INTFREE();\ 488 } while (0) 489 490 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_BMSK 0x38000000 491 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_SHFT 0x1b 492 493 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_BMSK 0x07000000 494 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_SHFT 0x18 495 496 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_BMSK 0x00e00000 497 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_SHFT 0x15 498 499 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_BMSK 0x001c0000 500 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_SHFT 0x12 501 502 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_BMSK 0x00038000 503 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_SHFT 0xf 504 505 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_BMSK 0x00007000 506 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_SHFT 0xc 507 508 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_BMSK 0x00000e00 509 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_SHFT 0x9 510 511 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_BMSK 0x000001c0 512 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_SHFT 0x6 513 514 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_BMSK 0x00000038 515 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_SHFT 0x3 516 517 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_BMSK 0x00000007 518 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_SHFT 0x0 519 520 //// Register TCL_R0_DSCP_TID1_MAP_3 //// 521 522 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x) (x+0x00000038) 523 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_PHYS(x) (x+0x00000038) 524 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK 0x3fffffff 525 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_SHFT 0 526 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x) \ 527 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK) 528 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_INM(x, mask) \ 529 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask) 530 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUT(x, val) \ 531 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), val) 532 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUTM(x, mask, val) \ 533 do {\ 534 HWIO_INTLOCK(); \ 535 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)); \ 536 HWIO_INTFREE();\ 537 } while (0) 538 539 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_BMSK 0x38000000 540 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_SHFT 0x1b 541 542 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_BMSK 0x07000000 543 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_SHFT 0x18 544 545 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_BMSK 0x00e00000 546 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_SHFT 0x15 547 548 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_BMSK 0x001c0000 549 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_SHFT 0x12 550 551 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_BMSK 0x00038000 552 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_SHFT 0xf 553 554 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_BMSK 0x00007000 555 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_SHFT 0xc 556 557 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_BMSK 0x00000e00 558 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_SHFT 0x9 559 560 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_BMSK 0x000001c0 561 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_SHFT 0x6 562 563 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_BMSK 0x00000038 564 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_SHFT 0x3 565 566 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_BMSK 0x00000007 567 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_SHFT 0x0 568 569 //// Register TCL_R0_DSCP_TID1_MAP_4 //// 570 571 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x) (x+0x0000003c) 572 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_PHYS(x) (x+0x0000003c) 573 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK 0x3fffffff 574 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_SHFT 0 575 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x) \ 576 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK) 577 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_INM(x, mask) \ 578 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask) 579 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUT(x, val) \ 580 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), val) 581 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUTM(x, mask, val) \ 582 do {\ 583 HWIO_INTLOCK(); \ 584 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)); \ 585 HWIO_INTFREE();\ 586 } while (0) 587 588 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_BMSK 0x38000000 589 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_SHFT 0x1b 590 591 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_BMSK 0x07000000 592 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_SHFT 0x18 593 594 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_BMSK 0x00e00000 595 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_SHFT 0x15 596 597 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_BMSK 0x001c0000 598 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_SHFT 0x12 599 600 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_BMSK 0x00038000 601 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_SHFT 0xf 602 603 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_BMSK 0x00007000 604 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_SHFT 0xc 605 606 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_BMSK 0x00000e00 607 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_SHFT 0x9 608 609 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_BMSK 0x000001c0 610 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_SHFT 0x6 611 612 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_BMSK 0x00000038 613 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_SHFT 0x3 614 615 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_BMSK 0x00000007 616 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_SHFT 0x0 617 618 //// Register TCL_R0_DSCP_TID1_MAP_5 //// 619 620 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x) (x+0x00000040) 621 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_PHYS(x) (x+0x00000040) 622 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK 0x3fffffff 623 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_SHFT 0 624 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x) \ 625 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK) 626 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_INM(x, mask) \ 627 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask) 628 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUT(x, val) \ 629 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), val) 630 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUTM(x, mask, val) \ 631 do {\ 632 HWIO_INTLOCK(); \ 633 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)); \ 634 HWIO_INTFREE();\ 635 } while (0) 636 637 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_BMSK 0x38000000 638 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_SHFT 0x1b 639 640 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_BMSK 0x07000000 641 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_SHFT 0x18 642 643 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_BMSK 0x00e00000 644 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_SHFT 0x15 645 646 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_BMSK 0x001c0000 647 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_SHFT 0x12 648 649 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_BMSK 0x00038000 650 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_SHFT 0xf 651 652 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_BMSK 0x00007000 653 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_SHFT 0xc 654 655 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_BMSK 0x00000e00 656 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_SHFT 0x9 657 658 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_BMSK 0x000001c0 659 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_SHFT 0x6 660 661 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_BMSK 0x00000038 662 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_SHFT 0x3 663 664 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_BMSK 0x00000007 665 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_SHFT 0x0 666 667 //// Register TCL_R0_DSCP_TID1_MAP_6 //// 668 669 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x) (x+0x00000044) 670 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_PHYS(x) (x+0x00000044) 671 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK 0x00000fff 672 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_SHFT 0 673 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x) \ 674 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK) 675 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_INM(x, mask) \ 676 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask) 677 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUT(x, val) \ 678 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), val) 679 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUTM(x, mask, val) \ 680 do {\ 681 HWIO_INTLOCK(); \ 682 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)); \ 683 HWIO_INTFREE();\ 684 } while (0) 685 686 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_BMSK 0x00000e00 687 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_SHFT 0x9 688 689 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_BMSK 0x000001c0 690 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_SHFT 0x6 691 692 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_BMSK 0x00000038 693 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_SHFT 0x3 694 695 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_BMSK 0x00000007 696 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_SHFT 0x0 697 698 //// Register TCL_R0_DSCP_TID2_MAP_0 //// 699 700 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x) (x+0x00000048) 701 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_PHYS(x) (x+0x00000048) 702 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK 0x3fffffff 703 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_SHFT 0 704 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x) \ 705 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK) 706 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_INM(x, mask) \ 707 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask) 708 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUT(x, val) \ 709 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), val) 710 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUTM(x, mask, val) \ 711 do {\ 712 HWIO_INTLOCK(); \ 713 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)); \ 714 HWIO_INTFREE();\ 715 } while (0) 716 717 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_BMSK 0x38000000 718 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_SHFT 0x1b 719 720 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_BMSK 0x07000000 721 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_SHFT 0x18 722 723 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_BMSK 0x00e00000 724 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_SHFT 0x15 725 726 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_BMSK 0x001c0000 727 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_SHFT 0x12 728 729 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_BMSK 0x00038000 730 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_SHFT 0xf 731 732 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_BMSK 0x00007000 733 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_SHFT 0xc 734 735 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_BMSK 0x00000e00 736 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_SHFT 0x9 737 738 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_BMSK 0x000001c0 739 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_SHFT 0x6 740 741 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_BMSK 0x00000038 742 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_SHFT 0x3 743 744 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_BMSK 0x00000007 745 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_SHFT 0x0 746 747 //// Register TCL_R0_DSCP_TID2_MAP_1 //// 748 749 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x) (x+0x0000004c) 750 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_PHYS(x) (x+0x0000004c) 751 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK 0x3fffffff 752 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_SHFT 0 753 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x) \ 754 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK) 755 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_INM(x, mask) \ 756 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask) 757 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUT(x, val) \ 758 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), val) 759 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUTM(x, mask, val) \ 760 do {\ 761 HWIO_INTLOCK(); \ 762 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)); \ 763 HWIO_INTFREE();\ 764 } while (0) 765 766 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_BMSK 0x38000000 767 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_SHFT 0x1b 768 769 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_BMSK 0x07000000 770 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_SHFT 0x18 771 772 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_BMSK 0x00e00000 773 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_SHFT 0x15 774 775 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_BMSK 0x001c0000 776 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_SHFT 0x12 777 778 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_BMSK 0x00038000 779 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_SHFT 0xf 780 781 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_BMSK 0x00007000 782 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_SHFT 0xc 783 784 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_BMSK 0x00000e00 785 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_SHFT 0x9 786 787 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_BMSK 0x000001c0 788 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_SHFT 0x6 789 790 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_BMSK 0x00000038 791 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_SHFT 0x3 792 793 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_BMSK 0x00000007 794 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_SHFT 0x0 795 796 //// Register TCL_R0_DSCP_TID2_MAP_2 //// 797 798 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x) (x+0x00000050) 799 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_PHYS(x) (x+0x00000050) 800 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK 0x3fffffff 801 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_SHFT 0 802 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x) \ 803 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK) 804 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_INM(x, mask) \ 805 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask) 806 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUT(x, val) \ 807 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), val) 808 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUTM(x, mask, val) \ 809 do {\ 810 HWIO_INTLOCK(); \ 811 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)); \ 812 HWIO_INTFREE();\ 813 } while (0) 814 815 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_BMSK 0x38000000 816 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_SHFT 0x1b 817 818 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_BMSK 0x07000000 819 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_SHFT 0x18 820 821 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_BMSK 0x00e00000 822 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_SHFT 0x15 823 824 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_BMSK 0x001c0000 825 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_SHFT 0x12 826 827 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_BMSK 0x00038000 828 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_SHFT 0xf 829 830 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_BMSK 0x00007000 831 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_SHFT 0xc 832 833 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_BMSK 0x00000e00 834 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_SHFT 0x9 835 836 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_BMSK 0x000001c0 837 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_SHFT 0x6 838 839 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_BMSK 0x00000038 840 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_SHFT 0x3 841 842 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_BMSK 0x00000007 843 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_SHFT 0x0 844 845 //// Register TCL_R0_DSCP_TID2_MAP_3 //// 846 847 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x) (x+0x00000054) 848 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_PHYS(x) (x+0x00000054) 849 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK 0x3fffffff 850 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_SHFT 0 851 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x) \ 852 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK) 853 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_INM(x, mask) \ 854 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask) 855 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUT(x, val) \ 856 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), val) 857 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUTM(x, mask, val) \ 858 do {\ 859 HWIO_INTLOCK(); \ 860 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)); \ 861 HWIO_INTFREE();\ 862 } while (0) 863 864 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_BMSK 0x38000000 865 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_SHFT 0x1b 866 867 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_BMSK 0x07000000 868 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_SHFT 0x18 869 870 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_BMSK 0x00e00000 871 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_SHFT 0x15 872 873 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_BMSK 0x001c0000 874 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_SHFT 0x12 875 876 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_BMSK 0x00038000 877 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_SHFT 0xf 878 879 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_BMSK 0x00007000 880 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_SHFT 0xc 881 882 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_BMSK 0x00000e00 883 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_SHFT 0x9 884 885 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_BMSK 0x000001c0 886 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_SHFT 0x6 887 888 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_BMSK 0x00000038 889 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_SHFT 0x3 890 891 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_BMSK 0x00000007 892 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_SHFT 0x0 893 894 //// Register TCL_R0_DSCP_TID2_MAP_4 //// 895 896 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x) (x+0x00000058) 897 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_PHYS(x) (x+0x00000058) 898 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK 0x3fffffff 899 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_SHFT 0 900 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x) \ 901 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK) 902 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_INM(x, mask) \ 903 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask) 904 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUT(x, val) \ 905 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), val) 906 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUTM(x, mask, val) \ 907 do {\ 908 HWIO_INTLOCK(); \ 909 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)); \ 910 HWIO_INTFREE();\ 911 } while (0) 912 913 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_BMSK 0x38000000 914 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_SHFT 0x1b 915 916 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_BMSK 0x07000000 917 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_SHFT 0x18 918 919 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_BMSK 0x00e00000 920 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_SHFT 0x15 921 922 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_BMSK 0x001c0000 923 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_SHFT 0x12 924 925 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_BMSK 0x00038000 926 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_SHFT 0xf 927 928 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_BMSK 0x00007000 929 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_SHFT 0xc 930 931 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_BMSK 0x00000e00 932 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_SHFT 0x9 933 934 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_BMSK 0x000001c0 935 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_SHFT 0x6 936 937 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_BMSK 0x00000038 938 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_SHFT 0x3 939 940 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_BMSK 0x00000007 941 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_SHFT 0x0 942 943 //// Register TCL_R0_DSCP_TID2_MAP_5 //// 944 945 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x) (x+0x0000005c) 946 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_PHYS(x) (x+0x0000005c) 947 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK 0x3fffffff 948 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_SHFT 0 949 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x) \ 950 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK) 951 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_INM(x, mask) \ 952 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask) 953 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUT(x, val) \ 954 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), val) 955 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUTM(x, mask, val) \ 956 do {\ 957 HWIO_INTLOCK(); \ 958 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)); \ 959 HWIO_INTFREE();\ 960 } while (0) 961 962 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_BMSK 0x38000000 963 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_SHFT 0x1b 964 965 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_BMSK 0x07000000 966 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_SHFT 0x18 967 968 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_BMSK 0x00e00000 969 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_SHFT 0x15 970 971 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_BMSK 0x001c0000 972 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_SHFT 0x12 973 974 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_BMSK 0x00038000 975 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_SHFT 0xf 976 977 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_BMSK 0x00007000 978 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_SHFT 0xc 979 980 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_BMSK 0x00000e00 981 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_SHFT 0x9 982 983 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_BMSK 0x000001c0 984 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_SHFT 0x6 985 986 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_BMSK 0x00000038 987 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_SHFT 0x3 988 989 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_BMSK 0x00000007 990 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_SHFT 0x0 991 992 //// Register TCL_R0_DSCP_TID2_MAP_6 //// 993 994 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x) (x+0x00000060) 995 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_PHYS(x) (x+0x00000060) 996 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK 0x00000fff 997 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_SHFT 0 998 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x) \ 999 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK) 1000 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_INM(x, mask) \ 1001 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask) 1002 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUT(x, val) \ 1003 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), val) 1004 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUTM(x, mask, val) \ 1005 do {\ 1006 HWIO_INTLOCK(); \ 1007 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)); \ 1008 HWIO_INTFREE();\ 1009 } while (0) 1010 1011 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_BMSK 0x00000e00 1012 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_SHFT 0x9 1013 1014 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_BMSK 0x000001c0 1015 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_SHFT 0x6 1016 1017 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_BMSK 0x00000038 1018 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_SHFT 0x3 1019 1020 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_BMSK 0x00000007 1021 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_SHFT 0x0 1022 1023 //// Register TCL_R0_PCP_TID_MAP //// 1024 1025 #define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x00000064) 1026 #define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x00000064) 1027 #define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff 1028 #define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 1029 #define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ 1030 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) 1031 #define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ 1032 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 1033 #define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ 1034 out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) 1035 #define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ 1036 do {\ 1037 HWIO_INTLOCK(); \ 1038 out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ 1039 HWIO_INTFREE();\ 1040 } while (0) 1041 1042 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 1043 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 1044 1045 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 1046 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 1047 1048 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 1049 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf 1050 1051 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 1052 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc 1053 1054 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 1055 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 1056 1057 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 1058 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 1059 1060 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 1061 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 1062 1063 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 1064 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 1065 1066 //// Register TCL_R0_ASE_HASH_KEY_31_0 //// 1067 1068 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x00000068) 1069 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x00000068) 1070 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff 1071 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 1072 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ 1073 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) 1074 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ 1075 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 1076 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ 1077 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) 1078 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ 1079 do {\ 1080 HWIO_INTLOCK(); \ 1081 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ 1082 HWIO_INTFREE();\ 1083 } while (0) 1084 1085 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 1086 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 1087 1088 //// Register TCL_R0_ASE_HASH_KEY_63_32 //// 1089 1090 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x0000006c) 1091 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x0000006c) 1092 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff 1093 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 1094 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ 1095 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) 1096 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ 1097 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 1098 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ 1099 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) 1100 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ 1101 do {\ 1102 HWIO_INTLOCK(); \ 1103 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ 1104 HWIO_INTFREE();\ 1105 } while (0) 1106 1107 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 1108 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 1109 1110 //// Register TCL_R0_ASE_HASH_KEY_64 //// 1111 1112 #define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x00000070) 1113 #define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x00000070) 1114 #define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 1115 #define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 1116 #define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ 1117 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) 1118 #define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ 1119 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 1120 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ 1121 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) 1122 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ 1123 do {\ 1124 HWIO_INTLOCK(); \ 1125 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ 1126 HWIO_INTFREE();\ 1127 } while (0) 1128 1129 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 1130 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 1131 1132 //// Register TCL_R0_FSE_HASH_KEY_31_0 //// 1133 1134 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x) (x+0x00000074) 1135 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_PHYS(x) (x+0x00000074) 1136 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK 0xffffffff 1137 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_SHFT 0 1138 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x) \ 1139 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK) 1140 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask) \ 1141 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) 1142 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val) \ 1143 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val) 1144 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val) \ 1145 do {\ 1146 HWIO_INTLOCK(); \ 1147 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \ 1148 HWIO_INTFREE();\ 1149 } while (0) 1150 1151 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 1152 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT 0x0 1153 1154 //// Register TCL_R0_FSE_HASH_KEY_63_32 //// 1155 1156 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x) (x+0x00000078) 1157 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_PHYS(x) (x+0x00000078) 1158 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK 0xffffffff 1159 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_SHFT 0 1160 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x) \ 1161 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK) 1162 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask) \ 1163 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) 1164 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val) \ 1165 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val) 1166 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val) \ 1167 do {\ 1168 HWIO_INTLOCK(); \ 1169 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \ 1170 HWIO_INTFREE();\ 1171 } while (0) 1172 1173 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 1174 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT 0x0 1175 1176 //// Register TCL_R0_FSE_HASH_KEY_95_64 //// 1177 1178 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x) (x+0x0000007c) 1179 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_PHYS(x) (x+0x0000007c) 1180 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK 0xffffffff 1181 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_SHFT 0 1182 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x) \ 1183 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK) 1184 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask) \ 1185 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) 1186 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val) \ 1187 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val) 1188 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val) \ 1189 do {\ 1190 HWIO_INTLOCK(); \ 1191 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \ 1192 HWIO_INTFREE();\ 1193 } while (0) 1194 1195 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK 0xffffffff 1196 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT 0x0 1197 1198 //// Register TCL_R0_FSE_HASH_KEY_127_96 //// 1199 1200 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x) (x+0x00000080) 1201 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_PHYS(x) (x+0x00000080) 1202 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK 0xffffffff 1203 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_SHFT 0 1204 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x) \ 1205 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK) 1206 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask) \ 1207 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) 1208 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val) \ 1209 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val) 1210 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val) \ 1211 do {\ 1212 HWIO_INTLOCK(); \ 1213 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \ 1214 HWIO_INTFREE();\ 1215 } while (0) 1216 1217 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK 0xffffffff 1218 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT 0x0 1219 1220 //// Register TCL_R0_FSE_HASH_KEY_159_128 //// 1221 1222 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x) (x+0x00000084) 1223 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_PHYS(x) (x+0x00000084) 1224 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK 0xffffffff 1225 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_SHFT 0 1226 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x) \ 1227 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK) 1228 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask) \ 1229 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) 1230 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val) \ 1231 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val) 1232 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val) \ 1233 do {\ 1234 HWIO_INTLOCK(); \ 1235 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \ 1236 HWIO_INTFREE();\ 1237 } while (0) 1238 1239 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK 0xffffffff 1240 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT 0x0 1241 1242 //// Register TCL_R0_FSE_HASH_KEY_191_160 //// 1243 1244 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x) (x+0x00000088) 1245 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_PHYS(x) (x+0x00000088) 1246 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK 0xffffffff 1247 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_SHFT 0 1248 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x) \ 1249 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK) 1250 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask) \ 1251 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) 1252 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val) \ 1253 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val) 1254 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val) \ 1255 do {\ 1256 HWIO_INTLOCK(); \ 1257 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \ 1258 HWIO_INTFREE();\ 1259 } while (0) 1260 1261 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK 0xffffffff 1262 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT 0x0 1263 1264 //// Register TCL_R0_FSE_HASH_KEY_223_192 //// 1265 1266 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x) (x+0x0000008c) 1267 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_PHYS(x) (x+0x0000008c) 1268 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK 0xffffffff 1269 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_SHFT 0 1270 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x) \ 1271 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK) 1272 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask) \ 1273 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) 1274 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val) \ 1275 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val) 1276 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val) \ 1277 do {\ 1278 HWIO_INTLOCK(); \ 1279 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \ 1280 HWIO_INTFREE();\ 1281 } while (0) 1282 1283 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK 0xffffffff 1284 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT 0x0 1285 1286 //// Register TCL_R0_FSE_HASH_KEY_255_224 //// 1287 1288 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x) (x+0x00000090) 1289 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_PHYS(x) (x+0x00000090) 1290 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK 0xffffffff 1291 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_SHFT 0 1292 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x) \ 1293 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK) 1294 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask) \ 1295 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) 1296 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val) \ 1297 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val) 1298 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val) \ 1299 do {\ 1300 HWIO_INTLOCK(); \ 1301 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \ 1302 HWIO_INTFREE();\ 1303 } while (0) 1304 1305 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK 0xffffffff 1306 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT 0x0 1307 1308 //// Register TCL_R0_FSE_HASH_KEY_287_256 //// 1309 1310 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x) (x+0x00000094) 1311 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_PHYS(x) (x+0x00000094) 1312 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK 0xffffffff 1313 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_SHFT 0 1314 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x) \ 1315 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK) 1316 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask) \ 1317 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) 1318 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val) \ 1319 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val) 1320 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val) \ 1321 do {\ 1322 HWIO_INTLOCK(); \ 1323 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \ 1324 HWIO_INTFREE();\ 1325 } while (0) 1326 1327 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK 0xffffffff 1328 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT 0x0 1329 1330 //// Register TCL_R0_FSE_HASH_KEY_314_288 //// 1331 1332 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x) (x+0x00000098) 1333 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_PHYS(x) (x+0x00000098) 1334 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK 0x07ffffff 1335 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_SHFT 0 1336 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x) \ 1337 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK) 1338 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask) \ 1339 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) 1340 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val) \ 1341 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val) 1342 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val) \ 1343 do {\ 1344 HWIO_INTLOCK(); \ 1345 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \ 1346 HWIO_INTFREE();\ 1347 } while (0) 1348 1349 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK 0x07ffffff 1350 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT 0x0 1351 1352 //// Register TCL_R0_CONFIG_SEARCH_QUEUE //// 1353 1354 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x0000009c) 1355 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x0000009c) 1356 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00003dfc 1357 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 1358 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ 1359 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) 1360 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ 1361 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 1362 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ 1363 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) 1364 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ 1365 do {\ 1366 HWIO_INTLOCK(); \ 1367 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ 1368 HWIO_INTFREE();\ 1369 } while (0) 1370 1371 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 1372 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd 1373 1374 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 1375 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc 1376 1377 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 1378 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb 1379 1380 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 1381 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa 1382 1383 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 1384 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 1385 1386 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 1387 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 1388 1389 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c 1390 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 1391 1392 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// 1393 1394 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000000a0) 1395 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000000a0) 1396 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 1397 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 1398 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ 1399 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) 1400 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 1401 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 1402 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 1403 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 1404 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 1405 do {\ 1406 HWIO_INTLOCK(); \ 1407 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 1408 HWIO_INTFREE();\ 1409 } while (0) 1410 1411 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 1412 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 1413 1414 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// 1415 1416 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000000a4) 1417 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000000a4) 1418 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 1419 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 1420 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 1421 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) 1422 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 1423 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 1424 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 1425 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 1426 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 1427 do {\ 1428 HWIO_INTLOCK(); \ 1429 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 1430 HWIO_INTFREE();\ 1431 } while (0) 1432 1433 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 1434 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 1435 1436 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// 1437 1438 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000000a8) 1439 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000000a8) 1440 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 1441 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 1442 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ 1443 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) 1444 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 1445 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 1446 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 1447 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 1448 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 1449 do {\ 1450 HWIO_INTLOCK(); \ 1451 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 1452 HWIO_INTFREE();\ 1453 } while (0) 1454 1455 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 1456 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 1457 1458 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// 1459 1460 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000000ac) 1461 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000000ac) 1462 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 1463 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 1464 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 1465 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) 1466 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 1467 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 1468 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 1469 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 1470 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 1471 do {\ 1472 HWIO_INTLOCK(); \ 1473 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 1474 HWIO_INTFREE();\ 1475 } while (0) 1476 1477 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 1478 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 1479 1480 //// Register TCL_R0_CONFIG_SEARCH_METADATA //// 1481 1482 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000000b0) 1483 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000000b0) 1484 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff 1485 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 1486 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ 1487 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) 1488 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ 1489 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 1490 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ 1491 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) 1492 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ 1493 do {\ 1494 HWIO_INTLOCK(); \ 1495 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ 1496 HWIO_INTFREE();\ 1497 } while (0) 1498 1499 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 1500 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 1501 1502 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff 1503 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 1504 1505 //// Register TCL_R0_TID_MAP_PRTY //// 1506 1507 #define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000000b4) 1508 #define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000000b4) 1509 #define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef 1510 #define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 1511 #define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ 1512 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) 1513 #define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ 1514 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 1515 #define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ 1516 out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) 1517 #define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ 1518 do {\ 1519 HWIO_INTLOCK(); \ 1520 out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ 1521 HWIO_INTFREE();\ 1522 } while (0) 1523 1524 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 1525 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 1526 1527 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f 1528 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 1529 1530 //// Register TCL_R0_INVALID_APB_ACC_ADDR //// 1531 1532 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000000b8) 1533 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000000b8) 1534 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff 1535 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 1536 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ 1537 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) 1538 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ 1539 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 1540 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ 1541 out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) 1542 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ 1543 do {\ 1544 HWIO_INTLOCK(); \ 1545 out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ 1546 HWIO_INTFREE();\ 1547 } while (0) 1548 1549 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff 1550 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 1551 1552 //// Register TCL_R0_WATCHDOG //// 1553 1554 #define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000000bc) 1555 #define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000000bc) 1556 #define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff 1557 #define HWIO_TCL_R0_WATCHDOG_SHFT 0 1558 #define HWIO_TCL_R0_WATCHDOG_IN(x) \ 1559 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) 1560 #define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ 1561 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 1562 #define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ 1563 out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) 1564 #define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ 1565 do {\ 1566 HWIO_INTLOCK(); \ 1567 out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ 1568 HWIO_INTFREE();\ 1569 } while (0) 1570 1571 #define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 1572 #define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 1573 1574 #define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff 1575 #define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 1576 1577 //// Register TCL_R0_CLKGATE_DISABLE //// 1578 1579 #define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x000000c0) 1580 #define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x000000c0) 1581 #define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff 1582 #define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 1583 #define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ 1584 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) 1585 #define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ 1586 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 1587 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ 1588 out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) 1589 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ 1590 do {\ 1591 HWIO_INTLOCK(); \ 1592 out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ 1593 HWIO_INTFREE();\ 1594 } while (0) 1595 1596 #define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_BMSK 0xffffffff 1597 #define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_SHFT 0x0 1598 1599 //// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// 1600 1601 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000000c4) 1602 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000000c4) 1603 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 1604 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 1605 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ 1606 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) 1607 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ 1608 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 1609 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ 1610 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) 1611 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 1612 do {\ 1613 HWIO_INTLOCK(); \ 1614 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ 1615 HWIO_INTFREE();\ 1616 } while (0) 1617 1618 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1619 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1620 1621 //// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// 1622 1623 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000000c8) 1624 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000000c8) 1625 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 1626 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 1627 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ 1628 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) 1629 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ 1630 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 1631 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ 1632 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) 1633 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 1634 do {\ 1635 HWIO_INTLOCK(); \ 1636 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ 1637 HWIO_INTFREE();\ 1638 } while (0) 1639 1640 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1641 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1642 1643 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1644 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1645 1646 //// Register TCL_R0_SW2TCL1_RING_ID //// 1647 1648 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x000000cc) 1649 #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x000000cc) 1650 #define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff 1651 #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 1652 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ 1653 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) 1654 #define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ 1655 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 1656 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ 1657 out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) 1658 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ 1659 do {\ 1660 HWIO_INTLOCK(); \ 1661 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ 1662 HWIO_INTFREE();\ 1663 } while (0) 1664 1665 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1666 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 1667 1668 //// Register TCL_R0_SW2TCL1_RING_STATUS //// 1669 1670 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x000000d0) 1671 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x000000d0) 1672 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff 1673 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 1674 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ 1675 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) 1676 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ 1677 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 1678 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ 1679 out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) 1680 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 1681 do {\ 1682 HWIO_INTLOCK(); \ 1683 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ 1684 HWIO_INTFREE();\ 1685 } while (0) 1686 1687 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1688 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1689 1690 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1691 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1692 1693 //// Register TCL_R0_SW2TCL1_RING_MISC //// 1694 1695 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000000d4) 1696 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000000d4) 1697 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x0000003f 1698 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 1699 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ 1700 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) 1701 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ 1702 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 1703 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ 1704 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) 1705 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ 1706 do {\ 1707 HWIO_INTLOCK(); \ 1708 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ 1709 HWIO_INTFREE();\ 1710 } while (0) 1711 1712 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1713 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1714 1715 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1716 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1717 1718 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1719 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1720 1721 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1722 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 1723 1724 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1725 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1726 1727 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1728 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1729 1730 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// 1731 1732 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000e0) 1733 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000e0) 1734 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1735 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 1736 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 1737 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) 1738 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 1739 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 1740 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 1741 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 1742 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1743 do {\ 1744 HWIO_INTLOCK(); \ 1745 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 1746 HWIO_INTFREE();\ 1747 } while (0) 1748 1749 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1750 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1751 1752 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// 1753 1754 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000e4) 1755 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000e4) 1756 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1757 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 1758 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 1759 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) 1760 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 1761 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 1762 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 1763 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 1764 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1765 do {\ 1766 HWIO_INTLOCK(); \ 1767 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 1768 HWIO_INTFREE();\ 1769 } while (0) 1770 1771 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1772 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1773 1774 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 1775 1776 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000f4) 1777 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000f4) 1778 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1779 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1780 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1781 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1782 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1783 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1784 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1785 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1786 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1787 do {\ 1788 HWIO_INTLOCK(); \ 1789 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1790 HWIO_INTFREE();\ 1791 } while (0) 1792 1793 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1794 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1795 1796 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1797 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1798 1799 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1800 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1801 1802 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 1803 1804 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000f8) 1805 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000f8) 1806 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1807 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1808 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1809 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1810 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1811 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1812 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1813 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1814 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1815 do {\ 1816 HWIO_INTLOCK(); \ 1817 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1818 HWIO_INTFREE();\ 1819 } while (0) 1820 1821 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1822 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1823 1824 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// 1825 1826 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000fc) 1827 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000fc) 1828 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1829 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 1830 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 1831 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 1832 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1833 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1834 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1835 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1836 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1837 do {\ 1838 HWIO_INTLOCK(); \ 1839 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1840 HWIO_INTFREE();\ 1841 } while (0) 1842 1843 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1844 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1845 1846 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1847 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1848 1849 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1850 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1851 1852 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 1853 1854 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000100) 1855 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000100) 1856 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1857 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1858 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1859 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1860 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1861 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1862 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1863 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1864 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1865 do {\ 1866 HWIO_INTLOCK(); \ 1867 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1868 HWIO_INTFREE();\ 1869 } while (0) 1870 1871 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1872 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1873 1874 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 1875 1876 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000104) 1877 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000104) 1878 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1879 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1880 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1881 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1882 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1883 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1884 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1885 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1886 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1887 do {\ 1888 HWIO_INTLOCK(); \ 1889 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1890 HWIO_INTFREE();\ 1891 } while (0) 1892 1893 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1894 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1895 1896 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 1897 1898 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000108) 1899 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000108) 1900 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1901 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1902 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1903 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1904 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1905 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1906 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1907 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1908 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1909 do {\ 1910 HWIO_INTLOCK(); \ 1911 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1912 HWIO_INTFREE();\ 1913 } while (0) 1914 1915 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1916 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1917 1918 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1919 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1920 1921 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// 1922 1923 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000010c) 1924 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000010c) 1925 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1926 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 1927 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 1928 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) 1929 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1930 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1931 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1932 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 1933 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1934 do {\ 1935 HWIO_INTLOCK(); \ 1936 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 1937 HWIO_INTFREE();\ 1938 } while (0) 1939 1940 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1941 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1942 1943 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// 1944 1945 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000110) 1946 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000110) 1947 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1948 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 1949 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 1950 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) 1951 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1952 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1953 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1954 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 1955 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1956 do {\ 1957 HWIO_INTLOCK(); \ 1958 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 1959 HWIO_INTFREE();\ 1960 } while (0) 1961 1962 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1963 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1964 1965 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1966 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1967 1968 //// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// 1969 1970 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000114) 1971 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000114) 1972 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 1973 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 1974 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ 1975 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) 1976 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 1977 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 1978 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 1979 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) 1980 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1981 do {\ 1982 HWIO_INTLOCK(); \ 1983 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ 1984 HWIO_INTFREE();\ 1985 } while (0) 1986 1987 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1988 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 1989 1990 //// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// 1991 1992 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000118) 1993 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000118) 1994 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1995 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 1996 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 1997 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 1998 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1999 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2000 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2001 out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2002 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2003 do {\ 2004 HWIO_INTLOCK(); \ 2005 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 2006 HWIO_INTFREE();\ 2007 } while (0) 2008 2009 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2010 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2011 2012 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// 2013 2014 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x0000011c) 2015 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x0000011c) 2016 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff 2017 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 2018 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ 2019 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) 2020 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ 2021 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 2022 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ 2023 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) 2024 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ 2025 do {\ 2026 HWIO_INTLOCK(); \ 2027 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ 2028 HWIO_INTFREE();\ 2029 } while (0) 2030 2031 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2032 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2033 2034 //// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// 2035 2036 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x00000120) 2037 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x00000120) 2038 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x00ffffff 2039 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 2040 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ 2041 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) 2042 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ 2043 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 2044 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ 2045 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) 2046 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ 2047 do {\ 2048 HWIO_INTLOCK(); \ 2049 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ 2050 HWIO_INTFREE();\ 2051 } while (0) 2052 2053 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2054 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2055 2056 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2057 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2058 2059 //// Register TCL_R0_SW2TCL2_RING_ID //// 2060 2061 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x00000124) 2062 #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x00000124) 2063 #define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff 2064 #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 2065 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ 2066 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) 2067 #define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ 2068 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 2069 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ 2070 out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) 2071 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ 2072 do {\ 2073 HWIO_INTLOCK(); \ 2074 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ 2075 HWIO_INTFREE();\ 2076 } while (0) 2077 2078 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2079 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 2080 2081 //// Register TCL_R0_SW2TCL2_RING_STATUS //// 2082 2083 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x00000128) 2084 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x00000128) 2085 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff 2086 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 2087 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ 2088 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) 2089 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ 2090 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 2091 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ 2092 out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) 2093 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ 2094 do {\ 2095 HWIO_INTLOCK(); \ 2096 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ 2097 HWIO_INTFREE();\ 2098 } while (0) 2099 2100 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2101 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2102 2103 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2104 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2105 2106 //// Register TCL_R0_SW2TCL2_RING_MISC //// 2107 2108 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x0000012c) 2109 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x0000012c) 2110 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x0000003f 2111 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 2112 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ 2113 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) 2114 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ 2115 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 2116 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ 2117 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) 2118 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ 2119 do {\ 2120 HWIO_INTLOCK(); \ 2121 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ 2122 HWIO_INTFREE();\ 2123 } while (0) 2124 2125 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2126 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2127 2128 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2129 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2130 2131 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2132 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2133 2134 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2135 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 2136 2137 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2138 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2139 2140 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2141 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2142 2143 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// 2144 2145 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000138) 2146 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000138) 2147 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff 2148 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 2149 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ 2150 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) 2151 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ 2152 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 2153 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ 2154 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) 2155 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2156 do {\ 2157 HWIO_INTLOCK(); \ 2158 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ 2159 HWIO_INTFREE();\ 2160 } while (0) 2161 2162 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2163 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2164 2165 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// 2166 2167 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000013c) 2168 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000013c) 2169 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff 2170 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 2171 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ 2172 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) 2173 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ 2174 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 2175 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ 2176 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) 2177 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2178 do {\ 2179 HWIO_INTLOCK(); \ 2180 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ 2181 HWIO_INTFREE();\ 2182 } while (0) 2183 2184 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2185 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2186 2187 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// 2188 2189 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000014c) 2190 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000014c) 2191 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2192 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2193 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2194 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2195 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2196 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2197 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2198 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2199 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2200 do {\ 2201 HWIO_INTLOCK(); \ 2202 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2203 HWIO_INTFREE();\ 2204 } while (0) 2205 2206 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2207 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2208 2209 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2210 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2211 2212 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2213 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2214 2215 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// 2216 2217 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000150) 2218 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000150) 2219 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2220 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2221 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2222 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2223 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2224 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2225 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2226 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2227 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2228 do {\ 2229 HWIO_INTLOCK(); \ 2230 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2231 HWIO_INTFREE();\ 2232 } while (0) 2233 2234 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2235 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2236 2237 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// 2238 2239 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000154) 2240 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000154) 2241 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2242 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 2243 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ 2244 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) 2245 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2246 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2247 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2248 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2249 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2250 do {\ 2251 HWIO_INTLOCK(); \ 2252 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ 2253 HWIO_INTFREE();\ 2254 } while (0) 2255 2256 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2257 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2258 2259 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2260 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2261 2262 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2263 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2264 2265 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// 2266 2267 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000158) 2268 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000158) 2269 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2270 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2271 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2272 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2273 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2274 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2275 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2276 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2277 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2278 do {\ 2279 HWIO_INTLOCK(); \ 2280 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2281 HWIO_INTFREE();\ 2282 } while (0) 2283 2284 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2285 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2286 2287 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// 2288 2289 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000015c) 2290 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000015c) 2291 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2292 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2293 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2294 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2295 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2296 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2297 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2298 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2299 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2300 do {\ 2301 HWIO_INTLOCK(); \ 2302 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2303 HWIO_INTFREE();\ 2304 } while (0) 2305 2306 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2307 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2308 2309 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// 2310 2311 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000160) 2312 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000160) 2313 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2314 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2315 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2316 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2317 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2318 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2319 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2320 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2321 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2322 do {\ 2323 HWIO_INTLOCK(); \ 2324 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2325 HWIO_INTFREE();\ 2326 } while (0) 2327 2328 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2329 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2330 2331 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2332 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2333 2334 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// 2335 2336 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000164) 2337 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000164) 2338 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2339 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 2340 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ 2341 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) 2342 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ 2343 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 2344 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ 2345 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) 2346 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2347 do {\ 2348 HWIO_INTLOCK(); \ 2349 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ 2350 HWIO_INTFREE();\ 2351 } while (0) 2352 2353 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2354 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2355 2356 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// 2357 2358 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000168) 2359 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000168) 2360 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2361 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 2362 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ 2363 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) 2364 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ 2365 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 2366 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ 2367 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) 2368 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2369 do {\ 2370 HWIO_INTLOCK(); \ 2371 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ 2372 HWIO_INTFREE();\ 2373 } while (0) 2374 2375 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2376 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2377 2378 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2379 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2380 2381 //// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// 2382 2383 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x0000016c) 2384 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x0000016c) 2385 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff 2386 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 2387 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ 2388 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) 2389 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ 2390 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 2391 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ 2392 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) 2393 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ 2394 do {\ 2395 HWIO_INTLOCK(); \ 2396 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ 2397 HWIO_INTFREE();\ 2398 } while (0) 2399 2400 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2401 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 2402 2403 //// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// 2404 2405 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000170) 2406 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000170) 2407 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2408 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 2409 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ 2410 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) 2411 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2412 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2413 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2414 out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2415 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2416 do {\ 2417 HWIO_INTLOCK(); \ 2418 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ 2419 HWIO_INTFREE();\ 2420 } while (0) 2421 2422 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2423 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2424 2425 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// 2426 2427 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000174) 2428 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000174) 2429 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff 2430 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 2431 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ 2432 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) 2433 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ 2434 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 2435 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ 2436 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) 2437 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ 2438 do {\ 2439 HWIO_INTLOCK(); \ 2440 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ 2441 HWIO_INTFREE();\ 2442 } while (0) 2443 2444 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2445 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2446 2447 //// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// 2448 2449 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000178) 2450 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000178) 2451 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x00ffffff 2452 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 2453 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ 2454 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) 2455 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ 2456 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 2457 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ 2458 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) 2459 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ 2460 do {\ 2461 HWIO_INTLOCK(); \ 2462 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ 2463 HWIO_INTFREE();\ 2464 } while (0) 2465 2466 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2467 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2468 2469 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2470 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2471 2472 //// Register TCL_R0_SW2TCL3_RING_ID //// 2473 2474 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000017c) 2475 #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000017c) 2476 #define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff 2477 #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 2478 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ 2479 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) 2480 #define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ 2481 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 2482 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ 2483 out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) 2484 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ 2485 do {\ 2486 HWIO_INTLOCK(); \ 2487 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ 2488 HWIO_INTFREE();\ 2489 } while (0) 2490 2491 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2492 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 2493 2494 //// Register TCL_R0_SW2TCL3_RING_STATUS //// 2495 2496 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x00000180) 2497 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x00000180) 2498 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff 2499 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 2500 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ 2501 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) 2502 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ 2503 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 2504 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ 2505 out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) 2506 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ 2507 do {\ 2508 HWIO_INTLOCK(); \ 2509 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ 2510 HWIO_INTFREE();\ 2511 } while (0) 2512 2513 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2514 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2515 2516 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2517 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2518 2519 //// Register TCL_R0_SW2TCL3_RING_MISC //// 2520 2521 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000184) 2522 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000184) 2523 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x0000003f 2524 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 2525 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ 2526 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) 2527 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ 2528 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 2529 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ 2530 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) 2531 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ 2532 do {\ 2533 HWIO_INTLOCK(); \ 2534 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ 2535 HWIO_INTFREE();\ 2536 } while (0) 2537 2538 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2539 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2540 2541 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2542 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2543 2544 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2545 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2546 2547 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2548 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 2549 2550 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2551 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2552 2553 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2554 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2555 2556 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// 2557 2558 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000190) 2559 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000190) 2560 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff 2561 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 2562 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ 2563 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) 2564 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ 2565 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 2566 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ 2567 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) 2568 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2569 do {\ 2570 HWIO_INTLOCK(); \ 2571 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ 2572 HWIO_INTFREE();\ 2573 } while (0) 2574 2575 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2576 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2577 2578 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// 2579 2580 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000194) 2581 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000194) 2582 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff 2583 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 2584 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ 2585 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) 2586 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ 2587 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 2588 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ 2589 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) 2590 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2591 do {\ 2592 HWIO_INTLOCK(); \ 2593 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ 2594 HWIO_INTFREE();\ 2595 } while (0) 2596 2597 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2598 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2599 2600 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// 2601 2602 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001a4) 2603 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001a4) 2604 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2605 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2606 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2607 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2608 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2609 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2610 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2611 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2612 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2613 do {\ 2614 HWIO_INTLOCK(); \ 2615 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2616 HWIO_INTFREE();\ 2617 } while (0) 2618 2619 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2620 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2621 2622 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2623 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2624 2625 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2626 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2627 2628 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// 2629 2630 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001a8) 2631 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001a8) 2632 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2633 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2634 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2635 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2636 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2637 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2638 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2639 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2640 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2641 do {\ 2642 HWIO_INTLOCK(); \ 2643 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2644 HWIO_INTFREE();\ 2645 } while (0) 2646 2647 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2648 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2649 2650 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// 2651 2652 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001ac) 2653 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001ac) 2654 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2655 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 2656 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ 2657 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) 2658 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2659 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2660 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2661 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2662 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2663 do {\ 2664 HWIO_INTLOCK(); \ 2665 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ 2666 HWIO_INTFREE();\ 2667 } while (0) 2668 2669 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2670 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2671 2672 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2673 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2674 2675 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2676 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2677 2678 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// 2679 2680 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b0) 2681 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b0) 2682 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2683 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2684 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2685 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2686 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2687 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2688 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2689 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2690 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2691 do {\ 2692 HWIO_INTLOCK(); \ 2693 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2694 HWIO_INTFREE();\ 2695 } while (0) 2696 2697 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2698 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2699 2700 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// 2701 2702 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001b4) 2703 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001b4) 2704 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2705 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2706 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2707 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2708 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2709 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2710 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2711 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2712 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2713 do {\ 2714 HWIO_INTLOCK(); \ 2715 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2716 HWIO_INTFREE();\ 2717 } while (0) 2718 2719 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2720 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2721 2722 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// 2723 2724 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001b8) 2725 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001b8) 2726 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2727 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2728 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2729 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2730 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2731 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2732 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2733 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2734 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2735 do {\ 2736 HWIO_INTLOCK(); \ 2737 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2738 HWIO_INTFREE();\ 2739 } while (0) 2740 2741 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2742 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2743 2744 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2745 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2746 2747 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// 2748 2749 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001bc) 2750 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001bc) 2751 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2752 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 2753 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ 2754 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) 2755 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ 2756 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 2757 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ 2758 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) 2759 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2760 do {\ 2761 HWIO_INTLOCK(); \ 2762 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ 2763 HWIO_INTFREE();\ 2764 } while (0) 2765 2766 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2767 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2768 2769 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// 2770 2771 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001c0) 2772 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001c0) 2773 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2774 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 2775 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ 2776 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) 2777 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ 2778 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 2779 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ 2780 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) 2781 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2782 do {\ 2783 HWIO_INTLOCK(); \ 2784 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ 2785 HWIO_INTFREE();\ 2786 } while (0) 2787 2788 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2789 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2790 2791 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2792 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2793 2794 //// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// 2795 2796 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x000001c4) 2797 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x000001c4) 2798 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff 2799 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 2800 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ 2801 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) 2802 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ 2803 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 2804 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ 2805 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) 2806 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ 2807 do {\ 2808 HWIO_INTLOCK(); \ 2809 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ 2810 HWIO_INTFREE();\ 2811 } while (0) 2812 2813 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2814 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 2815 2816 //// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// 2817 2818 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001c8) 2819 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001c8) 2820 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2821 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 2822 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ 2823 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) 2824 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2825 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2826 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2827 out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2828 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2829 do {\ 2830 HWIO_INTLOCK(); \ 2831 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ 2832 HWIO_INTFREE();\ 2833 } while (0) 2834 2835 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2836 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2837 2838 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// 2839 2840 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x) (x+0x000001cc) 2841 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x) (x+0x000001cc) 2842 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK 0xffffffff 2843 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT 0 2844 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x) \ 2845 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK) 2846 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask) \ 2847 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) 2848 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val) \ 2849 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val) 2850 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 2851 do {\ 2852 HWIO_INTLOCK(); \ 2853 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \ 2854 HWIO_INTFREE();\ 2855 } while (0) 2856 2857 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2858 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2859 2860 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB //// 2861 2862 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x) (x+0x000001d0) 2863 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x) (x+0x000001d0) 2864 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK 0x00ffffff 2865 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT 0 2866 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x) \ 2867 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK) 2868 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask) \ 2869 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) 2870 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val) \ 2871 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val) 2872 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 2873 do {\ 2874 HWIO_INTLOCK(); \ 2875 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \ 2876 HWIO_INTFREE();\ 2877 } while (0) 2878 2879 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2880 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2881 2882 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2883 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2884 2885 //// Register TCL_R0_SW2TCL_CMD_RING_ID //// 2886 2887 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x000001d4) 2888 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x000001d4) 2889 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x000000ff 2890 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 2891 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ 2892 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) 2893 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask) \ 2894 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) 2895 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val) \ 2896 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val) 2897 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val) \ 2898 do {\ 2899 HWIO_INTLOCK(); \ 2900 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \ 2901 HWIO_INTFREE();\ 2902 } while (0) 2903 2904 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2905 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 2906 2907 //// Register TCL_R0_SW2TCL_CMD_RING_STATUS //// 2908 2909 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x) (x+0x000001d8) 2910 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x) (x+0x000001d8) 2911 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK 0xffffffff 2912 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT 0 2913 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x) \ 2914 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK) 2915 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask) \ 2916 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) 2917 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val) \ 2918 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val) 2919 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val) \ 2920 do {\ 2921 HWIO_INTLOCK(); \ 2922 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \ 2923 HWIO_INTFREE();\ 2924 } while (0) 2925 2926 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2927 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2928 2929 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2930 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2931 2932 //// Register TCL_R0_SW2TCL_CMD_RING_MISC //// 2933 2934 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x) (x+0x000001dc) 2935 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x) (x+0x000001dc) 2936 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK 0x0000003f 2937 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT 0 2938 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x) \ 2939 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK) 2940 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask) \ 2941 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) 2942 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val) \ 2943 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val) 2944 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val) \ 2945 do {\ 2946 HWIO_INTLOCK(); \ 2947 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \ 2948 HWIO_INTFREE();\ 2949 } while (0) 2950 2951 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2952 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2953 2954 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2955 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2956 2957 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2958 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2959 2960 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2961 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 2962 2963 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2964 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2965 2966 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2967 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2968 2969 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB //// 2970 2971 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001e8) 2972 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001e8) 2973 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 2974 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT 0 2975 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x) \ 2976 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK) 2977 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 2978 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 2979 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 2980 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 2981 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2982 do {\ 2983 HWIO_INTLOCK(); \ 2984 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \ 2985 HWIO_INTFREE();\ 2986 } while (0) 2987 2988 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2989 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2990 2991 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB //// 2992 2993 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001ec) 2994 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001ec) 2995 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 2996 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT 0 2997 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x) \ 2998 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK) 2999 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 3000 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 3001 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 3002 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 3003 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 3004 do {\ 3005 HWIO_INTLOCK(); \ 3006 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \ 3007 HWIO_INTFREE();\ 3008 } while (0) 3009 3010 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 3011 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3012 3013 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 3014 3015 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001fc) 3016 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001fc) 3017 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3018 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 3019 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 3020 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3021 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 3022 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 3023 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 3024 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 3025 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 3026 do {\ 3027 HWIO_INTLOCK(); \ 3028 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 3029 HWIO_INTFREE();\ 3030 } while (0) 3031 3032 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3033 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3034 3035 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 3036 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3037 3038 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3039 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3040 3041 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 3042 3043 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000200) 3044 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000200) 3045 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 3046 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 3047 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 3048 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3049 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 3050 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 3051 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 3052 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 3053 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 3054 do {\ 3055 HWIO_INTLOCK(); \ 3056 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 3057 HWIO_INTFREE();\ 3058 } while (0) 3059 3060 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 3061 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3062 3063 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS //// 3064 3065 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000204) 3066 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000204) 3067 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3068 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 3069 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 3070 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK) 3071 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 3072 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 3073 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 3074 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 3075 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 3076 do {\ 3077 HWIO_INTLOCK(); \ 3078 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 3079 HWIO_INTFREE();\ 3080 } while (0) 3081 3082 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3083 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3084 3085 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 3086 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3087 3088 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3089 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3090 3091 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER //// 3092 3093 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000208) 3094 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000208) 3095 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 3096 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 3097 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 3098 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3099 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 3100 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 3101 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 3102 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 3103 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 3104 do {\ 3105 HWIO_INTLOCK(); \ 3106 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 3107 HWIO_INTFREE();\ 3108 } while (0) 3109 3110 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 3111 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3112 3113 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// 3114 3115 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000020c) 3116 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000020c) 3117 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3118 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3119 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3120 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3121 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3122 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3123 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3124 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3125 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3126 do {\ 3127 HWIO_INTLOCK(); \ 3128 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3129 HWIO_INTFREE();\ 3130 } while (0) 3131 3132 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3133 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3134 3135 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS //// 3136 3137 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000210) 3138 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000210) 3139 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3140 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3141 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3142 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3143 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3144 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3145 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3146 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3147 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3148 do {\ 3149 HWIO_INTLOCK(); \ 3150 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3151 HWIO_INTFREE();\ 3152 } while (0) 3153 3154 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3155 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3156 3157 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3158 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3159 3160 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB //// 3161 3162 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000214) 3163 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000214) 3164 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3165 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT 0 3166 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x) \ 3167 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK) 3168 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 3169 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 3170 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 3171 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 3172 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3173 do {\ 3174 HWIO_INTLOCK(); \ 3175 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 3176 HWIO_INTFREE();\ 3177 } while (0) 3178 3179 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3180 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3181 3182 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB //// 3183 3184 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000218) 3185 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000218) 3186 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3187 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT 0 3188 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x) \ 3189 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK) 3190 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 3191 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 3192 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 3193 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 3194 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3195 do {\ 3196 HWIO_INTLOCK(); \ 3197 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 3198 HWIO_INTFREE();\ 3199 } while (0) 3200 3201 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3202 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3203 3204 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3205 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3206 3207 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA //// 3208 3209 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x) (x+0x0000021c) 3210 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x) (x+0x0000021c) 3211 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK 0xffffffff 3212 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT 0 3213 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x) \ 3214 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK) 3215 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask) \ 3216 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) 3217 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val) \ 3218 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val) 3219 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 3220 do {\ 3221 HWIO_INTLOCK(); \ 3222 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \ 3223 HWIO_INTFREE();\ 3224 } while (0) 3225 3226 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3227 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 3228 3229 //// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET //// 3230 3231 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000220) 3232 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000220) 3233 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3234 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 3235 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 3236 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) 3237 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3238 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3239 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3240 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3241 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3242 do {\ 3243 HWIO_INTLOCK(); \ 3244 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 3245 HWIO_INTFREE();\ 3246 } while (0) 3247 3248 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3249 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3250 3251 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// 3252 3253 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000224) 3254 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000224) 3255 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 3256 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 3257 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ 3258 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) 3259 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ 3260 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 3261 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ 3262 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) 3263 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 3264 do {\ 3265 HWIO_INTLOCK(); \ 3266 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ 3267 HWIO_INTFREE();\ 3268 } while (0) 3269 3270 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3271 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3272 3273 //// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// 3274 3275 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000228) 3276 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000228) 3277 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 3278 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 3279 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ 3280 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) 3281 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ 3282 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 3283 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ 3284 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) 3285 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 3286 do {\ 3287 HWIO_INTLOCK(); \ 3288 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ 3289 HWIO_INTFREE();\ 3290 } while (0) 3291 3292 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3293 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3294 3295 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3296 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3297 3298 //// Register TCL_R0_FW2TCL1_RING_ID //// 3299 3300 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x0000022c) 3301 #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x0000022c) 3302 #define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff 3303 #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 3304 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ 3305 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) 3306 #define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ 3307 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 3308 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ 3309 out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) 3310 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ 3311 do {\ 3312 HWIO_INTLOCK(); \ 3313 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ 3314 HWIO_INTFREE();\ 3315 } while (0) 3316 3317 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3318 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 3319 3320 //// Register TCL_R0_FW2TCL1_RING_STATUS //// 3321 3322 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x00000230) 3323 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x00000230) 3324 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff 3325 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 3326 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ 3327 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) 3328 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ 3329 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 3330 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ 3331 out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) 3332 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 3333 do {\ 3334 HWIO_INTLOCK(); \ 3335 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ 3336 HWIO_INTFREE();\ 3337 } while (0) 3338 3339 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3340 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3341 3342 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3343 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3344 3345 //// Register TCL_R0_FW2TCL1_RING_MISC //// 3346 3347 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000234) 3348 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000234) 3349 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x0000003f 3350 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 3351 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ 3352 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) 3353 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ 3354 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 3355 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ 3356 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) 3357 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ 3358 do {\ 3359 HWIO_INTLOCK(); \ 3360 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ 3361 HWIO_INTFREE();\ 3362 } while (0) 3363 3364 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3365 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3366 3367 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3368 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3369 3370 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3371 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3372 3373 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3374 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 3375 3376 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3377 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3378 3379 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3380 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3381 3382 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// 3383 3384 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000240) 3385 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000240) 3386 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 3387 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 3388 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 3389 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) 3390 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 3391 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 3392 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 3393 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 3394 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 3395 do {\ 3396 HWIO_INTLOCK(); \ 3397 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 3398 HWIO_INTFREE();\ 3399 } while (0) 3400 3401 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 3402 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 3403 3404 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// 3405 3406 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000244) 3407 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000244) 3408 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 3409 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 3410 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 3411 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) 3412 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 3413 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 3414 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 3415 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 3416 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 3417 do {\ 3418 HWIO_INTLOCK(); \ 3419 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 3420 HWIO_INTFREE();\ 3421 } while (0) 3422 3423 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 3424 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3425 3426 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 3427 3428 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000254) 3429 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000254) 3430 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3431 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 3432 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 3433 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3434 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 3435 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 3436 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 3437 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 3438 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 3439 do {\ 3440 HWIO_INTLOCK(); \ 3441 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 3442 HWIO_INTFREE();\ 3443 } while (0) 3444 3445 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3446 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3447 3448 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 3449 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3450 3451 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3452 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3453 3454 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 3455 3456 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000258) 3457 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000258) 3458 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 3459 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 3460 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 3461 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3462 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 3463 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 3464 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 3465 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 3466 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 3467 do {\ 3468 HWIO_INTLOCK(); \ 3469 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 3470 HWIO_INTFREE();\ 3471 } while (0) 3472 3473 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 3474 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3475 3476 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// 3477 3478 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000025c) 3479 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000025c) 3480 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3481 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 3482 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 3483 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 3484 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 3485 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 3486 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 3487 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 3488 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 3489 do {\ 3490 HWIO_INTLOCK(); \ 3491 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 3492 HWIO_INTFREE();\ 3493 } while (0) 3494 3495 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3496 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3497 3498 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 3499 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3500 3501 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3502 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3503 3504 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 3505 3506 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000260) 3507 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000260) 3508 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 3509 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 3510 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 3511 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3512 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 3513 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 3514 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 3515 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 3516 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 3517 do {\ 3518 HWIO_INTLOCK(); \ 3519 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 3520 HWIO_INTFREE();\ 3521 } while (0) 3522 3523 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 3524 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3525 3526 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 3527 3528 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000264) 3529 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000264) 3530 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3531 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3532 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3533 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3534 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3535 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3536 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3537 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3538 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3539 do {\ 3540 HWIO_INTLOCK(); \ 3541 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3542 HWIO_INTFREE();\ 3543 } while (0) 3544 3545 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3546 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3547 3548 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 3549 3550 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000268) 3551 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000268) 3552 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3553 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3554 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3555 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3556 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3557 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3558 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3559 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3560 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3561 do {\ 3562 HWIO_INTLOCK(); \ 3563 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3564 HWIO_INTFREE();\ 3565 } while (0) 3566 3567 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3568 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3569 3570 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3571 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3572 3573 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// 3574 3575 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000026c) 3576 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000026c) 3577 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3578 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 3579 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 3580 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) 3581 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3582 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3583 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3584 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 3585 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3586 do {\ 3587 HWIO_INTLOCK(); \ 3588 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 3589 HWIO_INTFREE();\ 3590 } while (0) 3591 3592 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3593 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3594 3595 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// 3596 3597 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000270) 3598 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000270) 3599 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3600 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 3601 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 3602 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) 3603 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3604 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3605 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3606 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 3607 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3608 do {\ 3609 HWIO_INTLOCK(); \ 3610 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 3611 HWIO_INTFREE();\ 3612 } while (0) 3613 3614 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3615 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3616 3617 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3618 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3619 3620 //// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// 3621 3622 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000274) 3623 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000274) 3624 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 3625 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 3626 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ 3627 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) 3628 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 3629 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 3630 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 3631 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) 3632 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3633 do {\ 3634 HWIO_INTLOCK(); \ 3635 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ 3636 HWIO_INTFREE();\ 3637 } while (0) 3638 3639 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3640 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 3641 3642 //// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// 3643 3644 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000278) 3645 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000278) 3646 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3647 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 3648 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 3649 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 3650 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3651 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3652 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3653 out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3654 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3655 do {\ 3656 HWIO_INTLOCK(); \ 3657 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3658 HWIO_INTFREE();\ 3659 } while (0) 3660 3661 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3662 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3663 3664 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// 3665 3666 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x0000027c) 3667 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x0000027c) 3668 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff 3669 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 3670 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ 3671 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) 3672 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ 3673 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 3674 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ 3675 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) 3676 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ 3677 do {\ 3678 HWIO_INTLOCK(); \ 3679 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ 3680 HWIO_INTFREE();\ 3681 } while (0) 3682 3683 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3684 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3685 3686 //// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// 3687 3688 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x00000280) 3689 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x00000280) 3690 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff 3691 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 3692 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ 3693 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) 3694 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ 3695 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 3696 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ 3697 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) 3698 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ 3699 do {\ 3700 HWIO_INTLOCK(); \ 3701 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ 3702 HWIO_INTFREE();\ 3703 } while (0) 3704 3705 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3706 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3707 3708 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3709 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3710 3711 //// Register TCL_R0_TCL2TQM_RING_ID //// 3712 3713 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000284) 3714 #define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000284) 3715 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff 3716 #define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 3717 #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ 3718 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) 3719 #define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ 3720 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 3721 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ 3722 out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) 3723 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ 3724 do {\ 3725 HWIO_INTLOCK(); \ 3726 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ 3727 HWIO_INTFREE();\ 3728 } while (0) 3729 3730 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 3731 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 3732 3733 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3734 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 3735 3736 //// Register TCL_R0_TCL2TQM_RING_STATUS //// 3737 3738 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000288) 3739 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000288) 3740 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff 3741 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 3742 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ 3743 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) 3744 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ 3745 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 3746 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ 3747 out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) 3748 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ 3749 do {\ 3750 HWIO_INTLOCK(); \ 3751 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ 3752 HWIO_INTFREE();\ 3753 } while (0) 3754 3755 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3756 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3757 3758 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3759 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3760 3761 //// Register TCL_R0_TCL2TQM_RING_MISC //// 3762 3763 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x0000028c) 3764 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x0000028c) 3765 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x0000003f 3766 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 3767 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ 3768 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) 3769 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ 3770 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 3771 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ 3772 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) 3773 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ 3774 do {\ 3775 HWIO_INTLOCK(); \ 3776 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ 3777 HWIO_INTFREE();\ 3778 } while (0) 3779 3780 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3781 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3782 3783 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3784 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3785 3786 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3787 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3788 3789 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3790 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 3791 3792 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3793 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3794 3795 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3796 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3797 3798 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// 3799 3800 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000290) 3801 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000290) 3802 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff 3803 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 3804 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ 3805 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) 3806 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ 3807 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 3808 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ 3809 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) 3810 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3811 do {\ 3812 HWIO_INTLOCK(); \ 3813 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ 3814 HWIO_INTFREE();\ 3815 } while (0) 3816 3817 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3818 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3819 3820 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// 3821 3822 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000294) 3823 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000294) 3824 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff 3825 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 3826 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ 3827 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) 3828 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ 3829 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 3830 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ 3831 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) 3832 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3833 do {\ 3834 HWIO_INTLOCK(); \ 3835 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ 3836 HWIO_INTFREE();\ 3837 } while (0) 3838 3839 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3840 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3841 3842 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// 3843 3844 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002a0) 3845 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002a0) 3846 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3847 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 3848 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ 3849 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) 3850 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3851 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3852 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3853 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3854 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3855 do {\ 3856 HWIO_INTLOCK(); \ 3857 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ 3858 HWIO_INTFREE();\ 3859 } while (0) 3860 3861 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3862 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3863 3864 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3865 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3866 3867 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3868 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3869 3870 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// 3871 3872 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002a4) 3873 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002a4) 3874 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3875 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 3876 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ 3877 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) 3878 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3879 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3880 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3881 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3882 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3883 do {\ 3884 HWIO_INTLOCK(); \ 3885 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ 3886 HWIO_INTFREE();\ 3887 } while (0) 3888 3889 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3890 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3891 3892 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3893 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3894 3895 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3896 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3897 3898 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// 3899 3900 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002a8) 3901 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002a8) 3902 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3903 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 3904 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3905 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) 3906 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3907 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3908 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3909 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3910 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3911 do {\ 3912 HWIO_INTLOCK(); \ 3913 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3914 HWIO_INTFREE();\ 3915 } while (0) 3916 3917 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3918 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3919 3920 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// 3921 3922 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d0) 3923 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d0) 3924 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3925 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 3926 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ 3927 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) 3928 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3929 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3930 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3931 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3932 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3933 do {\ 3934 HWIO_INTLOCK(); \ 3935 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ 3936 HWIO_INTFREE();\ 3937 } while (0) 3938 3939 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3940 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3941 3942 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// 3943 3944 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000002d4) 3945 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000002d4) 3946 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff 3947 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 3948 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ 3949 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) 3950 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ 3951 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 3952 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ 3953 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) 3954 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ 3955 do {\ 3956 HWIO_INTLOCK(); \ 3957 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ 3958 HWIO_INTFREE();\ 3959 } while (0) 3960 3961 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3962 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3963 3964 //// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// 3965 3966 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000002d8) 3967 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000002d8) 3968 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff 3969 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 3970 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ 3971 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) 3972 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ 3973 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 3974 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ 3975 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) 3976 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ 3977 do {\ 3978 HWIO_INTLOCK(); \ 3979 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ 3980 HWIO_INTFREE();\ 3981 } while (0) 3982 3983 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3984 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3985 3986 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3987 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3988 3989 //// Register TCL_R0_TCL_STATUS1_RING_ID //// 3990 3991 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000002dc) 3992 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000002dc) 3993 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff 3994 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 3995 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ 3996 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) 3997 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ 3998 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 3999 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ 4000 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) 4001 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ 4002 do {\ 4003 HWIO_INTLOCK(); \ 4004 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ 4005 HWIO_INTFREE();\ 4006 } while (0) 4007 4008 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 4009 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 4010 4011 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4012 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 4013 4014 //// Register TCL_R0_TCL_STATUS1_RING_STATUS //// 4015 4016 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000002e0) 4017 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000002e0) 4018 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff 4019 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 4020 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ 4021 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) 4022 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ 4023 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 4024 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ 4025 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) 4026 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ 4027 do {\ 4028 HWIO_INTLOCK(); \ 4029 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ 4030 HWIO_INTFREE();\ 4031 } while (0) 4032 4033 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4034 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4035 4036 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4037 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4038 4039 //// Register TCL_R0_TCL_STATUS1_RING_MISC //// 4040 4041 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000002e4) 4042 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000002e4) 4043 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x0000003f 4044 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 4045 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ 4046 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) 4047 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ 4048 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 4049 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ 4050 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) 4051 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ 4052 do {\ 4053 HWIO_INTLOCK(); \ 4054 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ 4055 HWIO_INTFREE();\ 4056 } while (0) 4057 4058 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4059 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4060 4061 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4062 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4063 4064 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4065 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4066 4067 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4068 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 4069 4070 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4071 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4072 4073 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4074 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4075 4076 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// 4077 4078 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002e8) 4079 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002e8) 4080 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff 4081 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 4082 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ 4083 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) 4084 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ 4085 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 4086 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ 4087 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) 4088 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4089 do {\ 4090 HWIO_INTLOCK(); \ 4091 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ 4092 HWIO_INTFREE();\ 4093 } while (0) 4094 4095 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4096 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4097 4098 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// 4099 4100 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002ec) 4101 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002ec) 4102 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff 4103 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 4104 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ 4105 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) 4106 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ 4107 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 4108 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ 4109 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) 4110 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4111 do {\ 4112 HWIO_INTLOCK(); \ 4113 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ 4114 HWIO_INTFREE();\ 4115 } while (0) 4116 4117 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4118 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4119 4120 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// 4121 4122 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002f8) 4123 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002f8) 4124 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4125 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 4126 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ 4127 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) 4128 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4129 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4130 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4131 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4132 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4133 do {\ 4134 HWIO_INTLOCK(); \ 4135 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ 4136 HWIO_INTFREE();\ 4137 } while (0) 4138 4139 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4140 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4141 4142 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4143 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4144 4145 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4146 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4147 4148 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// 4149 4150 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002fc) 4151 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002fc) 4152 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4153 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 4154 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ 4155 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) 4156 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4157 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4158 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4159 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4160 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4161 do {\ 4162 HWIO_INTLOCK(); \ 4163 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ 4164 HWIO_INTFREE();\ 4165 } while (0) 4166 4167 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4168 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4169 4170 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4171 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4172 4173 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4174 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4175 4176 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// 4177 4178 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000300) 4179 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000300) 4180 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4181 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 4182 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4183 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) 4184 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4185 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4186 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4187 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4188 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4189 do {\ 4190 HWIO_INTLOCK(); \ 4191 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4192 HWIO_INTFREE();\ 4193 } while (0) 4194 4195 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4196 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4197 4198 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// 4199 4200 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000031c) 4201 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000031c) 4202 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4203 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 4204 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ 4205 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) 4206 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ 4207 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 4208 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ 4209 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) 4210 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4211 do {\ 4212 HWIO_INTLOCK(); \ 4213 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ 4214 HWIO_INTFREE();\ 4215 } while (0) 4216 4217 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4218 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4219 4220 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// 4221 4222 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000320) 4223 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000320) 4224 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4225 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 4226 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ 4227 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) 4228 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ 4229 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 4230 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ 4231 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) 4232 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4233 do {\ 4234 HWIO_INTLOCK(); \ 4235 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ 4236 HWIO_INTFREE();\ 4237 } while (0) 4238 4239 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4240 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4241 4242 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4243 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4244 4245 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// 4246 4247 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x00000324) 4248 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x00000324) 4249 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff 4250 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 4251 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ 4252 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) 4253 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ 4254 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 4255 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ 4256 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) 4257 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ 4258 do {\ 4259 HWIO_INTLOCK(); \ 4260 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ 4261 HWIO_INTFREE();\ 4262 } while (0) 4263 4264 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4265 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 4266 4267 //// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// 4268 4269 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000328) 4270 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000328) 4271 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4272 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 4273 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ 4274 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) 4275 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4276 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4277 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4278 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4279 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4280 do {\ 4281 HWIO_INTLOCK(); \ 4282 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ 4283 HWIO_INTFREE();\ 4284 } while (0) 4285 4286 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4287 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4288 4289 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// 4290 4291 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x0000032c) 4292 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x0000032c) 4293 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff 4294 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 4295 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ 4296 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) 4297 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ 4298 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 4299 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ 4300 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) 4301 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ 4302 do {\ 4303 HWIO_INTLOCK(); \ 4304 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ 4305 HWIO_INTFREE();\ 4306 } while (0) 4307 4308 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4309 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4310 4311 //// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// 4312 4313 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x00000330) 4314 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x00000330) 4315 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff 4316 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 4317 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ 4318 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) 4319 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ 4320 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 4321 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ 4322 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) 4323 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ 4324 do {\ 4325 HWIO_INTLOCK(); \ 4326 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ 4327 HWIO_INTFREE();\ 4328 } while (0) 4329 4330 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4331 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4332 4333 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4334 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4335 4336 //// Register TCL_R0_TCL_STATUS2_RING_ID //// 4337 4338 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000334) 4339 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000334) 4340 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff 4341 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 4342 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ 4343 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) 4344 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ 4345 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 4346 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ 4347 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) 4348 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ 4349 do {\ 4350 HWIO_INTLOCK(); \ 4351 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ 4352 HWIO_INTFREE();\ 4353 } while (0) 4354 4355 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 4356 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 4357 4358 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4359 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 4360 4361 //// Register TCL_R0_TCL_STATUS2_RING_STATUS //// 4362 4363 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000338) 4364 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000338) 4365 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff 4366 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 4367 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ 4368 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) 4369 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ 4370 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 4371 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ 4372 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) 4373 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ 4374 do {\ 4375 HWIO_INTLOCK(); \ 4376 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ 4377 HWIO_INTFREE();\ 4378 } while (0) 4379 4380 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4381 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4382 4383 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4384 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4385 4386 //// Register TCL_R0_TCL_STATUS2_RING_MISC //// 4387 4388 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x0000033c) 4389 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x0000033c) 4390 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x0000003f 4391 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 4392 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ 4393 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) 4394 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ 4395 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 4396 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ 4397 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) 4398 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ 4399 do {\ 4400 HWIO_INTLOCK(); \ 4401 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ 4402 HWIO_INTFREE();\ 4403 } while (0) 4404 4405 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4406 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4407 4408 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4409 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4410 4411 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4412 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4413 4414 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4415 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 4416 4417 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4418 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4419 4420 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4421 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4422 4423 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// 4424 4425 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000340) 4426 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000340) 4427 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff 4428 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 4429 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ 4430 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) 4431 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ 4432 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 4433 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ 4434 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) 4435 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4436 do {\ 4437 HWIO_INTLOCK(); \ 4438 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ 4439 HWIO_INTFREE();\ 4440 } while (0) 4441 4442 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4443 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4444 4445 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// 4446 4447 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000344) 4448 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000344) 4449 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff 4450 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 4451 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ 4452 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) 4453 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ 4454 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 4455 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ 4456 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) 4457 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4458 do {\ 4459 HWIO_INTLOCK(); \ 4460 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ 4461 HWIO_INTFREE();\ 4462 } while (0) 4463 4464 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4465 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4466 4467 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// 4468 4469 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000350) 4470 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000350) 4471 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4472 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 4473 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ 4474 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) 4475 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4476 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4477 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4478 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4479 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4480 do {\ 4481 HWIO_INTLOCK(); \ 4482 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ 4483 HWIO_INTFREE();\ 4484 } while (0) 4485 4486 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4487 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4488 4489 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4490 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4491 4492 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4493 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4494 4495 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// 4496 4497 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000354) 4498 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000354) 4499 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4500 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 4501 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ 4502 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) 4503 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4504 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4505 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4506 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4507 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4508 do {\ 4509 HWIO_INTLOCK(); \ 4510 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ 4511 HWIO_INTFREE();\ 4512 } while (0) 4513 4514 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4515 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4516 4517 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4518 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4519 4520 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4521 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4522 4523 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// 4524 4525 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000358) 4526 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000358) 4527 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4528 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 4529 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4530 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) 4531 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4532 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4533 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4534 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4535 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4536 do {\ 4537 HWIO_INTLOCK(); \ 4538 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4539 HWIO_INTFREE();\ 4540 } while (0) 4541 4542 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4543 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4544 4545 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// 4546 4547 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000374) 4548 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000374) 4549 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4550 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 4551 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ 4552 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) 4553 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ 4554 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 4555 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ 4556 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) 4557 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4558 do {\ 4559 HWIO_INTLOCK(); \ 4560 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ 4561 HWIO_INTFREE();\ 4562 } while (0) 4563 4564 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4565 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4566 4567 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// 4568 4569 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000378) 4570 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000378) 4571 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4572 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 4573 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ 4574 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) 4575 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ 4576 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 4577 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ 4578 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) 4579 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4580 do {\ 4581 HWIO_INTLOCK(); \ 4582 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ 4583 HWIO_INTFREE();\ 4584 } while (0) 4585 4586 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4587 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4588 4589 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4590 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4591 4592 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// 4593 4594 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x0000037c) 4595 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x0000037c) 4596 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff 4597 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 4598 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ 4599 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) 4600 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ 4601 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 4602 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ 4603 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) 4604 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ 4605 do {\ 4606 HWIO_INTLOCK(); \ 4607 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ 4608 HWIO_INTFREE();\ 4609 } while (0) 4610 4611 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4612 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 4613 4614 //// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// 4615 4616 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000380) 4617 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000380) 4618 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4619 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 4620 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ 4621 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) 4622 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4623 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4624 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4625 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4626 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4627 do {\ 4628 HWIO_INTLOCK(); \ 4629 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ 4630 HWIO_INTFREE();\ 4631 } while (0) 4632 4633 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4634 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4635 4636 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// 4637 4638 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000384) 4639 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000384) 4640 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff 4641 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 4642 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ 4643 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) 4644 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ 4645 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 4646 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ 4647 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) 4648 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4649 do {\ 4650 HWIO_INTLOCK(); \ 4651 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ 4652 HWIO_INTFREE();\ 4653 } while (0) 4654 4655 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4656 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4657 4658 //// Register TCL_R0_TCL2FW_RING_BASE_MSB //// 4659 4660 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000388) 4661 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000388) 4662 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff 4663 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 4664 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ 4665 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) 4666 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ 4667 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 4668 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ 4669 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) 4670 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4671 do {\ 4672 HWIO_INTLOCK(); \ 4673 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ 4674 HWIO_INTFREE();\ 4675 } while (0) 4676 4677 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4678 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4679 4680 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4681 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4682 4683 //// Register TCL_R0_TCL2FW_RING_ID //// 4684 4685 #define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x0000038c) 4686 #define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x0000038c) 4687 #define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff 4688 #define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 4689 #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ 4690 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) 4691 #define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ 4692 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 4693 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ 4694 out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) 4695 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ 4696 do {\ 4697 HWIO_INTLOCK(); \ 4698 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ 4699 HWIO_INTFREE();\ 4700 } while (0) 4701 4702 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4703 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 4704 4705 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4706 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4707 4708 //// Register TCL_R0_TCL2FW_RING_STATUS //// 4709 4710 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x00000390) 4711 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x00000390) 4712 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff 4713 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 4714 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ 4715 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) 4716 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ 4717 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 4718 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ 4719 out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) 4720 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ 4721 do {\ 4722 HWIO_INTLOCK(); \ 4723 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ 4724 HWIO_INTFREE();\ 4725 } while (0) 4726 4727 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4728 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4729 4730 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4731 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4732 4733 //// Register TCL_R0_TCL2FW_RING_MISC //// 4734 4735 #define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000394) 4736 #define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000394) 4737 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x0000003f 4738 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 4739 #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ 4740 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) 4741 #define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ 4742 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 4743 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ 4744 out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) 4745 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ 4746 do {\ 4747 HWIO_INTLOCK(); \ 4748 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ 4749 HWIO_INTFREE();\ 4750 } while (0) 4751 4752 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4753 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4754 4755 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4756 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4757 4758 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4759 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4760 4761 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4762 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4763 4764 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4765 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4766 4767 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4768 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4769 4770 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// 4771 4772 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000398) 4773 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000398) 4774 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4775 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 4776 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ 4777 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) 4778 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4779 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4780 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4781 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4782 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4783 do {\ 4784 HWIO_INTLOCK(); \ 4785 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ 4786 HWIO_INTFREE();\ 4787 } while (0) 4788 4789 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4790 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4791 4792 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// 4793 4794 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000039c) 4795 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000039c) 4796 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4797 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 4798 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ 4799 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) 4800 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4801 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4802 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4803 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4804 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4805 do {\ 4806 HWIO_INTLOCK(); \ 4807 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ 4808 HWIO_INTFREE();\ 4809 } while (0) 4810 4811 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4812 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4813 4814 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// 4815 4816 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003a8) 4817 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003a8) 4818 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4819 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4820 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4821 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) 4822 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4823 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4824 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4825 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4826 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4827 do {\ 4828 HWIO_INTLOCK(); \ 4829 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4830 HWIO_INTFREE();\ 4831 } while (0) 4832 4833 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4834 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4835 4836 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4837 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4838 4839 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4840 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4841 4842 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// 4843 4844 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003ac) 4845 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003ac) 4846 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4847 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4848 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4849 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) 4850 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4851 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4852 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4853 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4854 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4855 do {\ 4856 HWIO_INTLOCK(); \ 4857 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4858 HWIO_INTFREE();\ 4859 } while (0) 4860 4861 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4862 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4863 4864 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4865 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4866 4867 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4868 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4869 4870 //// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// 4871 4872 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b0) 4873 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b0) 4874 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4875 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4876 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4877 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4878 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4879 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4880 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4881 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4882 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4883 do {\ 4884 HWIO_INTLOCK(); \ 4885 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4886 HWIO_INTFREE();\ 4887 } while (0) 4888 4889 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4890 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4891 4892 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// 4893 4894 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003d8) 4895 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003d8) 4896 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4897 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 4898 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 4899 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) 4900 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4901 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4902 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4903 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4904 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4905 do {\ 4906 HWIO_INTLOCK(); \ 4907 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 4908 HWIO_INTFREE();\ 4909 } while (0) 4910 4911 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4912 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4913 4914 //// Register TCL_R0_GXI_TESTBUS_LOWER //// 4915 4916 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000003dc) 4917 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000003dc) 4918 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 4919 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 4920 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ 4921 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) 4922 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 4923 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 4924 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 4925 out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 4926 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 4927 do {\ 4928 HWIO_INTLOCK(); \ 4929 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ 4930 HWIO_INTFREE();\ 4931 } while (0) 4932 4933 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 4934 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 4935 4936 //// Register TCL_R0_GXI_TESTBUS_UPPER //// 4937 4938 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000003e0) 4939 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000003e0) 4940 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 4941 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 4942 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ 4943 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) 4944 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 4945 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 4946 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 4947 out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 4948 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 4949 do {\ 4950 HWIO_INTLOCK(); \ 4951 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ 4952 HWIO_INTFREE();\ 4953 } while (0) 4954 4955 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 4956 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 4957 4958 //// Register TCL_R0_GXI_SM_STATES_IX_0 //// 4959 4960 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000003e4) 4961 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000003e4) 4962 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 4963 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 4964 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ 4965 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) 4966 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 4967 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 4968 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 4969 out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 4970 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 4971 do {\ 4972 HWIO_INTLOCK(); \ 4973 out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ 4974 HWIO_INTFREE();\ 4975 } while (0) 4976 4977 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 4978 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 4979 4980 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 4981 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 4982 4983 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 4984 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 4985 4986 //// Register TCL_R0_GXI_END_OF_TEST_CHECK //// 4987 4988 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000003e8) 4989 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000003e8) 4990 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 4991 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 4992 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 4993 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) 4994 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 4995 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 4996 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 4997 out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 4998 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 4999 do {\ 5000 HWIO_INTLOCK(); \ 5001 out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 5002 HWIO_INTFREE();\ 5003 } while (0) 5004 5005 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5006 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5007 5008 //// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// 5009 5010 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000003ec) 5011 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000003ec) 5012 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 5013 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 5014 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 5015 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 5016 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 5017 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 5018 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 5019 out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 5020 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 5021 do {\ 5022 HWIO_INTLOCK(); \ 5023 out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 5024 HWIO_INTFREE();\ 5025 } while (0) 5026 5027 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 5028 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 5029 5030 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff 5031 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 5032 5033 //// Register TCL_R0_GXI_GXI_ERR_INTS //// 5034 5035 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000003f0) 5036 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000003f0) 5037 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 5038 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 5039 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ 5040 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) 5041 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 5042 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 5043 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 5044 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 5045 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 5046 do {\ 5047 HWIO_INTLOCK(); \ 5048 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ 5049 HWIO_INTFREE();\ 5050 } while (0) 5051 5052 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 5053 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 5054 5055 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 5056 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 5057 5058 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 5059 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 5060 5061 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 5062 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 5063 5064 //// Register TCL_R0_GXI_GXI_ERR_STATS //// 5065 5066 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000003f4) 5067 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000003f4) 5068 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 5069 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 5070 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ 5071 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) 5072 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 5073 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 5074 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 5075 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 5076 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 5077 do {\ 5078 HWIO_INTLOCK(); \ 5079 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ 5080 HWIO_INTFREE();\ 5081 } while (0) 5082 5083 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 5084 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 5085 5086 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 5087 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 5088 5089 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 5090 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 5091 5092 //// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// 5093 5094 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000003f8) 5095 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000003f8) 5096 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 5097 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 5098 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 5099 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 5100 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 5101 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 5102 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 5103 out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 5104 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 5105 do {\ 5106 HWIO_INTLOCK(); \ 5107 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 5108 HWIO_INTFREE();\ 5109 } while (0) 5110 5111 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 5112 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 5113 5114 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 5115 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 5116 5117 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 5118 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 5119 5120 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 5121 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 5122 5123 //// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// 5124 5125 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000003fc) 5126 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000003fc) 5127 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 5128 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 5129 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 5130 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 5131 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 5132 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 5133 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 5134 out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 5135 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 5136 do {\ 5137 HWIO_INTLOCK(); \ 5138 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 5139 HWIO_INTFREE();\ 5140 } while (0) 5141 5142 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 5143 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 5144 5145 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 5146 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 5147 5148 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 5149 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 5150 5151 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 5152 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 5153 5154 //// Register TCL_R0_GXI_GXI_MISC_CONTROL //// 5155 5156 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000400) 5157 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000400) 5158 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff 5159 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 5160 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 5161 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) 5162 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 5163 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 5164 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 5165 out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 5166 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 5167 do {\ 5168 HWIO_INTLOCK(); \ 5169 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 5170 HWIO_INTFREE();\ 5171 } while (0) 5172 5173 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 5174 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 5175 5176 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 5177 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 5178 5179 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 5180 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 5181 5182 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 5183 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 5184 5185 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 5186 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 5187 5188 //// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// 5189 5190 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000404) 5191 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000404) 5192 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 5193 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 5194 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 5195 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) 5196 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 5197 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 5198 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 5199 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 5200 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 5201 do {\ 5202 HWIO_INTLOCK(); \ 5203 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 5204 HWIO_INTFREE();\ 5205 } while (0) 5206 5207 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 5208 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 5209 5210 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 5211 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 5212 5213 //// Register TCL_R0_GXI_GXI_WDOG_STATUS //// 5214 5215 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000408) 5216 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000408) 5217 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 5218 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 5219 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 5220 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) 5221 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 5222 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 5223 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 5224 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 5225 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 5226 do {\ 5227 HWIO_INTLOCK(); \ 5228 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 5229 HWIO_INTFREE();\ 5230 } while (0) 5231 5232 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 5233 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 5234 5235 //// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// 5236 5237 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x0000040c) 5238 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x0000040c) 5239 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 5240 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 5241 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 5242 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 5243 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 5244 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 5245 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 5246 out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 5247 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 5248 do {\ 5249 HWIO_INTLOCK(); \ 5250 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 5251 HWIO_INTFREE();\ 5252 } while (0) 5253 5254 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 5255 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 5256 5257 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 5258 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 5259 5260 //// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// 5261 5262 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000410) 5263 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000410) 5264 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 5265 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 5266 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ 5267 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) 5268 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ 5269 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 5270 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ 5271 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) 5272 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 5273 do {\ 5274 HWIO_INTLOCK(); \ 5275 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ 5276 HWIO_INTFREE();\ 5277 } while (0) 5278 5279 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5280 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5281 5282 //// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// 5283 5284 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000414) 5285 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000414) 5286 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5287 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 5288 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ 5289 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) 5290 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5291 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5292 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5293 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5294 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5295 do {\ 5296 HWIO_INTLOCK(); \ 5297 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ 5298 HWIO_INTFREE();\ 5299 } while (0) 5300 5301 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5302 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5303 5304 //// Register TCL_R0_ASE_GST_SIZE //// 5305 5306 #define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000418) 5307 #define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000418) 5308 #define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff 5309 #define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 5310 #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ 5311 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) 5312 #define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ 5313 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 5314 #define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ 5315 out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) 5316 #define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ 5317 do {\ 5318 HWIO_INTLOCK(); \ 5319 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ 5320 HWIO_INTFREE();\ 5321 } while (0) 5322 5323 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff 5324 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 5325 5326 //// Register TCL_R0_ASE_SEARCH_CTRL //// 5327 5328 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x0000041c) 5329 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x0000041c) 5330 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff03ff 5331 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 5332 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ 5333 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) 5334 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ 5335 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 5336 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ 5337 out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) 5338 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ 5339 do {\ 5340 HWIO_INTLOCK(); \ 5341 out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ 5342 HWIO_INTFREE();\ 5343 } while (0) 5344 5345 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5346 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5347 5348 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5349 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5350 5351 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5352 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5353 5354 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5355 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5356 5357 //// Register TCL_R0_ASE_WATCHDOG //// 5358 5359 #define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000420) 5360 #define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000420) 5361 #define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff 5362 #define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 5363 #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ 5364 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) 5365 #define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ 5366 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 5367 #define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ 5368 out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) 5369 #define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ 5370 do {\ 5371 HWIO_INTLOCK(); \ 5372 out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ 5373 HWIO_INTFREE();\ 5374 } while (0) 5375 5376 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 5377 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 5378 5379 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5380 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 5381 5382 //// Register TCL_R0_ASE_CLKGATE_DISABLE //// 5383 5384 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000424) 5385 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000424) 5386 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff 5387 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 5388 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ 5389 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) 5390 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ 5391 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 5392 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ 5393 out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) 5394 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5395 do {\ 5396 HWIO_INTLOCK(); \ 5397 out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ 5398 HWIO_INTFREE();\ 5399 } while (0) 5400 5401 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_BMSK 0xffffffff 5402 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_SHFT 0x0 5403 5404 //// Register TCL_R0_ASE_WRITE_BACK_PENDING //// 5405 5406 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000428) 5407 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000428) 5408 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 5409 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 5410 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ 5411 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) 5412 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ 5413 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 5414 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ 5415 out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) 5416 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5417 do {\ 5418 HWIO_INTLOCK(); \ 5419 out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ 5420 HWIO_INTFREE();\ 5421 } while (0) 5422 5423 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5424 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5425 5426 //// Register TCL_R0_FSE_GST_BASE_ADDR_LOW //// 5427 5428 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x0000042c) 5429 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x0000042c) 5430 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 5431 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_SHFT 0 5432 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x) \ 5433 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK) 5434 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask) \ 5435 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) 5436 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val) \ 5437 out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val) 5438 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 5439 do {\ 5440 HWIO_INTLOCK(); \ 5441 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \ 5442 HWIO_INTFREE();\ 5443 } while (0) 5444 5445 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5446 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5447 5448 //// Register TCL_R0_FSE_GST_BASE_ADDR_HIGH //// 5449 5450 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000430) 5451 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000430) 5452 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5453 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_SHFT 0 5454 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x) \ 5455 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK) 5456 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5457 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5458 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5459 out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5460 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5461 do {\ 5462 HWIO_INTLOCK(); \ 5463 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \ 5464 HWIO_INTFREE();\ 5465 } while (0) 5466 5467 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5468 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5469 5470 //// Register TCL_R0_FSE_GST_SIZE //// 5471 5472 #define HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x) (x+0x00000434) 5473 #define HWIO_TCL_R0_FSE_GST_SIZE_PHYS(x) (x+0x00000434) 5474 #define HWIO_TCL_R0_FSE_GST_SIZE_RMSK 0x000fffff 5475 #define HWIO_TCL_R0_FSE_GST_SIZE_SHFT 0 5476 #define HWIO_TCL_R0_FSE_GST_SIZE_IN(x) \ 5477 in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK) 5478 #define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask) \ 5479 in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) 5480 #define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val) \ 5481 out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val) 5482 #define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val) \ 5483 do {\ 5484 HWIO_INTLOCK(); \ 5485 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \ 5486 HWIO_INTFREE();\ 5487 } while (0) 5488 5489 #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK 0x000fffff 5490 #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT 0x0 5491 5492 //// Register TCL_R0_FSE_SEARCH_CTRL //// 5493 5494 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x) (x+0x00000438) 5495 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_PHYS(x) (x+0x00000438) 5496 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK 0xffff03ff 5497 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SHFT 0 5498 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x) \ 5499 in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK) 5500 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask) \ 5501 in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) 5502 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val) \ 5503 out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val) 5504 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val) \ 5505 do {\ 5506 HWIO_INTLOCK(); \ 5507 out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \ 5508 HWIO_INTFREE();\ 5509 } while (0) 5510 5511 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5512 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5513 5514 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5515 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5516 5517 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5518 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5519 5520 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5521 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5522 5523 //// Register TCL_R0_FSE_WATCHDOG //// 5524 5525 #define HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x) (x+0x0000043c) 5526 #define HWIO_TCL_R0_FSE_WATCHDOG_PHYS(x) (x+0x0000043c) 5527 #define HWIO_TCL_R0_FSE_WATCHDOG_RMSK 0xffffffff 5528 #define HWIO_TCL_R0_FSE_WATCHDOG_SHFT 0 5529 #define HWIO_TCL_R0_FSE_WATCHDOG_IN(x) \ 5530 in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK) 5531 #define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask) \ 5532 in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) 5533 #define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val) \ 5534 out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val) 5535 #define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val) \ 5536 do {\ 5537 HWIO_INTLOCK(); \ 5538 out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \ 5539 HWIO_INTFREE();\ 5540 } while (0) 5541 5542 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK 0xffff0000 5543 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT 0x10 5544 5545 #define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5546 #define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_SHFT 0x0 5547 5548 //// Register TCL_R0_FSE_CLKGATE_DISABLE //// 5549 5550 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x) (x+0x00000440) 5551 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PHYS(x) (x+0x00000440) 5552 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK 0xffffffff 5553 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SHFT 0 5554 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x) \ 5555 in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK) 5556 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask) \ 5557 in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) 5558 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val) \ 5559 out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val) 5560 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5561 do {\ 5562 HWIO_INTLOCK(); \ 5563 out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \ 5564 HWIO_INTFREE();\ 5565 } while (0) 5566 5567 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_BMSK 0xffffffff 5568 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_SHFT 0x0 5569 5570 //// Register TCL_R0_FSE_WRITE_BACK_PENDING //// 5571 5572 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000444) 5573 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000444) 5574 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK 0x00000001 5575 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_SHFT 0 5576 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x) \ 5577 in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK) 5578 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask) \ 5579 in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) 5580 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val) \ 5581 out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val) 5582 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5583 do {\ 5584 HWIO_INTLOCK(); \ 5585 out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \ 5586 HWIO_INTFREE();\ 5587 } while (0) 5588 5589 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5590 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5591 5592 //// Register TCL_R1_SM_STATES_IX_0 //// 5593 5594 #define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001000) 5595 #define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001000) 5596 #define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff 5597 #define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 5598 #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ 5599 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) 5600 #define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ 5601 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 5602 #define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ 5603 out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) 5604 #define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 5605 do {\ 5606 HWIO_INTLOCK(); \ 5607 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ 5608 HWIO_INTFREE();\ 5609 } while (0) 5610 5611 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 5612 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 5613 5614 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 5615 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 5616 5617 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 5618 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 5619 5620 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 5621 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf 5622 5623 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK 0x00007000 5624 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT 0xc 5625 5626 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 5627 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 5628 5629 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 5630 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 5631 5632 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 5633 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 5634 5635 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 5636 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 5637 5638 //// Register TCL_R1_SM_STATES_IX_1 //// 5639 5640 #define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001004) 5641 #define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001004) 5642 #define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x00007fff 5643 #define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 5644 #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ 5645 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) 5646 #define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ 5647 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 5648 #define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ 5649 out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) 5650 #define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 5651 do {\ 5652 HWIO_INTLOCK(); \ 5653 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ 5654 HWIO_INTFREE();\ 5655 } while (0) 5656 5657 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 5658 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc 5659 5660 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 5661 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 5662 5663 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 5664 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 5665 5666 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 5667 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 5668 5669 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 5670 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 5671 5672 //// Register TCL_R1_TESTBUS_CTRL_0 //// 5673 5674 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001008) 5675 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001008) 5676 #define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x1fffffff 5677 #define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 5678 #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ 5679 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) 5680 #define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ 5681 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 5682 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ 5683 out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) 5684 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ 5685 do {\ 5686 HWIO_INTLOCK(); \ 5687 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ 5688 HWIO_INTFREE();\ 5689 } while (0) 5690 5691 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 5692 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 5693 5694 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 5695 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 5696 5697 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 5698 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe 5699 5700 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 5701 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa 5702 5703 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 5704 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 5705 5706 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f 5707 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 5708 5709 //// Register TCL_R1_TESTBUS_LOW //// 5710 5711 #define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x0000100c) 5712 #define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x0000100c) 5713 #define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff 5714 #define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 5715 #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ 5716 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) 5717 #define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ 5718 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 5719 #define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ 5720 out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) 5721 #define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 5722 do {\ 5723 HWIO_INTLOCK(); \ 5724 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ 5725 HWIO_INTFREE();\ 5726 } while (0) 5727 5728 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 5729 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 5730 5731 //// Register TCL_R1_TESTBUS_HIGH //// 5732 5733 #define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001010) 5734 #define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001010) 5735 #define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff 5736 #define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 5737 #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ 5738 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) 5739 #define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ 5740 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 5741 #define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ 5742 out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) 5743 #define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 5744 do {\ 5745 HWIO_INTLOCK(); \ 5746 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ 5747 HWIO_INTFREE();\ 5748 } while (0) 5749 5750 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 5751 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 5752 5753 //// Register TCL_R1_EVENTMASK_IX_0 //// 5754 5755 #define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001014) 5756 #define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001014) 5757 #define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff 5758 #define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 5759 #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ 5760 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) 5761 #define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ 5762 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 5763 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ 5764 out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) 5765 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 5766 do {\ 5767 HWIO_INTLOCK(); \ 5768 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ 5769 HWIO_INTFREE();\ 5770 } while (0) 5771 5772 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff 5773 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 5774 5775 //// Register TCL_R1_EVENTMASK_IX_1 //// 5776 5777 #define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001018) 5778 #define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001018) 5779 #define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff 5780 #define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 5781 #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ 5782 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) 5783 #define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ 5784 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 5785 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ 5786 out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) 5787 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 5788 do {\ 5789 HWIO_INTLOCK(); \ 5790 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ 5791 HWIO_INTFREE();\ 5792 } while (0) 5793 5794 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff 5795 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 5796 5797 //// Register TCL_R1_EVENTMASK_IX_2 //// 5798 5799 #define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x0000101c) 5800 #define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x0000101c) 5801 #define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff 5802 #define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 5803 #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ 5804 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) 5805 #define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ 5806 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 5807 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ 5808 out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) 5809 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ 5810 do {\ 5811 HWIO_INTLOCK(); \ 5812 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ 5813 HWIO_INTFREE();\ 5814 } while (0) 5815 5816 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff 5817 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 5818 5819 //// Register TCL_R1_EVENTMASK_IX_3 //// 5820 5821 #define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001020) 5822 #define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001020) 5823 #define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff 5824 #define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 5825 #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ 5826 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) 5827 #define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ 5828 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 5829 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ 5830 out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) 5831 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ 5832 do {\ 5833 HWIO_INTLOCK(); \ 5834 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ 5835 HWIO_INTFREE();\ 5836 } while (0) 5837 5838 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff 5839 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 5840 5841 //// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// 5842 5843 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001024) 5844 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001024) 5845 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 5846 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 5847 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 5848 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 5849 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 5850 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 5851 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 5852 out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 5853 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 5854 do {\ 5855 HWIO_INTLOCK(); \ 5856 out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 5857 HWIO_INTFREE();\ 5858 } while (0) 5859 5860 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 5861 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 5862 5863 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 5864 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 5865 5866 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 5867 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 5868 5869 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 5870 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 5871 5872 //// Register TCL_R1_END_OF_TEST_CHECK //// 5873 5874 #define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001028) 5875 #define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001028) 5876 #define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 5877 #define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 5878 #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ 5879 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) 5880 #define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ 5881 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 5882 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ 5883 out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) 5884 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5885 do {\ 5886 HWIO_INTLOCK(); \ 5887 out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ 5888 HWIO_INTFREE();\ 5889 } while (0) 5890 5891 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5892 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5893 5894 //// Register TCL_R1_ASE_END_OF_TEST_CHECK //// 5895 5896 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000102c) 5897 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000102c) 5898 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 5899 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 5900 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ 5901 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) 5902 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ 5903 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 5904 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ 5905 out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) 5906 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5907 do {\ 5908 HWIO_INTLOCK(); \ 5909 out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ 5910 HWIO_INTFREE();\ 5911 } while (0) 5912 5913 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5914 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5915 5916 //// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// 5917 5918 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001030) 5919 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001030) 5920 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 5921 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 5922 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ 5923 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) 5924 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 5925 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 5926 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 5927 out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 5928 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 5929 do {\ 5930 HWIO_INTLOCK(); \ 5931 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 5932 HWIO_INTFREE();\ 5933 } while (0) 5934 5935 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 5936 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 5937 5938 //// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// 5939 5940 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001034) 5941 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001034) 5942 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 5943 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 5944 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 5945 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 5946 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 5947 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 5948 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 5949 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 5950 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 5951 do {\ 5952 HWIO_INTLOCK(); \ 5953 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 5954 HWIO_INTFREE();\ 5955 } while (0) 5956 5957 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 5958 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 5959 5960 //// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// 5961 5962 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001038) 5963 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001038) 5964 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 5965 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 5966 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 5967 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 5968 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 5969 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 5970 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 5971 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 5972 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 5973 do {\ 5974 HWIO_INTLOCK(); \ 5975 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 5976 HWIO_INTFREE();\ 5977 } while (0) 5978 5979 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 5980 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 5981 5982 //// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 5983 5984 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x0000103c) 5985 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x0000103c) 5986 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 5987 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 5988 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 5989 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 5990 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 5991 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 5992 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 5993 out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 5994 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 5995 do {\ 5996 HWIO_INTLOCK(); \ 5997 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 5998 HWIO_INTFREE();\ 5999 } while (0) 6000 6001 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 6002 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 6003 6004 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 6005 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 6006 6007 //// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// 6008 6009 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001040) 6010 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001040) 6011 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 6012 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 6013 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 6014 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 6015 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 6016 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 6017 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 6018 out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 6019 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 6020 do {\ 6021 HWIO_INTLOCK(); \ 6022 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 6023 HWIO_INTFREE();\ 6024 } while (0) 6025 6026 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 6027 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 6028 6029 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 6030 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 6031 6032 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 6033 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 6034 6035 //// Register TCL_R1_ASE_SM_STATES //// 6036 6037 #define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001044) 6038 #define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001044) 6039 #define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fffff 6040 #define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 6041 #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ 6042 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) 6043 #define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ 6044 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 6045 #define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ 6046 out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) 6047 #define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ 6048 do {\ 6049 HWIO_INTLOCK(); \ 6050 out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ 6051 HWIO_INTFREE();\ 6052 } while (0) 6053 6054 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 6055 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 6056 6057 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 6058 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 6059 6060 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 6061 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 6062 6063 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 6064 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 6065 6066 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 6067 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 6068 6069 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 6070 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 6071 6072 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 6073 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 6074 6075 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 6076 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 6077 6078 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 6079 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 6080 6081 //// Register TCL_R1_ASE_CACHE_DEBUG //// 6082 6083 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001048) 6084 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001048) 6085 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff 6086 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 6087 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ 6088 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) 6089 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ 6090 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 6091 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ 6092 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) 6093 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ 6094 do {\ 6095 HWIO_INTLOCK(); \ 6096 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ 6097 HWIO_INTFREE();\ 6098 } while (0) 6099 6100 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 6101 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 6102 6103 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// 6104 6105 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x0000104c) 6106 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x0000104c) 6107 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 6108 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 6109 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 6110 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) 6111 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 6112 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 6113 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 6114 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 6115 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 6116 do {\ 6117 HWIO_INTLOCK(); \ 6118 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 6119 HWIO_INTFREE();\ 6120 } while (0) 6121 6122 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 6123 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 6124 6125 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 6126 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 6127 6128 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 6129 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 6130 6131 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 6132 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 6133 6134 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// 6135 6136 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1050+0x4*n) 6137 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1050+0x4*n) 6138 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 6139 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 6140 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 6141 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 6142 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) 6143 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 6144 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 6145 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 6146 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 6147 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 6148 do {\ 6149 HWIO_INTLOCK(); \ 6150 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 6151 HWIO_INTFREE();\ 6152 } while (0) 6153 6154 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 6155 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 6156 6157 //// Register TCL_R1_FSE_END_OF_TEST_CHECK //// 6158 6159 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x) (x+0x000010d0) 6160 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_PHYS(x) (x+0x000010d0) 6161 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK 0x00000001 6162 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_SHFT 0 6163 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x) \ 6164 in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK) 6165 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask) \ 6166 in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) 6167 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val) \ 6168 out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val) 6169 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 6170 do {\ 6171 HWIO_INTLOCK(); \ 6172 out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \ 6173 HWIO_INTFREE();\ 6174 } while (0) 6175 6176 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 6177 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 6178 6179 //// Register TCL_R1_FSE_DEBUG_CLEAR_COUNTERS //// 6180 6181 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x000010d4) 6182 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x000010d4) 6183 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 6184 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_SHFT 0 6185 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x) \ 6186 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK) 6187 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 6188 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 6189 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 6190 out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 6191 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 6192 do {\ 6193 HWIO_INTLOCK(); \ 6194 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 6195 HWIO_INTFREE();\ 6196 } while (0) 6197 6198 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 6199 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 6200 6201 //// Register TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER //// 6202 6203 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x000010d8) 6204 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x000010d8) 6205 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 6206 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 6207 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 6208 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 6209 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 6210 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 6211 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 6212 out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 6213 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 6214 do {\ 6215 HWIO_INTLOCK(); \ 6216 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 6217 HWIO_INTFREE();\ 6218 } while (0) 6219 6220 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 6221 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 6222 6223 //// Register TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER //// 6224 6225 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x000010dc) 6226 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x000010dc) 6227 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 6228 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 6229 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 6230 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 6231 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 6232 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 6233 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 6234 out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 6235 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 6236 do {\ 6237 HWIO_INTLOCK(); \ 6238 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 6239 HWIO_INTFREE();\ 6240 } while (0) 6241 6242 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 6243 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 6244 6245 //// Register TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 6246 6247 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x000010e0) 6248 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x000010e0) 6249 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 6250 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 6251 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 6252 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 6253 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 6254 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 6255 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 6256 out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 6257 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 6258 do {\ 6259 HWIO_INTLOCK(); \ 6260 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 6261 HWIO_INTFREE();\ 6262 } while (0) 6263 6264 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 6265 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 6266 6267 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 6268 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 6269 6270 //// Register TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER //// 6271 6272 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x000010e4) 6273 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x000010e4) 6274 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 6275 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 6276 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 6277 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 6278 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 6279 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 6280 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 6281 out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 6282 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 6283 do {\ 6284 HWIO_INTLOCK(); \ 6285 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 6286 HWIO_INTFREE();\ 6287 } while (0) 6288 6289 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 6290 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 6291 6292 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 6293 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 6294 6295 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 6296 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 6297 6298 //// Register TCL_R1_FSE_SM_STATES //// 6299 6300 #define HWIO_TCL_R1_FSE_SM_STATES_ADDR(x) (x+0x000010e8) 6301 #define HWIO_TCL_R1_FSE_SM_STATES_PHYS(x) (x+0x000010e8) 6302 #define HWIO_TCL_R1_FSE_SM_STATES_RMSK 0x003fffff 6303 #define HWIO_TCL_R1_FSE_SM_STATES_SHFT 0 6304 #define HWIO_TCL_R1_FSE_SM_STATES_IN(x) \ 6305 in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK) 6306 #define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask) \ 6307 in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) 6308 #define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val) \ 6309 out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val) 6310 #define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val) \ 6311 do {\ 6312 HWIO_INTLOCK(); \ 6313 out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \ 6314 HWIO_INTFREE();\ 6315 } while (0) 6316 6317 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 6318 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 6319 6320 #define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 6321 #define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 6322 6323 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 6324 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 6325 6326 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 6327 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 6328 6329 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 6330 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 6331 6332 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 6333 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 6334 6335 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 6336 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 6337 6338 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 6339 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 6340 6341 #define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 6342 #define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 6343 6344 //// Register TCL_R1_FSE_CACHE_DEBUG //// 6345 6346 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x) (x+0x000010ec) 6347 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_PHYS(x) (x+0x000010ec) 6348 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK 0x000003ff 6349 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_SHFT 0 6350 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x) \ 6351 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK) 6352 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask) \ 6353 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) 6354 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val) \ 6355 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val) 6356 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val) \ 6357 do {\ 6358 HWIO_INTLOCK(); \ 6359 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \ 6360 HWIO_INTFREE();\ 6361 } while (0) 6362 6363 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 6364 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT 0x0 6365 6366 //// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS //// 6367 6368 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x000010f0) 6369 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x000010f0) 6370 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 6371 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 6372 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 6373 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK) 6374 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 6375 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 6376 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 6377 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 6378 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 6379 do {\ 6380 HWIO_INTLOCK(); \ 6381 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 6382 HWIO_INTFREE();\ 6383 } while (0) 6384 6385 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 6386 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 6387 6388 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 6389 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 6390 6391 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 6392 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 6393 6394 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 6395 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 6396 6397 //// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_n //// 6398 6399 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x10F4+0x4*n) 6400 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x10F4+0x4*n) 6401 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 6402 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_SHFT 0 6403 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_MAXn 31 6404 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 6405 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK) 6406 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 6407 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 6408 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 6409 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 6410 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 6411 do {\ 6412 HWIO_INTLOCK(); \ 6413 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 6414 HWIO_INTFREE();\ 6415 } while (0) 6416 6417 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 6418 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 6419 6420 //// Register TCL_R2_SW2TCL1_RING_HP //// 6421 6422 #define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) 6423 #define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) 6424 #define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x0000ffff 6425 #define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 6426 #define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ 6427 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) 6428 #define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ 6429 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 6430 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ 6431 out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) 6432 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ 6433 do {\ 6434 HWIO_INTLOCK(); \ 6435 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ 6436 HWIO_INTFREE();\ 6437 } while (0) 6438 6439 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6440 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6441 6442 //// Register TCL_R2_SW2TCL1_RING_TP //// 6443 6444 #define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) 6445 #define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) 6446 #define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x0000ffff 6447 #define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 6448 #define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ 6449 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) 6450 #define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ 6451 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 6452 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ 6453 out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) 6454 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ 6455 do {\ 6456 HWIO_INTLOCK(); \ 6457 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ 6458 HWIO_INTFREE();\ 6459 } while (0) 6460 6461 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6462 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6463 6464 //// Register TCL_R2_SW2TCL2_RING_HP //// 6465 6466 #define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) 6467 #define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) 6468 #define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x0000ffff 6469 #define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 6470 #define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ 6471 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) 6472 #define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ 6473 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 6474 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ 6475 out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) 6476 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ 6477 do {\ 6478 HWIO_INTLOCK(); \ 6479 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ 6480 HWIO_INTFREE();\ 6481 } while (0) 6482 6483 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6484 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 6485 6486 //// Register TCL_R2_SW2TCL2_RING_TP //// 6487 6488 #define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) 6489 #define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) 6490 #define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x0000ffff 6491 #define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 6492 #define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ 6493 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) 6494 #define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ 6495 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 6496 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ 6497 out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) 6498 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ 6499 do {\ 6500 HWIO_INTLOCK(); \ 6501 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ 6502 HWIO_INTFREE();\ 6503 } while (0) 6504 6505 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6506 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 6507 6508 //// Register TCL_R2_SW2TCL3_RING_HP //// 6509 6510 #define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) 6511 #define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) 6512 #define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x0000ffff 6513 #define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 6514 #define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ 6515 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) 6516 #define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ 6517 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 6518 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ 6519 out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) 6520 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ 6521 do {\ 6522 HWIO_INTLOCK(); \ 6523 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ 6524 HWIO_INTFREE();\ 6525 } while (0) 6526 6527 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6528 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 6529 6530 //// Register TCL_R2_SW2TCL3_RING_TP //// 6531 6532 #define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) 6533 #define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) 6534 #define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x0000ffff 6535 #define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 6536 #define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ 6537 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) 6538 #define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ 6539 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 6540 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ 6541 out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) 6542 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ 6543 do {\ 6544 HWIO_INTLOCK(); \ 6545 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ 6546 HWIO_INTFREE();\ 6547 } while (0) 6548 6549 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6550 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 6551 6552 //// Register TCL_R2_SW2TCL_CMD_RING_HP //// 6553 6554 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x) (x+0x00002018) 6555 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x) (x+0x00002018) 6556 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK 0x0000ffff 6557 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT 0 6558 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x) \ 6559 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK) 6560 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask) \ 6561 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) 6562 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val) \ 6563 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val) 6564 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val) \ 6565 do {\ 6566 HWIO_INTLOCK(); \ 6567 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \ 6568 HWIO_INTFREE();\ 6569 } while (0) 6570 6571 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6572 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT 0x0 6573 6574 //// Register TCL_R2_SW2TCL_CMD_RING_TP //// 6575 6576 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x) (x+0x0000201c) 6577 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x) (x+0x0000201c) 6578 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK 0x0000ffff 6579 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT 0 6580 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x) \ 6581 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK) 6582 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask) \ 6583 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) 6584 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val) \ 6585 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val) 6586 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val) \ 6587 do {\ 6588 HWIO_INTLOCK(); \ 6589 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \ 6590 HWIO_INTFREE();\ 6591 } while (0) 6592 6593 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6594 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT 0x0 6595 6596 //// Register TCL_R2_FW2TCL1_RING_HP //// 6597 6598 #define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) 6599 #define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) 6600 #define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff 6601 #define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 6602 #define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ 6603 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) 6604 #define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ 6605 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 6606 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ 6607 out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) 6608 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ 6609 do {\ 6610 HWIO_INTLOCK(); \ 6611 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ 6612 HWIO_INTFREE();\ 6613 } while (0) 6614 6615 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6616 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6617 6618 //// Register TCL_R2_FW2TCL1_RING_TP //// 6619 6620 #define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) 6621 #define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) 6622 #define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff 6623 #define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 6624 #define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ 6625 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) 6626 #define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ 6627 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 6628 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ 6629 out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) 6630 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ 6631 do {\ 6632 HWIO_INTLOCK(); \ 6633 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ 6634 HWIO_INTFREE();\ 6635 } while (0) 6636 6637 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6638 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6639 6640 //// Register TCL_R2_TCL2TQM_RING_HP //// 6641 6642 #define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) 6643 #define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) 6644 #define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff 6645 #define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 6646 #define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ 6647 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) 6648 #define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ 6649 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 6650 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ 6651 out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) 6652 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ 6653 do {\ 6654 HWIO_INTLOCK(); \ 6655 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ 6656 HWIO_INTFREE();\ 6657 } while (0) 6658 6659 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6660 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 6661 6662 //// Register TCL_R2_TCL2TQM_RING_TP //// 6663 6664 #define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) 6665 #define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) 6666 #define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff 6667 #define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 6668 #define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ 6669 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) 6670 #define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ 6671 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 6672 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ 6673 out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) 6674 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ 6675 do {\ 6676 HWIO_INTLOCK(); \ 6677 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ 6678 HWIO_INTFREE();\ 6679 } while (0) 6680 6681 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6682 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 6683 6684 //// Register TCL_R2_TCL_STATUS1_RING_HP //// 6685 6686 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) 6687 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) 6688 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff 6689 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 6690 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ 6691 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) 6692 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ 6693 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 6694 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ 6695 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) 6696 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ 6697 do {\ 6698 HWIO_INTLOCK(); \ 6699 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ 6700 HWIO_INTFREE();\ 6701 } while (0) 6702 6703 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6704 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 6705 6706 //// Register TCL_R2_TCL_STATUS1_RING_TP //// 6707 6708 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) 6709 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) 6710 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff 6711 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 6712 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ 6713 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) 6714 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ 6715 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 6716 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ 6717 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) 6718 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ 6719 do {\ 6720 HWIO_INTLOCK(); \ 6721 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ 6722 HWIO_INTFREE();\ 6723 } while (0) 6724 6725 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6726 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 6727 6728 //// Register TCL_R2_TCL_STATUS2_RING_HP //// 6729 6730 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) 6731 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) 6732 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff 6733 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 6734 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ 6735 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) 6736 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ 6737 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 6738 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ 6739 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) 6740 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ 6741 do {\ 6742 HWIO_INTLOCK(); \ 6743 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ 6744 HWIO_INTFREE();\ 6745 } while (0) 6746 6747 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6748 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 6749 6750 //// Register TCL_R2_TCL_STATUS2_RING_TP //// 6751 6752 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) 6753 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) 6754 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff 6755 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 6756 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ 6757 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) 6758 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ 6759 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 6760 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ 6761 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) 6762 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ 6763 do {\ 6764 HWIO_INTLOCK(); \ 6765 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ 6766 HWIO_INTFREE();\ 6767 } while (0) 6768 6769 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6770 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 6771 6772 //// Register TCL_R2_TCL2FW_RING_HP //// 6773 6774 #define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) 6775 #define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) 6776 #define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff 6777 #define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 6778 #define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ 6779 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) 6780 #define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ 6781 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 6782 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ 6783 out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) 6784 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ 6785 do {\ 6786 HWIO_INTLOCK(); \ 6787 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ 6788 HWIO_INTFREE();\ 6789 } while (0) 6790 6791 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6792 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 6793 6794 //// Register TCL_R2_TCL2FW_RING_TP //// 6795 6796 #define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) 6797 #define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) 6798 #define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff 6799 #define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 6800 #define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ 6801 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) 6802 #define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ 6803 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 6804 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ 6805 out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) 6806 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ 6807 do {\ 6808 HWIO_INTLOCK(); \ 6809 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ 6810 HWIO_INTFREE();\ 6811 } while (0) 6812 6813 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6814 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 6815 6816 6817 #endif 6818 6819