1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_FLUSH_CACHE_H_ 25 #define _REO_FLUSH_CACHE_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_reo_cmd_header.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct uniform_reo_cmd_header cmd_header; 35 // 1 flush_addr_31_0[31:0] 36 // 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15] 37 // 3 reserved_3a[31:0] 38 // 4 reserved_4a[31:0] 39 // 5 reserved_5a[31:0] 40 // 6 reserved_6a[31:0] 41 // 7 reserved_7a[31:0] 42 // 8 reserved_8a[31:0] 43 // 44 // ################ END SUMMARY ################# 45 46 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 47 48 struct reo_flush_cache { 49 struct uniform_reo_cmd_header cmd_header; 50 uint32_t flush_addr_31_0 : 32; //[31:0] 51 uint32_t flush_addr_39_32 : 8, //[7:0] 52 forward_all_mpdus_in_queue : 1, //[8] 53 release_cache_block_index : 1, //[9] 54 cache_block_resource_index : 2, //[11:10] 55 flush_without_invalidate : 1, //[12] 56 block_cache_usage_after_flush : 1, //[13] 57 flush_entire_cache : 1, //[14] 58 reserved_2b : 17; //[31:15] 59 uint32_t reserved_3a : 32; //[31:0] 60 uint32_t reserved_4a : 32; //[31:0] 61 uint32_t reserved_5a : 32; //[31:0] 62 uint32_t reserved_6a : 32; //[31:0] 63 uint32_t reserved_7a : 32; //[31:0] 64 uint32_t reserved_8a : 32; //[31:0] 65 }; 66 67 /* 68 69 struct uniform_reo_cmd_header cmd_header 70 71 Consumer: REO 72 73 Producer: SW 74 75 76 77 Details for command execution tracking purposes. 78 79 flush_addr_31_0 80 81 Consumer: REO 82 83 Producer: SW 84 85 86 87 Address (lower 32 bits) of the descriptor to flush 88 89 <legal all> 90 91 flush_addr_39_32 92 93 Consumer: REO 94 95 Producer: SW 96 97 98 99 Address (upper 8 bits) of the descriptor to flush 100 101 <legal all> 102 103 forward_all_mpdus_in_queue 104 105 Is only allowed to be set when the flush address 106 corresponds with a REO descriptor. 107 108 109 110 When set, REO shall first forward all the MPDUs held in 111 the indicated re-order queue, before flushing the descriptor 112 from the cache. 113 114 <legal all> 115 116 release_cache_block_index 117 118 Field not valid when Flush_entire_cache is set. 119 120 121 122 If SW has previously used a blocking resource that it 123 now wants to re-use for this command, this bit shall be set. 124 It prevents SW from having to send a separate 125 REO_UNBLOCK_CACHE command. 126 127 128 129 When set, HW will first release the blocking resource 130 (indicated in field 'Cache_block_resouce_index') before this 131 command gets executed. 132 133 If that resource was already unblocked, this will be 134 considered an error. This command will not be executed, and 135 an error shall be returned. 136 137 <legal all> 138 139 cache_block_resource_index 140 141 Field not valid when Flush_entire_cache is set. 142 143 144 145 Indicates which of the four blocking resources in REO 146 will be assigned for managing the blocking of this 147 (descriptor) address 148 149 <legal all> 150 151 flush_without_invalidate 152 153 Field not valid when Flush_entire_cache is set. 154 155 156 157 When set, REO shall flush the cache line contents from 158 the cache, but there is NO need to invalidate the cache line 159 entry... The contents in the cache can be maintained. This 160 feature can be used by SW (and DV) to get a current snapshot 161 of the contents in the cache 162 163 164 165 <legal all> 166 167 block_cache_usage_after_flush 168 169 Field not valid when Flush_entire_cache is set. 170 171 172 173 When set, REO shall block any cache accesses to this 174 address till explicitly unblocked. 175 176 177 178 Whenever SW sets this bit, SW shall also set bit 179 'Forward_all_mpdus_in_queue' to ensure all packets are 180 flushed out in order to make sure this queue desc is not in 181 one of the aging link lists. In case SW does not want to 182 flush the MPDUs in the queue, see the recipe description 183 below this TLV definition. 184 185 186 187 The 'blocking' index to be used for this is indicated in 188 field 'cache_block_resource_index'. If SW had previously 189 used this blocking resource and was not freed up yet, SW 190 shall first unblock that index (by setting bit 191 Release_cache_block_index) or use an unblock command. 192 193 194 195 If the resource indicated here was already blocked (and 196 did not get unblocked in this command), it is considered an 197 error scenario... 198 199 No flush shall happen. The status for this command shall 200 indicate error. 201 202 203 204 <legal all> 205 206 flush_entire_cache 207 208 When set, the entire cache shall be flushed. The entire 209 cache will also remain blocked, till the 210 'REO_UNBLOCK_COMMAND' is received with bit unblock type set 211 to unblock_cache. All other fields in this command are to be 212 ignored. 213 214 215 216 Note that flushing the entire cache has no changes to 217 the current settings of the blocking resource settings 218 219 220 221 <legal all> 222 223 reserved_2b 224 225 <legal 0> 226 227 reserved_3a 228 229 <legal 0> 230 231 reserved_4a 232 233 <legal 0> 234 235 reserved_5a 236 237 <legal 0> 238 239 reserved_6a 240 241 <legal 0> 242 243 reserved_7a 244 245 <legal 0> 246 247 reserved_8a 248 249 <legal 0> 250 */ 251 252 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000 253 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0 254 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff 255 256 /* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0 257 258 Consumer: REO 259 260 Producer: SW 261 262 263 264 Address (lower 32 bits) of the descriptor to flush 265 266 <legal all> 267 */ 268 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 269 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 270 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff 271 272 /* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32 273 274 Consumer: REO 275 276 Producer: SW 277 278 279 280 Address (upper 8 bits) of the descriptor to flush 281 282 <legal all> 283 */ 284 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 285 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 286 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff 287 288 /* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE 289 290 Is only allowed to be set when the flush address 291 corresponds with a REO descriptor. 292 293 294 295 When set, REO shall first forward all the MPDUs held in 296 the indicated re-order queue, before flushing the descriptor 297 from the cache. 298 299 <legal all> 300 */ 301 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 302 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 303 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 304 305 /* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX 306 307 Field not valid when Flush_entire_cache is set. 308 309 310 311 If SW has previously used a blocking resource that it 312 now wants to re-use for this command, this bit shall be set. 313 It prevents SW from having to send a separate 314 REO_UNBLOCK_CACHE command. 315 316 317 318 When set, HW will first release the blocking resource 319 (indicated in field 'Cache_block_resouce_index') before this 320 command gets executed. 321 322 If that resource was already unblocked, this will be 323 considered an error. This command will not be executed, and 324 an error shall be returned. 325 326 <legal all> 327 */ 328 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 329 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 330 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 331 332 /* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX 333 334 Field not valid when Flush_entire_cache is set. 335 336 337 338 Indicates which of the four blocking resources in REO 339 will be assigned for managing the blocking of this 340 (descriptor) address 341 342 <legal all> 343 */ 344 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 345 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 346 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 347 348 /* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE 349 350 Field not valid when Flush_entire_cache is set. 351 352 353 354 When set, REO shall flush the cache line contents from 355 the cache, but there is NO need to invalidate the cache line 356 entry... The contents in the cache can be maintained. This 357 feature can be used by SW (and DV) to get a current snapshot 358 of the contents in the cache 359 360 361 362 <legal all> 363 */ 364 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 365 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 366 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 367 368 /* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH 369 370 Field not valid when Flush_entire_cache is set. 371 372 373 374 When set, REO shall block any cache accesses to this 375 address till explicitly unblocked. 376 377 378 379 Whenever SW sets this bit, SW shall also set bit 380 'Forward_all_mpdus_in_queue' to ensure all packets are 381 flushed out in order to make sure this queue desc is not in 382 one of the aging link lists. In case SW does not want to 383 flush the MPDUs in the queue, see the recipe description 384 below this TLV definition. 385 386 387 388 The 'blocking' index to be used for this is indicated in 389 field 'cache_block_resource_index'. If SW had previously 390 used this blocking resource and was not freed up yet, SW 391 shall first unblock that index (by setting bit 392 Release_cache_block_index) or use an unblock command. 393 394 395 396 If the resource indicated here was already blocked (and 397 did not get unblocked in this command), it is considered an 398 error scenario... 399 400 No flush shall happen. The status for this command shall 401 indicate error. 402 403 404 405 <legal all> 406 */ 407 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 408 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 409 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 410 411 /* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE 412 413 When set, the entire cache shall be flushed. The entire 414 cache will also remain blocked, till the 415 'REO_UNBLOCK_COMMAND' is received with bit unblock type set 416 to unblock_cache. All other fields in this command are to be 417 ignored. 418 419 420 421 Note that flushing the entire cache has no changes to 422 the current settings of the blocking resource settings 423 424 425 426 <legal all> 427 */ 428 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 429 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 430 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 431 432 /* Description REO_FLUSH_CACHE_2_RESERVED_2B 433 434 <legal 0> 435 */ 436 #define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 437 #define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 438 #define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 439 440 /* Description REO_FLUSH_CACHE_3_RESERVED_3A 441 442 <legal 0> 443 */ 444 #define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c 445 #define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 446 #define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff 447 448 /* Description REO_FLUSH_CACHE_4_RESERVED_4A 449 450 <legal 0> 451 */ 452 #define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 453 #define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 454 #define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff 455 456 /* Description REO_FLUSH_CACHE_5_RESERVED_5A 457 458 <legal 0> 459 */ 460 #define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 461 #define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 462 #define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff 463 464 /* Description REO_FLUSH_CACHE_6_RESERVED_6A 465 466 <legal 0> 467 */ 468 #define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 469 #define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 470 #define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff 471 472 /* Description REO_FLUSH_CACHE_7_RESERVED_7A 473 474 <legal 0> 475 */ 476 #define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c 477 #define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 478 #define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff 479 480 /* Description REO_FLUSH_CACHE_8_RESERVED_8A 481 482 <legal 0> 483 */ 484 #define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 485 #define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 486 #define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff 487 488 489 #endif // _REO_FLUSH_CACHE_H_ 490