1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // $ATH_LICENSE_HW_HDR_C$ 20 // 21 // DO NOT EDIT! This file is automatically generated 22 // These definitions are tied to a particular hardware layout 23 24 25 #ifndef _RX_MPDU_END_H_ 26 #define _RX_MPDU_END_H_ 27 #if !defined(__ASSEMBLER__) 28 #endif 29 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 35 // 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] 36 // 37 // ################ END SUMMARY ################# 38 39 #define NUM_OF_DWORDS_RX_MPDU_END 2 40 41 struct rx_mpdu_end { 42 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 43 sw_frame_group_id : 7, //[8:2] 44 reserved_0 : 7, //[15:9] 45 phy_ppdu_id : 16; //[31:16] 46 uint32_t reserved_1a : 11, //[10:0] 47 unsup_ktype_short_frame : 1, //[11] 48 rx_in_tx_decrypt_byp : 1, //[12] 49 overflow_err : 1, //[13] 50 mpdu_length_err : 1, //[14] 51 tkip_mic_err : 1, //[15] 52 decrypt_err : 1, //[16] 53 unencrypted_frame_err : 1, //[17] 54 pn_fields_contain_valid_info : 1, //[18] 55 fcs_err : 1, //[19] 56 msdu_length_err : 1, //[20] 57 rxdma0_destination_ring : 2, //[22:21] 58 rxdma1_destination_ring : 2, //[24:23] 59 decrypt_status_code : 3, //[27:25] 60 rx_bitmap_not_updated : 1, //[28] 61 reserved_1b : 3; //[31:29] 62 }; 63 64 /* 65 66 rxpcu_mpdu_filter_in_category 67 68 Field indicates what the reason was that this MPDU frame 69 was allowed to come into the receive path by RXPCU 70 71 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 72 frame filter programming of rxpcu 73 74 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 75 regular frame filter and would have been dropped, were it 76 not for the frame fitting into the 'monitor_client' 77 category. 78 79 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 80 regular frame filter and also did not pass the 81 rxpcu_monitor_client filter. It would have been dropped 82 accept that it did pass the 'monitor_other' category. 83 84 <legal 0-2> 85 86 sw_frame_group_id 87 88 SW processes frames based on certain classifications. 89 This field indicates to what sw classification this MPDU is 90 mapped. 91 92 The classification is given in priority order 93 94 95 96 <enum 0 sw_frame_group_NDP_frame> 97 98 99 100 <enum 1 sw_frame_group_Multicast_data> 101 102 <enum 2 sw_frame_group_Unicast_data> 103 104 <enum 3 sw_frame_group_Null_data > This includes mpdus 105 of type Data Null as well as QoS Data Null 106 107 108 109 <enum 4 sw_frame_group_mgmt_0000 > 110 111 <enum 5 sw_frame_group_mgmt_0001 > 112 113 <enum 6 sw_frame_group_mgmt_0010 > 114 115 <enum 7 sw_frame_group_mgmt_0011 > 116 117 <enum 8 sw_frame_group_mgmt_0100 > 118 119 <enum 9 sw_frame_group_mgmt_0101 > 120 121 <enum 10 sw_frame_group_mgmt_0110 > 122 123 <enum 11 sw_frame_group_mgmt_0111 > 124 125 <enum 12 sw_frame_group_mgmt_1000 > 126 127 <enum 13 sw_frame_group_mgmt_1001 > 128 129 <enum 14 sw_frame_group_mgmt_1010 > 130 131 <enum 15 sw_frame_group_mgmt_1011 > 132 133 <enum 16 sw_frame_group_mgmt_1100 > 134 135 <enum 17 sw_frame_group_mgmt_1101 > 136 137 <enum 18 sw_frame_group_mgmt_1110 > 138 139 <enum 19 sw_frame_group_mgmt_1111 > 140 141 142 143 <enum 20 sw_frame_group_ctrl_0000 > 144 145 <enum 21 sw_frame_group_ctrl_0001 > 146 147 <enum 22 sw_frame_group_ctrl_0010 > 148 149 <enum 23 sw_frame_group_ctrl_0011 > 150 151 <enum 24 sw_frame_group_ctrl_0100 > 152 153 <enum 25 sw_frame_group_ctrl_0101 > 154 155 <enum 26 sw_frame_group_ctrl_0110 > 156 157 <enum 27 sw_frame_group_ctrl_0111 > 158 159 <enum 28 sw_frame_group_ctrl_1000 > 160 161 <enum 29 sw_frame_group_ctrl_1001 > 162 163 <enum 30 sw_frame_group_ctrl_1010 > 164 165 <enum 31 sw_frame_group_ctrl_1011 > 166 167 <enum 32 sw_frame_group_ctrl_1100 > 168 169 <enum 33 sw_frame_group_ctrl_1101 > 170 171 <enum 34 sw_frame_group_ctrl_1110 > 172 173 <enum 35 sw_frame_group_ctrl_1111 > 174 175 176 177 <enum 36 sw_frame_group_unsupported> This covers type 3 178 and protocol version != 0 179 180 181 182 183 184 185 <legal 0-37> 186 187 reserved_0 188 189 <legal 0> 190 191 phy_ppdu_id 192 193 A ppdu counter value that PHY increments for every PPDU 194 received. The counter value wraps around 195 196 <legal all> 197 198 reserved_1a 199 200 <legal 0> 201 202 unsup_ktype_short_frame 203 204 This bit will be '1' when WEP or TKIP or WAPI key type 205 is received for 11ah short frame. Crypto will bypass the 206 received packet without decryption to RxOLE after setting 207 this bit. 208 209 rx_in_tx_decrypt_byp 210 211 Indicates that RX packet is not decrypted as Crypto is 212 busy with TX packet processing. 213 214 overflow_err 215 216 RXPCU Receive FIFO ran out of space to receive the full 217 MPDU. Therefor this MPDU is terminated early and is thus 218 corrupted. 219 220 221 222 This MPDU will not be ACKed. 223 224 RXPCU might still be able to correctly receive the 225 following MPDUs in the PPDU if enough fifo space became 226 available in time 227 228 mpdu_length_err 229 230 Set by RXPCU if the expected MPDU length does not 231 correspond with the actually received number of bytes in the 232 MPDU. 233 234 tkip_mic_err 235 236 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 237 for this MPDU 238 239 decrypt_err 240 241 Set by RX CRYPTO when CRYPTO detected a decrypt error 242 for this MPDU or CRYPTO received an encrypted frame, but did 243 not get a valid corresponding key id in the peer entry. 244 245 unencrypted_frame_err 246 247 Set by RX CRYPTO when CRYPTO detected an unencrypted 248 frame while in the peer entry field 249 'All_frames_shall_be_encrypted' is set. 250 251 pn_fields_contain_valid_info 252 253 Set by RX CRYPTO to indicate that there is a valid PN 254 field present in this MPDU 255 256 fcs_err 257 258 Set by RXPCU when there is an FCS error detected for 259 this MPDU 260 261 msdu_length_err 262 263 Set by RXOLE when there is an msdu length error detected 264 in at least 1 of the MSDUs embedded within the MPDU 265 266 rxdma0_destination_ring 267 268 The ring to which RXDMA0 shall push the frame, assuming 269 no MPDU level errors are detected. In case of MPDU level 270 errors, RXDMA0 might change the RXDMA0 destination 271 272 273 274 <enum 0 rxdma_release_ring > RXDMA0 shall push the 275 frame to the Release ring. Effectively this means the frame 276 needs to be dropped. 277 278 279 280 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 281 the FW ring 282 283 284 285 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 286 the SW ring 287 288 289 290 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 291 to the REO entrance ring 292 293 294 295 <legal all> 296 297 rxdma1_destination_ring 298 299 The ring to which RXDMA1 shall push the frame, assuming 300 no MPDU level errors are detected. In case of MPDU level 301 errors, RXDMA1 might change the RXDMA destination 302 303 304 305 <enum 0 rxdma_release_ring > RXDMA1 shall push the 306 frame to the Release ring. Effectively this means the frame 307 needs to be dropped. 308 309 310 311 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 312 the FW ring 313 314 315 316 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 317 the SW ring 318 319 320 321 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 322 to the REO entrance ring 323 324 325 326 <legal all> 327 328 decrypt_status_code 329 330 Field provides insight into the decryption performed 331 332 333 334 <enum 0 decrypt_ok> Frame had protection enabled and 335 decrypted properly 336 337 <enum 1 decrypt_unprotected_frame > Frame is unprotected 338 and hence bypassed 339 340 <enum 2 decrypt_data_err > Frame has protection enabled 341 and could not be properly decrypted due to MIC/ICV mismatch 342 etc. 343 344 <enum 3 decrypt_key_invalid > Frame has protection 345 enabled but the key that was required to decrypt this frame 346 was not valid 347 348 <enum 4 decrypt_peer_entry_invalid > Frame has 349 protection enabled but the key that was required to decrypt 350 this frame was not valid 351 352 <enum 5 decrypt_other > Reserved for other indications 353 354 355 356 <legal 0 - 5> 357 358 rx_bitmap_not_updated 359 360 Frame is received, but RXPCU could not update the 361 receive bitmap due to (temporary) fifo contraints. 362 363 <legal all> 364 365 reserved_1b 366 367 <legal 0> 368 */ 369 370 371 /* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 372 373 Field indicates what the reason was that this MPDU frame 374 was allowed to come into the receive path by RXPCU 375 376 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 377 frame filter programming of rxpcu 378 379 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 380 regular frame filter and would have been dropped, were it 381 not for the frame fitting into the 'monitor_client' 382 category. 383 384 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 385 regular frame filter and also did not pass the 386 rxpcu_monitor_client filter. It would have been dropped 387 accept that it did pass the 'monitor_other' category. 388 389 <legal 0-2> 390 */ 391 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 392 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 393 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 394 395 /* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID 396 397 SW processes frames based on certain classifications. 398 This field indicates to what sw classification this MPDU is 399 mapped. 400 401 The classification is given in priority order 402 403 404 405 <enum 0 sw_frame_group_NDP_frame> 406 407 408 409 <enum 1 sw_frame_group_Multicast_data> 410 411 <enum 2 sw_frame_group_Unicast_data> 412 413 <enum 3 sw_frame_group_Null_data > This includes mpdus 414 of type Data Null as well as QoS Data Null 415 416 417 418 <enum 4 sw_frame_group_mgmt_0000 > 419 420 <enum 5 sw_frame_group_mgmt_0001 > 421 422 <enum 6 sw_frame_group_mgmt_0010 > 423 424 <enum 7 sw_frame_group_mgmt_0011 > 425 426 <enum 8 sw_frame_group_mgmt_0100 > 427 428 <enum 9 sw_frame_group_mgmt_0101 > 429 430 <enum 10 sw_frame_group_mgmt_0110 > 431 432 <enum 11 sw_frame_group_mgmt_0111 > 433 434 <enum 12 sw_frame_group_mgmt_1000 > 435 436 <enum 13 sw_frame_group_mgmt_1001 > 437 438 <enum 14 sw_frame_group_mgmt_1010 > 439 440 <enum 15 sw_frame_group_mgmt_1011 > 441 442 <enum 16 sw_frame_group_mgmt_1100 > 443 444 <enum 17 sw_frame_group_mgmt_1101 > 445 446 <enum 18 sw_frame_group_mgmt_1110 > 447 448 <enum 19 sw_frame_group_mgmt_1111 > 449 450 451 452 <enum 20 sw_frame_group_ctrl_0000 > 453 454 <enum 21 sw_frame_group_ctrl_0001 > 455 456 <enum 22 sw_frame_group_ctrl_0010 > 457 458 <enum 23 sw_frame_group_ctrl_0011 > 459 460 <enum 24 sw_frame_group_ctrl_0100 > 461 462 <enum 25 sw_frame_group_ctrl_0101 > 463 464 <enum 26 sw_frame_group_ctrl_0110 > 465 466 <enum 27 sw_frame_group_ctrl_0111 > 467 468 <enum 28 sw_frame_group_ctrl_1000 > 469 470 <enum 29 sw_frame_group_ctrl_1001 > 471 472 <enum 30 sw_frame_group_ctrl_1010 > 473 474 <enum 31 sw_frame_group_ctrl_1011 > 475 476 <enum 32 sw_frame_group_ctrl_1100 > 477 478 <enum 33 sw_frame_group_ctrl_1101 > 479 480 <enum 34 sw_frame_group_ctrl_1110 > 481 482 <enum 35 sw_frame_group_ctrl_1111 > 483 484 485 486 <enum 36 sw_frame_group_unsupported> This covers type 3 487 and protocol version != 0 488 489 490 491 492 493 494 <legal 0-37> 495 */ 496 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 497 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 498 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 499 500 /* Description RX_MPDU_END_0_RESERVED_0 501 502 <legal 0> 503 */ 504 #define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 505 #define RX_MPDU_END_0_RESERVED_0_LSB 9 506 #define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 507 508 /* Description RX_MPDU_END_0_PHY_PPDU_ID 509 510 A ppdu counter value that PHY increments for every PPDU 511 received. The counter value wraps around 512 513 <legal all> 514 */ 515 #define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 516 #define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 517 #define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 518 519 /* Description RX_MPDU_END_1_RESERVED_1A 520 521 <legal 0> 522 */ 523 #define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 524 #define RX_MPDU_END_1_RESERVED_1A_LSB 0 525 #define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff 526 527 /* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME 528 529 This bit will be '1' when WEP or TKIP or WAPI key type 530 is received for 11ah short frame. Crypto will bypass the 531 received packet without decryption to RxOLE after setting 532 this bit. 533 */ 534 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 535 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 536 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 537 538 /* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP 539 540 Indicates that RX packet is not decrypted as Crypto is 541 busy with TX packet processing. 542 */ 543 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 544 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 545 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 546 547 /* Description RX_MPDU_END_1_OVERFLOW_ERR 548 549 RXPCU Receive FIFO ran out of space to receive the full 550 MPDU. Therefor this MPDU is terminated early and is thus 551 corrupted. 552 553 554 555 This MPDU will not be ACKed. 556 557 RXPCU might still be able to correctly receive the 558 following MPDUs in the PPDU if enough fifo space became 559 available in time 560 */ 561 #define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 562 #define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 563 #define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 564 565 /* Description RX_MPDU_END_1_MPDU_LENGTH_ERR 566 567 Set by RXPCU if the expected MPDU length does not 568 correspond with the actually received number of bytes in the 569 MPDU. 570 */ 571 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 572 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 573 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 574 575 /* Description RX_MPDU_END_1_TKIP_MIC_ERR 576 577 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 578 for this MPDU 579 */ 580 #define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 581 #define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 582 #define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 583 584 /* Description RX_MPDU_END_1_DECRYPT_ERR 585 586 Set by RX CRYPTO when CRYPTO detected a decrypt error 587 for this MPDU or CRYPTO received an encrypted frame, but did 588 not get a valid corresponding key id in the peer entry. 589 */ 590 #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 591 #define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 592 #define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 593 594 /* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR 595 596 Set by RX CRYPTO when CRYPTO detected an unencrypted 597 frame while in the peer entry field 598 'All_frames_shall_be_encrypted' is set. 599 */ 600 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 601 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 602 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 603 604 /* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO 605 606 Set by RX CRYPTO to indicate that there is a valid PN 607 field present in this MPDU 608 */ 609 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 610 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 611 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 612 613 /* Description RX_MPDU_END_1_FCS_ERR 614 615 Set by RXPCU when there is an FCS error detected for 616 this MPDU 617 */ 618 #define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 619 #define RX_MPDU_END_1_FCS_ERR_LSB 19 620 #define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 621 622 /* Description RX_MPDU_END_1_MSDU_LENGTH_ERR 623 624 Set by RXOLE when there is an msdu length error detected 625 in at least 1 of the MSDUs embedded within the MPDU 626 */ 627 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 628 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 629 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 630 631 /* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING 632 633 The ring to which RXDMA0 shall push the frame, assuming 634 no MPDU level errors are detected. In case of MPDU level 635 errors, RXDMA0 might change the RXDMA0 destination 636 637 638 639 <enum 0 rxdma_release_ring > RXDMA0 shall push the 640 frame to the Release ring. Effectively this means the frame 641 needs to be dropped. 642 643 644 645 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 646 the FW ring 647 648 649 650 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 651 the SW ring 652 653 654 655 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 656 to the REO entrance ring 657 658 659 660 <legal all> 661 */ 662 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 663 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 664 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 665 666 /* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING 667 668 The ring to which RXDMA1 shall push the frame, assuming 669 no MPDU level errors are detected. In case of MPDU level 670 errors, RXDMA1 might change the RXDMA destination 671 672 673 674 <enum 0 rxdma_release_ring > RXDMA1 shall push the 675 frame to the Release ring. Effectively this means the frame 676 needs to be dropped. 677 678 679 680 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 681 the FW ring 682 683 684 685 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 686 the SW ring 687 688 689 690 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 691 to the REO entrance ring 692 693 694 695 <legal all> 696 */ 697 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 698 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 699 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 700 701 /* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE 702 703 Field provides insight into the decryption performed 704 705 706 707 <enum 0 decrypt_ok> Frame had protection enabled and 708 decrypted properly 709 710 <enum 1 decrypt_unprotected_frame > Frame is unprotected 711 and hence bypassed 712 713 <enum 2 decrypt_data_err > Frame has protection enabled 714 and could not be properly decrypted due to MIC/ICV mismatch 715 etc. 716 717 <enum 3 decrypt_key_invalid > Frame has protection 718 enabled but the key that was required to decrypt this frame 719 was not valid 720 721 <enum 4 decrypt_peer_entry_invalid > Frame has 722 protection enabled but the key that was required to decrypt 723 this frame was not valid 724 725 <enum 5 decrypt_other > Reserved for other indications 726 727 728 729 <legal 0 - 5> 730 */ 731 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 732 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 733 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 734 735 /* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED 736 737 Frame is received, but RXPCU could not update the 738 receive bitmap due to (temporary) fifo contraints. 739 740 <legal all> 741 */ 742 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 743 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 744 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 745 746 /* Description RX_MPDU_END_1_RESERVED_1B 747 748 <legal 0> 749 */ 750 #define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 751 #define RX_MPDU_END_1_RESERVED_1B_LSB 29 752 #define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 753 754 755 #endif // _RX_MPDU_END_H_ 756