1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // $ATH_LICENSE_HW_HDR_C$ 20 // 21 // DO NOT EDIT! This file is automatically generated 22 // These definitions are tied to a particular hardware layout 23 24 25 #ifndef _RX_MPDU_INFO_H_ 26 #define _RX_MPDU_INFO_H_ 27 #if !defined(__ASSEMBLER__) 28 #endif 29 30 #include "rxpt_classify_info.h" 31 32 // ################ START SUMMARY ################# 33 // 34 // Dword Fields 35 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16] 36 // 1 ast_index[15:0], sw_peer_id[31:16] 37 // 2 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], reserved_2a[15:10], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] 38 // 3 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], mesh_sta[6], bssid_hit[7], bssid_number[11:8], tid[15:12], reserved_3a[31:16] 39 // 4 pn_31_0[31:0] 40 // 5 pn_63_32[31:0] 41 // 6 pn_95_64[31:0] 42 // 7 pn_127_96[31:0] 43 // 8 peer_meta_data[31:0] 44 // 9 struct rxpt_classify_info rxpt_classify_info_details; 45 // 10 rx_reo_queue_desc_addr_31_0[31:0] 46 // 11 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26] 47 // 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30] 48 // 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], reserved_13[31:30] 49 // 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] 50 // 15 mac_addr_ad1_31_0[31:0] 51 // 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] 52 // 17 mac_addr_ad2_47_16[31:0] 53 // 18 mac_addr_ad3_31_0[31:0] 54 // 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] 55 // 20 mac_addr_ad4_31_0[31:0] 56 // 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] 57 // 22 mpdu_ht_control_field[31:0] 58 // 59 // ################ END SUMMARY ################# 60 61 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 62 63 struct rx_mpdu_info { 64 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 65 sw_frame_group_id : 7, //[8:2] 66 ndp_frame : 1, //[9] 67 phy_err : 1, //[10] 68 phy_err_during_mpdu_header : 1, //[11] 69 protocol_version_err : 1, //[12] 70 ast_based_lookup_valid : 1, //[13] 71 reserved_0a : 2, //[15:14] 72 phy_ppdu_id : 16; //[31:16] 73 uint32_t ast_index : 16, //[15:0] 74 sw_peer_id : 16; //[31:16] 75 uint32_t mpdu_frame_control_valid : 1, //[0] 76 mpdu_duration_valid : 1, //[1] 77 mac_addr_ad1_valid : 1, //[2] 78 mac_addr_ad2_valid : 1, //[3] 79 mac_addr_ad3_valid : 1, //[4] 80 mac_addr_ad4_valid : 1, //[5] 81 mpdu_sequence_control_valid : 1, //[6] 82 mpdu_qos_control_valid : 1, //[7] 83 mpdu_ht_control_valid : 1, //[8] 84 frame_encryption_info_valid : 1, //[9] 85 reserved_2a : 6, //[15:10] 86 fr_ds : 1, //[16] 87 to_ds : 1, //[17] 88 encrypted : 1, //[18] 89 mpdu_retry : 1, //[19] 90 mpdu_sequence_number : 12; //[31:20] 91 uint32_t epd_en : 1, //[0] 92 all_frames_shall_be_encrypted : 1, //[1] 93 encrypt_type : 4, //[5:2] 94 mesh_sta : 1, //[6] 95 bssid_hit : 1, //[7] 96 bssid_number : 4, //[11:8] 97 tid : 4, //[15:12] 98 reserved_3a : 16; //[31:16] 99 uint32_t pn_31_0 : 32; //[31:0] 100 uint32_t pn_63_32 : 32; //[31:0] 101 uint32_t pn_95_64 : 32; //[31:0] 102 uint32_t pn_127_96 : 32; //[31:0] 103 uint32_t peer_meta_data : 32; //[31:0] 104 struct rxpt_classify_info rxpt_classify_info_details; 105 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 106 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 107 receive_queue_number : 16, //[23:8] 108 pre_delim_err_warning : 1, //[24] 109 first_delim_err : 1, //[25] 110 reserved_11 : 6; //[31:26] 111 uint32_t key_id_octet : 8, //[7:0] 112 new_peer_entry : 1, //[8] 113 decrypt_needed : 1, //[9] 114 decap_type : 2, //[11:10] 115 rx_insert_vlan_c_tag_padding : 1, //[12] 116 rx_insert_vlan_s_tag_padding : 1, //[13] 117 strip_vlan_c_tag_decap : 1, //[14] 118 strip_vlan_s_tag_decap : 1, //[15] 119 pre_delim_count : 12, //[27:16] 120 ampdu_flag : 1, //[28] 121 bar_frame : 1, //[29] 122 reserved_12 : 2; //[31:30] 123 uint32_t mpdu_length : 14, //[13:0] 124 first_mpdu : 1, //[14] 125 mcast_bcast : 1, //[15] 126 ast_index_not_found : 1, //[16] 127 ast_index_timeout : 1, //[17] 128 power_mgmt : 1, //[18] 129 non_qos : 1, //[19] 130 null_data : 1, //[20] 131 mgmt_type : 1, //[21] 132 ctrl_type : 1, //[22] 133 more_data : 1, //[23] 134 eosp : 1, //[24] 135 fragment_flag : 1, //[25] 136 order : 1, //[26] 137 u_apsd_trigger : 1, //[27] 138 encrypt_required : 1, //[28] 139 directed : 1, //[29] 140 reserved_13 : 2; //[31:30] 141 uint32_t mpdu_frame_control_field : 16, //[15:0] 142 mpdu_duration_field : 16; //[31:16] 143 uint32_t mac_addr_ad1_31_0 : 32; //[31:0] 144 uint32_t mac_addr_ad1_47_32 : 16, //[15:0] 145 mac_addr_ad2_15_0 : 16; //[31:16] 146 uint32_t mac_addr_ad2_47_16 : 32; //[31:0] 147 uint32_t mac_addr_ad3_31_0 : 32; //[31:0] 148 uint32_t mac_addr_ad3_47_32 : 16, //[15:0] 149 mpdu_sequence_control_field : 16; //[31:16] 150 uint32_t mac_addr_ad4_31_0 : 32; //[31:0] 151 uint32_t mac_addr_ad4_47_32 : 16, //[15:0] 152 mpdu_qos_control_field : 16; //[31:16] 153 uint32_t mpdu_ht_control_field : 32; //[31:0] 154 }; 155 156 /* 157 158 rxpcu_mpdu_filter_in_category 159 160 Field indicates what the reason was that this MPDU frame 161 was allowed to come into the receive path by RXPCU 162 163 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 164 frame filter programming of rxpcu 165 166 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 167 regular frame filter and would have been dropped, were it 168 not for the frame fitting into the 'monitor_client' 169 category. 170 171 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 172 regular frame filter and also did not pass the 173 rxpcu_monitor_client filter. It would have been dropped 174 accept that it did pass the 'monitor_other' category. 175 176 177 178 Note: for ndp frame, if it was expected because the 179 preceding NDPA was filter_pass, the setting 180 rxpcu_filter_pass will be used. This setting will also be 181 used for every ndp frame in case Promiscuous mode is 182 enabled. 183 184 185 186 In case promiscuous is not enabled, and an NDP is not 187 preceded by a NPDA filter pass frame, the only other setting 188 that could appear here for the NDP is rxpcu_monitor_other. 189 190 (rxpcu has a configuration bit specifically for this 191 scenario) 192 193 194 195 Note: for 196 197 <legal 0-2> 198 199 sw_frame_group_id 200 201 SW processes frames based on certain classifications. 202 This field indicates to what sw classification this MPDU is 203 mapped. 204 205 The classification is given in priority order 206 207 208 209 <enum 0 sw_frame_group_NDP_frame> Note: The 210 corresponding Rxpcu_Mpdu_filter_in_category can be 211 rxpcu_filter_pass or rxpcu_monitor_other 212 213 214 215 <enum 1 sw_frame_group_Multicast_data> 216 217 <enum 2 sw_frame_group_Unicast_data> 218 219 <enum 3 sw_frame_group_Null_data > This includes mpdus 220 of type Data Null as well as QoS Data Null 221 222 223 224 <enum 4 sw_frame_group_mgmt_0000 > 225 226 <enum 5 sw_frame_group_mgmt_0001 > 227 228 <enum 6 sw_frame_group_mgmt_0010 > 229 230 <enum 7 sw_frame_group_mgmt_0011 > 231 232 <enum 8 sw_frame_group_mgmt_0100 > 233 234 <enum 9 sw_frame_group_mgmt_0101 > 235 236 <enum 10 sw_frame_group_mgmt_0110 > 237 238 <enum 11 sw_frame_group_mgmt_0111 > 239 240 <enum 12 sw_frame_group_mgmt_1000 > 241 242 <enum 13 sw_frame_group_mgmt_1001 > 243 244 <enum 14 sw_frame_group_mgmt_1010 > 245 246 <enum 15 sw_frame_group_mgmt_1011 > 247 248 <enum 16 sw_frame_group_mgmt_1100 > 249 250 <enum 17 sw_frame_group_mgmt_1101 > 251 252 <enum 18 sw_frame_group_mgmt_1110 > 253 254 <enum 19 sw_frame_group_mgmt_1111 > 255 256 257 258 <enum 20 sw_frame_group_ctrl_0000 > 259 260 <enum 21 sw_frame_group_ctrl_0001 > 261 262 <enum 22 sw_frame_group_ctrl_0010 > 263 264 <enum 23 sw_frame_group_ctrl_0011 > 265 266 <enum 24 sw_frame_group_ctrl_0100 > 267 268 <enum 25 sw_frame_group_ctrl_0101 > 269 270 <enum 26 sw_frame_group_ctrl_0110 > 271 272 <enum 27 sw_frame_group_ctrl_0111 > 273 274 <enum 28 sw_frame_group_ctrl_1000 > 275 276 <enum 29 sw_frame_group_ctrl_1001 > 277 278 <enum 30 sw_frame_group_ctrl_1010 > 279 280 <enum 31 sw_frame_group_ctrl_1011 > 281 282 <enum 32 sw_frame_group_ctrl_1100 > 283 284 <enum 33 sw_frame_group_ctrl_1101 > 285 286 <enum 34 sw_frame_group_ctrl_1110 > 287 288 <enum 35 sw_frame_group_ctrl_1111 > 289 290 291 292 <enum 36 sw_frame_group_unsupported> This covers type 3 293 and protocol version != 0 294 295 Note: The corresponding Rxpcu_Mpdu_filter_in_category 296 can only be rxpcu_monitor_other 297 298 299 300 301 Note: The corresponding Rxpcu_Mpdu_filter_in_category 302 can be rxpcu_filter_pass 303 304 305 306 <legal 0-37> 307 308 ndp_frame 309 310 When set, the received frame was an NDP frame, and thus 311 there will be no MPDU data. 312 313 <legal all> 314 315 phy_err 316 317 When set, a PHY error was received before MAC received 318 any data, and thus there will be no MPDU data. 319 320 <legal all> 321 322 phy_err_during_mpdu_header 323 324 When set, a PHY error was received before MAC received 325 the complete MPDU header which was needed for proper 326 decoding 327 328 <legal all> 329 330 protocol_version_err 331 332 Set when RXPCU detected a version error in the Frame 333 control field 334 335 <legal all> 336 337 ast_based_lookup_valid 338 339 When set, AST based lookup for this frame has found a 340 valid result. 341 342 343 344 Note that for NDP frame this will never be set 345 346 <legal all> 347 348 reserved_0a 349 350 <legal 0> 351 352 phy_ppdu_id 353 354 A ppdu counter value that PHY increments for every PPDU 355 received. The counter value wraps around 356 357 <legal all> 358 359 ast_index 360 361 This field indicates the index of the AST entry 362 corresponding to this MPDU. It is provided by the GSE module 363 instantiated in RXPCU. 364 365 A value of 0xFFFF indicates an invalid AST index, 366 meaning that No AST entry was found or NO AST search was 367 performed 368 369 370 371 In case of ndp or phy_err, this field will be set to 372 0xFFFF 373 374 <legal all> 375 376 sw_peer_id 377 378 In case of ndp or phy_err or AST_based_lookup_valid == 379 0, this field will be set to 0 380 381 382 383 This field indicates a unique peer identifier. It is set 384 equal to field 'sw_peer_id' from the AST entry 385 386 387 388 <legal all> 389 390 mpdu_frame_control_valid 391 392 When set, the field Mpdu_Frame_control_field has valid 393 information 394 395 396 397 398 <legal all> 399 400 mpdu_duration_valid 401 402 When set, the field Mpdu_duration_field has valid 403 information 404 405 406 407 408 <legal all> 409 410 mac_addr_ad1_valid 411 412 When set, the fields mac_addr_ad1_..... have valid 413 information 414 415 416 417 418 <legal all> 419 420 mac_addr_ad2_valid 421 422 When set, the fields mac_addr_ad2_..... have valid 423 information 424 425 426 427 428 429 430 431 <legal all> 432 433 mac_addr_ad3_valid 434 435 When set, the fields mac_addr_ad3_..... have valid 436 information 437 438 439 440 441 442 443 444 <legal all> 445 446 mac_addr_ad4_valid 447 448 When set, the fields mac_addr_ad4_..... have valid 449 information 450 451 452 453 454 455 456 457 <legal all> 458 459 mpdu_sequence_control_valid 460 461 When set, the fields mpdu_sequence_control_field and 462 mpdu_sequence_number have valid information as well as field 463 464 465 466 For MPDUs without a sequence control field, this field 467 will not be set. 468 469 470 471 472 <legal all> 473 474 mpdu_qos_control_valid 475 476 When set, the field mpdu_qos_control_field has valid 477 information 478 479 480 481 For MPDUs without a QoS control field, this field will 482 not be set. 483 484 485 486 487 <legal all> 488 489 mpdu_ht_control_valid 490 491 When set, the field mpdu_HT_control_field has valid 492 information 493 494 495 496 For MPDUs without a HT control field, this field will 497 not be set. 498 499 500 501 502 <legal all> 503 504 frame_encryption_info_valid 505 506 When set, the encryption related info fields, like IV 507 and PN are valid 508 509 510 511 For MPDUs that are not encrypted, this will not be set. 512 513 514 515 516 <legal all> 517 518 reserved_2a 519 520 <legal 0> 521 522 fr_ds 523 524 Field only valid when Mpdu_frame_control_valid is set 525 526 527 528 Set if the from DS bit is set in the frame control. 529 530 <legal all> 531 532 to_ds 533 534 Field only valid when Mpdu_frame_control_valid is set 535 536 537 538 Set if the to DS bit is set in the frame control. 539 540 <legal all> 541 542 encrypted 543 544 Field only valid when Mpdu_frame_control_valid is set. 545 546 547 548 Protected bit from the frame control. 549 550 <legal all> 551 552 mpdu_retry 553 554 Field only valid when Mpdu_frame_control_valid is set. 555 556 557 558 Retry bit from the frame control. Only valid when 559 first_msdu is set. 560 561 <legal all> 562 563 mpdu_sequence_number 564 565 Field only valid when Mpdu_sequence_control_valid is 566 set. 567 568 569 570 The sequence number from the 802.11 header. 571 572 <legal all> 573 574 epd_en 575 576 Field only valid when AST_based_lookup_valid == 1. 577 578 579 580 581 582 In case of ndp or phy_err or AST_based_lookup_valid == 583 0, this field will be set to 0 584 585 586 587 If set to one use EPD instead of LPD 588 589 590 591 592 <legal all> 593 594 all_frames_shall_be_encrypted 595 596 In case of ndp or phy_err or AST_based_lookup_valid == 597 0, this field will be set to 0 598 599 600 601 When set, all frames (data only ?) shall be encrypted. 602 If not, RX CRYPTO shall set an error flag. 603 604 <legal all> 605 606 encrypt_type 607 608 In case of ndp or phy_err or AST_based_lookup_valid == 609 0, this field will be set to 0 610 611 612 613 Indicates type of decrypt cipher used (as defined in the 614 peer entry) 615 616 617 618 <enum 0 wep_40> WEP 40-bit 619 620 <enum 1 wep_104> WEP 104-bit 621 622 <enum 2 tkip_no_mic> TKIP without MIC 623 624 <enum 3 wep_128> WEP 128-bit 625 626 <enum 4 tkip_with_mic> TKIP with MIC 627 628 <enum 5 wapi> WAPI 629 630 <enum 6 aes_ccmp_128> AES CCMP 128 631 632 <enum 7 no_cipher> No crypto 633 634 <enum 8 aes_ccmp_256> AES CCMP 256 635 636 <enum 9 aes_gcmp_128> AES CCMP 128 637 638 <enum 10 aes_gcmp_256> AES CCMP 256 639 640 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 641 642 643 644 645 <legal 0-11> 646 647 mesh_sta 648 649 In case of ndp or phy_err or AST_based_lookup_valid == 650 0, this field will be set to 0 651 652 653 654 When set, this is a Mesh (11s) STA 655 656 <legal all> 657 658 bssid_hit 659 660 In case of ndp or phy_err or AST_based_lookup_valid == 661 0, this field will be set to 0 662 663 664 665 When set, the BSSID of the incoming frame matched one of 666 the 8 BSSID register values 667 668 669 670 <legal all> 671 672 bssid_number 673 674 Field only valid when bssid_hit is set. 675 676 677 678 This number indicates which one out of the 8 BSSID 679 register values matched the incoming frame 680 681 <legal all> 682 683 tid 684 685 Field only valid when mpdu_qos_control_valid is set 686 687 688 689 The TID field in the QoS control field 690 691 <legal all> 692 693 reserved_3a 694 695 <legal 0> 696 697 pn_31_0 698 699 700 701 702 703 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 704 is valid. 705 706 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 707 WEPSeed[1], pn1}. Only pn[47:0] is valid. 708 709 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 710 pn1, pn0}. Only pn[47:0] is valid. 711 712 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 713 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 714 pn0}. pn[127:0] are valid. 715 716 717 718 719 pn_63_32 720 721 722 723 724 Bits [63:32] of the PN number. See description for 725 pn_31_0. 726 727 728 729 730 pn_95_64 731 732 733 734 735 Bits [95:64] of the PN number. See description for 736 pn_31_0. 737 738 739 740 741 pn_127_96 742 743 744 745 746 Bits [127:96] of the PN number. See description for 747 pn_31_0. 748 749 750 751 752 peer_meta_data 753 754 In case of ndp or phy_err or AST_based_lookup_valid == 755 0, this field will be set to 0 756 757 758 759 Meta data that SW has programmed in the Peer table entry 760 of the transmitting STA. 761 762 <legal all> 763 764 struct rxpt_classify_info rxpt_classify_info_details 765 766 In case of ndp or phy_err or AST_based_lookup_valid == 767 0, this field will be set to 0 768 769 770 771 RXOLE related classification info 772 773 <legal all 774 775 rx_reo_queue_desc_addr_31_0 776 777 In case of ndp or phy_err or AST_based_lookup_valid == 778 0, this field will be set to 0 779 780 781 782 Address (lower 32 bits) of the REO queue descriptor. 783 784 785 786 If no Peer entry lookup happened for this frame, the 787 value wil be set to 0, and the frame shall never be pushed 788 to REO entrance ring. 789 790 <legal all> 791 792 rx_reo_queue_desc_addr_39_32 793 794 In case of ndp or phy_err or AST_based_lookup_valid == 795 0, this field will be set to 0 796 797 798 799 Address (upper 8 bits) of the REO queue descriptor. 800 801 802 803 If no Peer entry lookup happened for this frame, the 804 value wil be set to 0, and the frame shall never be pushed 805 to REO entrance ring. 806 807 <legal all> 808 809 receive_queue_number 810 811 In case of ndp or phy_err or AST_based_lookup_valid == 812 0, this field will be set to 0 813 814 815 816 Indicates the MPDU queue ID to which this MPDU link 817 descriptor belongs 818 819 Used for tracking and debugging 820 821 <legal all> 822 823 pre_delim_err_warning 824 825 Indicates that a delimiter FCS error was found in 826 between the Previous MPDU and this MPDU. 827 828 829 830 Note that this is just a warning, and does not mean that 831 this MPDU is corrupted in any way. If it is, there will be 832 other errors indicated such as FCS or decrypt errors 833 834 835 836 In case of ndp or phy_err, this field will indicate at 837 least one of delimiters located after the last MPDU in the 838 previous PPDU has been corrupted. 839 840 first_delim_err 841 842 Indicates that the first delimiter had a FCS failure. 843 Only valid when first_mpdu and first_msdu are set. 844 845 846 847 848 reserved_11 849 850 <legal 0> 851 852 key_id_octet 853 854 855 856 857 The key ID octet from the IV. 858 859 860 861 In case of ndp or phy_err or AST_based_lookup_valid == 862 0, this field will be set to 0 863 864 <legal all> 865 866 new_peer_entry 867 868 In case of ndp or phy_err or AST_based_lookup_valid == 869 0, this field will be set to 0 870 871 872 873 Set if new RX_PEER_ENTRY TLV follows. If clear, 874 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 875 uses old peer entry or not decrypt. 876 877 <legal all> 878 879 decrypt_needed 880 881 In case of ndp or phy_err or AST_based_lookup_valid == 882 0, this field will be set to 0 883 884 885 886 Set if decryption is needed. 887 888 889 890 Note: 891 892 When RXPCU sets bit 'ast_index_not_found' and/or 893 ast_index_timeout', RXPCU will also ensure that this bit is 894 NOT set 895 896 CRYPTO for that reason only needs to evaluate this bit 897 and non of the other ones. 898 899 <legal all> 900 901 decap_type 902 903 In case of ndp or phy_err or AST_based_lookup_valid == 904 0, this field will be set to 0 905 906 907 908 Used by the OLE during decapsulation. 909 910 911 912 Indicates the decapsulation that HW will perform: 913 914 915 916 <enum 0 PTE_DECAP_RAW> No encapsulation 917 918 <enum 1 PTE_DECAP_Native_WiFi> 919 920 <enum 2 PTE_DECAP_Ethernet_802_3> Ethernet 2 (DIX) or 921 802.3 (uses SNAP/LLC) 922 923 <legal 0-2> 924 925 rx_insert_vlan_c_tag_padding 926 927 In case of ndp or phy_err or AST_based_lookup_valid == 928 0, this field will be set to 0 929 930 931 932 Insert 4 byte of all zeros as VLAN tag if the rx payload 933 does not have VLAN. Used during decapsulation. 934 935 <legal all> 936 937 rx_insert_vlan_s_tag_padding 938 939 In case of ndp or phy_err or AST_based_lookup_valid == 940 0, this field will be set to 0 941 942 943 944 Insert 4 byte of all zeros as double VLAN tag if the rx 945 payload does not have VLAN. Used during 946 947 <legal all> 948 949 strip_vlan_c_tag_decap 950 951 In case of ndp or phy_err or AST_based_lookup_valid == 952 0, this field will be set to 0 953 954 955 956 Strip the VLAN during decapsulation. Used by the OLE. 957 958 <legal all> 959 960 strip_vlan_s_tag_decap 961 962 In case of ndp or phy_err or AST_based_lookup_valid == 963 0, this field will be set to 0 964 965 966 967 Strip the double VLAN during decapsulation. Used by 968 the OLE. 969 970 <legal all> 971 972 pre_delim_count 973 974 The number of delimiters before this MPDU. 975 976 977 978 Note that this number is cleared at PPDU start. 979 980 981 982 If this MPDU is the first received MPDU in the PPDU and 983 this MPDU gets filtered-in, this field will indicate the 984 number of delimiters located after the last MPDU in the 985 previous PPDU. 986 987 988 989 If this MPDU is located after the first received MPDU in 990 an PPDU, this field will indicate the number of delimiters 991 located between the previous MPDU and this MPDU. 992 993 994 995 In case of ndp or phy_err, this field will indicate the 996 number of delimiters located after the last MPDU in the 997 previous PPDU. 998 999 <legal all> 1000 1001 ampdu_flag 1002 1003 When set, received frame was part of an A-MPDU. 1004 1005 1006 1007 1008 <legal all> 1009 1010 bar_frame 1011 1012 In case of ndp or phy_err or AST_based_lookup_valid == 1013 0, this field will be set to 0 1014 1015 1016 1017 When set, received frame is a BAR frame 1018 1019 <legal all> 1020 1021 reserved_12 1022 1023 <legal 0>. 1024 1025 mpdu_length 1026 1027 In case of ndp or phy_err this field will be set to 0 1028 1029 1030 1031 MPDU length before decapsulation. 1032 1033 <legal all> 1034 1035 first_mpdu 1036 1037 See definition in RX attention descriptor 1038 1039 1040 1041 In case of ndp or phy_err, this field will be set. Note 1042 however that there will not actually be any data contents in 1043 the MPDU. 1044 1045 <legal all> 1046 1047 mcast_bcast 1048 1049 In case of ndp or phy_err or Phy_err_during_mpdu_header 1050 this field will be set to 0 1051 1052 1053 1054 See definition in RX attention descriptor 1055 1056 <legal all> 1057 1058 ast_index_not_found 1059 1060 In case of ndp or phy_err or Phy_err_during_mpdu_header 1061 this field will be set to 0 1062 1063 1064 1065 See definition in RX attention descriptor 1066 1067 <legal all> 1068 1069 ast_index_timeout 1070 1071 In case of ndp or phy_err or Phy_err_during_mpdu_header 1072 this field will be set to 0 1073 1074 1075 1076 See definition in RX attention descriptor 1077 1078 <legal all> 1079 1080 power_mgmt 1081 1082 In case of ndp or phy_err or Phy_err_during_mpdu_header 1083 this field will be set to 0 1084 1085 1086 1087 See definition in RX attention descriptor 1088 1089 <legal all> 1090 1091 non_qos 1092 1093 In case of ndp or phy_err or Phy_err_during_mpdu_header 1094 this field will be set to 1 1095 1096 1097 1098 See definition in RX attention descriptor 1099 1100 <legal all> 1101 1102 null_data 1103 1104 In case of ndp or phy_err or Phy_err_during_mpdu_header 1105 this field will be set to 0 1106 1107 1108 1109 See definition in RX attention descriptor 1110 1111 <legal all> 1112 1113 mgmt_type 1114 1115 In case of ndp or phy_err or Phy_err_during_mpdu_header 1116 this field will be set to 0 1117 1118 1119 1120 See definition in RX attention descriptor 1121 1122 <legal all> 1123 1124 ctrl_type 1125 1126 In case of ndp or phy_err or Phy_err_during_mpdu_header 1127 this field will be set to 0 1128 1129 1130 1131 See definition in RX attention descriptor 1132 1133 <legal all> 1134 1135 more_data 1136 1137 In case of ndp or phy_err or Phy_err_during_mpdu_header 1138 this field will be set to 0 1139 1140 1141 1142 See definition in RX attention descriptor 1143 1144 <legal all> 1145 1146 eosp 1147 1148 In case of ndp or phy_err or Phy_err_during_mpdu_header 1149 this field will be set to 0 1150 1151 1152 1153 See definition in RX attention descriptor 1154 1155 <legal all> 1156 1157 fragment_flag 1158 1159 In case of ndp or phy_err or Phy_err_during_mpdu_header 1160 this field will be set to 0 1161 1162 1163 1164 See definition in RX attention descriptor 1165 1166 <legal all> 1167 1168 order 1169 1170 In case of ndp or phy_err or Phy_err_during_mpdu_header 1171 this field will be set to 0 1172 1173 1174 1175 See definition in RX attention descriptor 1176 1177 1178 1179 <legal all> 1180 1181 u_apsd_trigger 1182 1183 In case of ndp or phy_err or Phy_err_during_mpdu_header 1184 this field will be set to 0 1185 1186 1187 1188 See definition in RX attention descriptor 1189 1190 <legal all> 1191 1192 encrypt_required 1193 1194 In case of ndp or phy_err or Phy_err_during_mpdu_header 1195 this field will be set to 0 1196 1197 1198 1199 See definition in RX attention descriptor 1200 1201 <legal all> 1202 1203 directed 1204 1205 In case of ndp or phy_err or Phy_err_during_mpdu_header 1206 this field will be set to 0 1207 1208 1209 1210 See definition in RX attention descriptor 1211 1212 <legal all> 1213 1214 reserved_13 1215 1216 <legal 0> 1217 1218 mpdu_frame_control_field 1219 1220 Field only valid when Mpdu_frame_control_valid is set 1221 1222 1223 1224 The frame control field of this received MPDU. 1225 1226 1227 1228 Field only valid when Ndp_frame and phy_err are NOT set 1229 1230 1231 1232 Bytes 0 + 1 of the received MPDU 1233 1234 <legal all> 1235 1236 mpdu_duration_field 1237 1238 Field only valid when Mpdu_duration_valid is set 1239 1240 1241 1242 The duration field of this received MPDU. 1243 1244 <legal all> 1245 1246 mac_addr_ad1_31_0 1247 1248 Field only valid when mac_addr_ad1_valid is set 1249 1250 1251 1252 The Least Significant 4 bytes of the Received Frames MAC 1253 Address AD1 1254 1255 <legal all> 1256 1257 mac_addr_ad1_47_32 1258 1259 Field only valid when mac_addr_ad1_valid is set 1260 1261 1262 1263 The 2 most significant bytes of the Received Frames MAC 1264 Address AD1 1265 1266 <legal all> 1267 1268 mac_addr_ad2_15_0 1269 1270 Field only valid when mac_addr_ad2_valid is set 1271 1272 1273 1274 The Least Significant 2 bytes of the Received Frames MAC 1275 Address AD2 1276 1277 <legal all> 1278 1279 mac_addr_ad2_47_16 1280 1281 Field only valid when mac_addr_ad2_valid is set 1282 1283 1284 1285 The 4 most significant bytes of the Received Frames MAC 1286 Address AD2 1287 1288 <legal all> 1289 1290 mac_addr_ad3_31_0 1291 1292 Field only valid when mac_addr_ad3_valid is set 1293 1294 1295 1296 The Least Significant 4 bytes of the Received Frames MAC 1297 Address AD3 1298 1299 <legal all> 1300 1301 mac_addr_ad3_47_32 1302 1303 Field only valid when mac_addr_ad3_valid is set 1304 1305 1306 1307 The 2 most significant bytes of the Received Frames MAC 1308 Address AD3 1309 1310 <legal all> 1311 1312 mpdu_sequence_control_field 1313 1314 1315 1316 1317 The sequence control field of the MPDU 1318 1319 <legal all> 1320 1321 mac_addr_ad4_31_0 1322 1323 Field only valid when mac_addr_ad4_valid is set 1324 1325 1326 1327 The Least Significant 4 bytes of the Received Frames MAC 1328 Address AD4 1329 1330 <legal all> 1331 1332 mac_addr_ad4_47_32 1333 1334 Field only valid when mac_addr_ad4_valid is set 1335 1336 1337 1338 The 2 most significant bytes of the Received Frames MAC 1339 Address AD4 1340 1341 <legal all> 1342 1343 mpdu_qos_control_field 1344 1345 Field only valid when mpdu_qos_control_valid is set 1346 1347 1348 1349 The sequence control field of the MPDU 1350 1351 <legal all> 1352 1353 mpdu_ht_control_field 1354 1355 Field only valid when mpdu_qos_control_valid is set 1356 1357 1358 1359 The HT control field of the MPDU 1360 1361 <legal all> 1362 */ 1363 1364 1365 /* Description RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY 1366 1367 Field indicates what the reason was that this MPDU frame 1368 was allowed to come into the receive path by RXPCU 1369 1370 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 1371 frame filter programming of rxpcu 1372 1373 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 1374 regular frame filter and would have been dropped, were it 1375 not for the frame fitting into the 'monitor_client' 1376 category. 1377 1378 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 1379 regular frame filter and also did not pass the 1380 rxpcu_monitor_client filter. It would have been dropped 1381 accept that it did pass the 'monitor_other' category. 1382 1383 1384 1385 Note: for ndp frame, if it was expected because the 1386 preceding NDPA was filter_pass, the setting 1387 rxpcu_filter_pass will be used. This setting will also be 1388 used for every ndp frame in case Promiscuous mode is 1389 enabled. 1390 1391 1392 1393 In case promiscuous is not enabled, and an NDP is not 1394 preceded by a NPDA filter pass frame, the only other setting 1395 that could appear here for the NDP is rxpcu_monitor_other. 1396 1397 (rxpcu has a configuration bit specifically for this 1398 scenario) 1399 1400 1401 1402 Note: for 1403 1404 <legal 0-2> 1405 */ 1406 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 1407 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 1408 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 1409 1410 /* Description RX_MPDU_INFO_0_SW_FRAME_GROUP_ID 1411 1412 SW processes frames based on certain classifications. 1413 This field indicates to what sw classification this MPDU is 1414 mapped. 1415 1416 The classification is given in priority order 1417 1418 1419 1420 <enum 0 sw_frame_group_NDP_frame> Note: The 1421 corresponding Rxpcu_Mpdu_filter_in_category can be 1422 rxpcu_filter_pass or rxpcu_monitor_other 1423 1424 1425 1426 <enum 1 sw_frame_group_Multicast_data> 1427 1428 <enum 2 sw_frame_group_Unicast_data> 1429 1430 <enum 3 sw_frame_group_Null_data > This includes mpdus 1431 of type Data Null as well as QoS Data Null 1432 1433 1434 1435 <enum 4 sw_frame_group_mgmt_0000 > 1436 1437 <enum 5 sw_frame_group_mgmt_0001 > 1438 1439 <enum 6 sw_frame_group_mgmt_0010 > 1440 1441 <enum 7 sw_frame_group_mgmt_0011 > 1442 1443 <enum 8 sw_frame_group_mgmt_0100 > 1444 1445 <enum 9 sw_frame_group_mgmt_0101 > 1446 1447 <enum 10 sw_frame_group_mgmt_0110 > 1448 1449 <enum 11 sw_frame_group_mgmt_0111 > 1450 1451 <enum 12 sw_frame_group_mgmt_1000 > 1452 1453 <enum 13 sw_frame_group_mgmt_1001 > 1454 1455 <enum 14 sw_frame_group_mgmt_1010 > 1456 1457 <enum 15 sw_frame_group_mgmt_1011 > 1458 1459 <enum 16 sw_frame_group_mgmt_1100 > 1460 1461 <enum 17 sw_frame_group_mgmt_1101 > 1462 1463 <enum 18 sw_frame_group_mgmt_1110 > 1464 1465 <enum 19 sw_frame_group_mgmt_1111 > 1466 1467 1468 1469 <enum 20 sw_frame_group_ctrl_0000 > 1470 1471 <enum 21 sw_frame_group_ctrl_0001 > 1472 1473 <enum 22 sw_frame_group_ctrl_0010 > 1474 1475 <enum 23 sw_frame_group_ctrl_0011 > 1476 1477 <enum 24 sw_frame_group_ctrl_0100 > 1478 1479 <enum 25 sw_frame_group_ctrl_0101 > 1480 1481 <enum 26 sw_frame_group_ctrl_0110 > 1482 1483 <enum 27 sw_frame_group_ctrl_0111 > 1484 1485 <enum 28 sw_frame_group_ctrl_1000 > 1486 1487 <enum 29 sw_frame_group_ctrl_1001 > 1488 1489 <enum 30 sw_frame_group_ctrl_1010 > 1490 1491 <enum 31 sw_frame_group_ctrl_1011 > 1492 1493 <enum 32 sw_frame_group_ctrl_1100 > 1494 1495 <enum 33 sw_frame_group_ctrl_1101 > 1496 1497 <enum 34 sw_frame_group_ctrl_1110 > 1498 1499 <enum 35 sw_frame_group_ctrl_1111 > 1500 1501 1502 1503 <enum 36 sw_frame_group_unsupported> This covers type 3 1504 and protocol version != 0 1505 1506 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1507 can only be rxpcu_monitor_other 1508 1509 1510 1511 1512 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1513 can be rxpcu_filter_pass 1514 1515 1516 1517 <legal 0-37> 1518 */ 1519 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 1520 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB 2 1521 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 1522 1523 /* Description RX_MPDU_INFO_0_NDP_FRAME 1524 1525 When set, the received frame was an NDP frame, and thus 1526 there will be no MPDU data. 1527 1528 <legal all> 1529 */ 1530 #define RX_MPDU_INFO_0_NDP_FRAME_OFFSET 0x00000000 1531 #define RX_MPDU_INFO_0_NDP_FRAME_LSB 9 1532 #define RX_MPDU_INFO_0_NDP_FRAME_MASK 0x00000200 1533 1534 /* Description RX_MPDU_INFO_0_PHY_ERR 1535 1536 When set, a PHY error was received before MAC received 1537 any data, and thus there will be no MPDU data. 1538 1539 <legal all> 1540 */ 1541 #define RX_MPDU_INFO_0_PHY_ERR_OFFSET 0x00000000 1542 #define RX_MPDU_INFO_0_PHY_ERR_LSB 10 1543 #define RX_MPDU_INFO_0_PHY_ERR_MASK 0x00000400 1544 1545 /* Description RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER 1546 1547 When set, a PHY error was received before MAC received 1548 the complete MPDU header which was needed for proper 1549 decoding 1550 1551 <legal all> 1552 */ 1553 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000000 1554 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB 11 1555 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 1556 1557 /* Description RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR 1558 1559 Set when RXPCU detected a version error in the Frame 1560 control field 1561 1562 <legal all> 1563 */ 1564 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET 0x00000000 1565 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB 12 1566 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK 0x00001000 1567 1568 /* Description RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID 1569 1570 When set, AST based lookup for this frame has found a 1571 valid result. 1572 1573 1574 1575 Note that for NDP frame this will never be set 1576 1577 <legal all> 1578 */ 1579 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET 0x00000000 1580 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB 13 1581 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK 0x00002000 1582 1583 /* Description RX_MPDU_INFO_0_RESERVED_0A 1584 1585 <legal 0> 1586 */ 1587 #define RX_MPDU_INFO_0_RESERVED_0A_OFFSET 0x00000000 1588 #define RX_MPDU_INFO_0_RESERVED_0A_LSB 14 1589 #define RX_MPDU_INFO_0_RESERVED_0A_MASK 0x0000c000 1590 1591 /* Description RX_MPDU_INFO_0_PHY_PPDU_ID 1592 1593 A ppdu counter value that PHY increments for every PPDU 1594 received. The counter value wraps around 1595 1596 <legal all> 1597 */ 1598 #define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 1599 #define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB 16 1600 #define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK 0xffff0000 1601 1602 /* Description RX_MPDU_INFO_1_AST_INDEX 1603 1604 This field indicates the index of the AST entry 1605 corresponding to this MPDU. It is provided by the GSE module 1606 instantiated in RXPCU. 1607 1608 A value of 0xFFFF indicates an invalid AST index, 1609 meaning that No AST entry was found or NO AST search was 1610 performed 1611 1612 1613 1614 In case of ndp or phy_err, this field will be set to 1615 0xFFFF 1616 1617 <legal all> 1618 */ 1619 #define RX_MPDU_INFO_1_AST_INDEX_OFFSET 0x00000004 1620 #define RX_MPDU_INFO_1_AST_INDEX_LSB 0 1621 #define RX_MPDU_INFO_1_AST_INDEX_MASK 0x0000ffff 1622 1623 /* Description RX_MPDU_INFO_1_SW_PEER_ID 1624 1625 In case of ndp or phy_err or AST_based_lookup_valid == 1626 0, this field will be set to 0 1627 1628 1629 1630 This field indicates a unique peer identifier. It is set 1631 equal to field 'sw_peer_id' from the AST entry 1632 1633 1634 1635 <legal all> 1636 */ 1637 #define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET 0x00000004 1638 #define RX_MPDU_INFO_1_SW_PEER_ID_LSB 16 1639 #define RX_MPDU_INFO_1_SW_PEER_ID_MASK 0xffff0000 1640 1641 /* Description RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID 1642 1643 When set, the field Mpdu_Frame_control_field has valid 1644 information 1645 1646 1647 1648 1649 <legal all> 1650 */ 1651 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000008 1652 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB 0 1653 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 1654 1655 /* Description RX_MPDU_INFO_2_MPDU_DURATION_VALID 1656 1657 When set, the field Mpdu_duration_field has valid 1658 information 1659 1660 1661 1662 1663 <legal all> 1664 */ 1665 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET 0x00000008 1666 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB 1 1667 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK 0x00000002 1668 1669 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID 1670 1671 When set, the fields mac_addr_ad1_..... have valid 1672 information 1673 1674 1675 1676 1677 <legal all> 1678 */ 1679 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET 0x00000008 1680 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB 2 1681 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK 0x00000004 1682 1683 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID 1684 1685 When set, the fields mac_addr_ad2_..... have valid 1686 information 1687 1688 1689 1690 1691 1692 1693 1694 <legal all> 1695 */ 1696 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET 0x00000008 1697 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB 3 1698 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK 0x00000008 1699 1700 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID 1701 1702 When set, the fields mac_addr_ad3_..... have valid 1703 information 1704 1705 1706 1707 1708 1709 1710 1711 <legal all> 1712 */ 1713 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET 0x00000008 1714 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB 4 1715 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK 0x00000010 1716 1717 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID 1718 1719 When set, the fields mac_addr_ad4_..... have valid 1720 information 1721 1722 1723 1724 1725 1726 1727 1728 <legal all> 1729 */ 1730 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET 0x00000008 1731 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB 5 1732 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK 0x00000020 1733 1734 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID 1735 1736 When set, the fields mpdu_sequence_control_field and 1737 mpdu_sequence_number have valid information as well as field 1738 1739 1740 1741 For MPDUs without a sequence control field, this field 1742 will not be set. 1743 1744 1745 1746 1747 <legal all> 1748 */ 1749 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000008 1750 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1751 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1752 1753 /* Description RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID 1754 1755 When set, the field mpdu_qos_control_field has valid 1756 information 1757 1758 1759 1760 For MPDUs without a QoS control field, this field will 1761 not be set. 1762 1763 1764 1765 1766 <legal all> 1767 */ 1768 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 1769 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB 7 1770 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1771 1772 /* Description RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID 1773 1774 When set, the field mpdu_HT_control_field has valid 1775 information 1776 1777 1778 1779 For MPDUs without a HT control field, this field will 1780 not be set. 1781 1782 1783 1784 1785 <legal all> 1786 */ 1787 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET 0x00000008 1788 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB 8 1789 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1790 1791 /* Description RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID 1792 1793 When set, the encryption related info fields, like IV 1794 and PN are valid 1795 1796 1797 1798 For MPDUs that are not encrypted, this will not be set. 1799 1800 1801 1802 1803 <legal all> 1804 */ 1805 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000008 1806 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1807 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1808 1809 /* Description RX_MPDU_INFO_2_RESERVED_2A 1810 1811 <legal 0> 1812 */ 1813 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 1814 #define RX_MPDU_INFO_2_RESERVED_2A_LSB 10 1815 #define RX_MPDU_INFO_2_RESERVED_2A_MASK 0x0000fc00 1816 1817 /* Description RX_MPDU_INFO_2_FR_DS 1818 1819 Field only valid when Mpdu_frame_control_valid is set 1820 1821 1822 1823 Set if the from DS bit is set in the frame control. 1824 1825 <legal all> 1826 */ 1827 #define RX_MPDU_INFO_2_FR_DS_OFFSET 0x00000008 1828 #define RX_MPDU_INFO_2_FR_DS_LSB 16 1829 #define RX_MPDU_INFO_2_FR_DS_MASK 0x00010000 1830 1831 /* Description RX_MPDU_INFO_2_TO_DS 1832 1833 Field only valid when Mpdu_frame_control_valid is set 1834 1835 1836 1837 Set if the to DS bit is set in the frame control. 1838 1839 <legal all> 1840 */ 1841 #define RX_MPDU_INFO_2_TO_DS_OFFSET 0x00000008 1842 #define RX_MPDU_INFO_2_TO_DS_LSB 17 1843 #define RX_MPDU_INFO_2_TO_DS_MASK 0x00020000 1844 1845 /* Description RX_MPDU_INFO_2_ENCRYPTED 1846 1847 Field only valid when Mpdu_frame_control_valid is set. 1848 1849 1850 1851 Protected bit from the frame control. 1852 1853 <legal all> 1854 */ 1855 #define RX_MPDU_INFO_2_ENCRYPTED_OFFSET 0x00000008 1856 #define RX_MPDU_INFO_2_ENCRYPTED_LSB 18 1857 #define RX_MPDU_INFO_2_ENCRYPTED_MASK 0x00040000 1858 1859 /* Description RX_MPDU_INFO_2_MPDU_RETRY 1860 1861 Field only valid when Mpdu_frame_control_valid is set. 1862 1863 1864 1865 Retry bit from the frame control. Only valid when 1866 first_msdu is set. 1867 1868 <legal all> 1869 */ 1870 #define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET 0x00000008 1871 #define RX_MPDU_INFO_2_MPDU_RETRY_LSB 19 1872 #define RX_MPDU_INFO_2_MPDU_RETRY_MASK 0x00080000 1873 1874 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER 1875 1876 Field only valid when Mpdu_sequence_control_valid is 1877 set. 1878 1879 1880 1881 The sequence number from the 802.11 header. 1882 1883 <legal all> 1884 */ 1885 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 1886 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB 20 1887 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1888 1889 /* Description RX_MPDU_INFO_3_EPD_EN 1890 1891 Field only valid when AST_based_lookup_valid == 1. 1892 1893 1894 1895 1896 1897 In case of ndp or phy_err or AST_based_lookup_valid == 1898 0, this field will be set to 0 1899 1900 1901 1902 If set to one use EPD instead of LPD 1903 1904 1905 1906 1907 <legal all> 1908 */ 1909 #define RX_MPDU_INFO_3_EPD_EN_OFFSET 0x0000000c 1910 #define RX_MPDU_INFO_3_EPD_EN_LSB 0 1911 #define RX_MPDU_INFO_3_EPD_EN_MASK 0x00000001 1912 1913 /* Description RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED 1914 1915 In case of ndp or phy_err or AST_based_lookup_valid == 1916 0, this field will be set to 0 1917 1918 1919 1920 When set, all frames (data only ?) shall be encrypted. 1921 If not, RX CRYPTO shall set an error flag. 1922 1923 <legal all> 1924 */ 1925 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000c 1926 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 1927 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 1928 1929 /* Description RX_MPDU_INFO_3_ENCRYPT_TYPE 1930 1931 In case of ndp or phy_err or AST_based_lookup_valid == 1932 0, this field will be set to 0 1933 1934 1935 1936 Indicates type of decrypt cipher used (as defined in the 1937 peer entry) 1938 1939 1940 1941 <enum 0 wep_40> WEP 40-bit 1942 1943 <enum 1 wep_104> WEP 104-bit 1944 1945 <enum 2 tkip_no_mic> TKIP without MIC 1946 1947 <enum 3 wep_128> WEP 128-bit 1948 1949 <enum 4 tkip_with_mic> TKIP with MIC 1950 1951 <enum 5 wapi> WAPI 1952 1953 <enum 6 aes_ccmp_128> AES CCMP 128 1954 1955 <enum 7 no_cipher> No crypto 1956 1957 <enum 8 aes_ccmp_256> AES CCMP 256 1958 1959 <enum 9 aes_gcmp_128> AES CCMP 128 1960 1961 <enum 10 aes_gcmp_256> AES CCMP 256 1962 1963 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 1964 1965 1966 1967 1968 <legal 0-11> 1969 */ 1970 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET 0x0000000c 1971 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB 2 1972 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK 0x0000003c 1973 1974 /* Description RX_MPDU_INFO_3_MESH_STA 1975 1976 In case of ndp or phy_err or AST_based_lookup_valid == 1977 0, this field will be set to 0 1978 1979 1980 1981 When set, this is a Mesh (11s) STA 1982 1983 <legal all> 1984 */ 1985 #define RX_MPDU_INFO_3_MESH_STA_OFFSET 0x0000000c 1986 #define RX_MPDU_INFO_3_MESH_STA_LSB 6 1987 #define RX_MPDU_INFO_3_MESH_STA_MASK 0x00000040 1988 1989 /* Description RX_MPDU_INFO_3_BSSID_HIT 1990 1991 In case of ndp or phy_err or AST_based_lookup_valid == 1992 0, this field will be set to 0 1993 1994 1995 1996 When set, the BSSID of the incoming frame matched one of 1997 the 8 BSSID register values 1998 1999 2000 2001 <legal all> 2002 */ 2003 #define RX_MPDU_INFO_3_BSSID_HIT_OFFSET 0x0000000c 2004 #define RX_MPDU_INFO_3_BSSID_HIT_LSB 7 2005 #define RX_MPDU_INFO_3_BSSID_HIT_MASK 0x00000080 2006 2007 /* Description RX_MPDU_INFO_3_BSSID_NUMBER 2008 2009 Field only valid when bssid_hit is set. 2010 2011 2012 2013 This number indicates which one out of the 8 BSSID 2014 register values matched the incoming frame 2015 2016 <legal all> 2017 */ 2018 #define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET 0x0000000c 2019 #define RX_MPDU_INFO_3_BSSID_NUMBER_LSB 8 2020 #define RX_MPDU_INFO_3_BSSID_NUMBER_MASK 0x00000f00 2021 2022 /* Description RX_MPDU_INFO_3_TID 2023 2024 Field only valid when mpdu_qos_control_valid is set 2025 2026 2027 2028 The TID field in the QoS control field 2029 2030 <legal all> 2031 */ 2032 #define RX_MPDU_INFO_3_TID_OFFSET 0x0000000c 2033 #define RX_MPDU_INFO_3_TID_LSB 12 2034 #define RX_MPDU_INFO_3_TID_MASK 0x0000f000 2035 2036 /* Description RX_MPDU_INFO_3_RESERVED_3A 2037 2038 <legal 0> 2039 */ 2040 #define RX_MPDU_INFO_3_RESERVED_3A_OFFSET 0x0000000c 2041 #define RX_MPDU_INFO_3_RESERVED_3A_LSB 16 2042 #define RX_MPDU_INFO_3_RESERVED_3A_MASK 0xffff0000 2043 2044 /* Description RX_MPDU_INFO_4_PN_31_0 2045 2046 2047 2048 2049 2050 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 2051 is valid. 2052 2053 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 2054 WEPSeed[1], pn1}. Only pn[47:0] is valid. 2055 2056 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 2057 pn1, pn0}. Only pn[47:0] is valid. 2058 2059 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 2060 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 2061 pn0}. pn[127:0] are valid. 2062 2063 2064 2065 */ 2066 #define RX_MPDU_INFO_4_PN_31_0_OFFSET 0x00000010 2067 #define RX_MPDU_INFO_4_PN_31_0_LSB 0 2068 #define RX_MPDU_INFO_4_PN_31_0_MASK 0xffffffff 2069 2070 /* Description RX_MPDU_INFO_5_PN_63_32 2071 2072 2073 2074 2075 Bits [63:32] of the PN number. See description for 2076 pn_31_0. 2077 2078 2079 2080 */ 2081 #define RX_MPDU_INFO_5_PN_63_32_OFFSET 0x00000014 2082 #define RX_MPDU_INFO_5_PN_63_32_LSB 0 2083 #define RX_MPDU_INFO_5_PN_63_32_MASK 0xffffffff 2084 2085 /* Description RX_MPDU_INFO_6_PN_95_64 2086 2087 2088 2089 2090 Bits [95:64] of the PN number. See description for 2091 pn_31_0. 2092 2093 2094 2095 */ 2096 #define RX_MPDU_INFO_6_PN_95_64_OFFSET 0x00000018 2097 #define RX_MPDU_INFO_6_PN_95_64_LSB 0 2098 #define RX_MPDU_INFO_6_PN_95_64_MASK 0xffffffff 2099 2100 /* Description RX_MPDU_INFO_7_PN_127_96 2101 2102 2103 2104 2105 Bits [127:96] of the PN number. See description for 2106 pn_31_0. 2107 2108 2109 2110 */ 2111 #define RX_MPDU_INFO_7_PN_127_96_OFFSET 0x0000001c 2112 #define RX_MPDU_INFO_7_PN_127_96_LSB 0 2113 #define RX_MPDU_INFO_7_PN_127_96_MASK 0xffffffff 2114 2115 /* Description RX_MPDU_INFO_8_PEER_META_DATA 2116 2117 In case of ndp or phy_err or AST_based_lookup_valid == 2118 0, this field will be set to 0 2119 2120 2121 2122 Meta data that SW has programmed in the Peer table entry 2123 of the transmitting STA. 2124 2125 <legal all> 2126 */ 2127 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 2128 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 2129 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 2130 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_OFFSET 0x00000024 2131 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_LSB 0 2132 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_MASK 0xffffffff 2133 2134 /* Description RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0 2135 2136 In case of ndp or phy_err or AST_based_lookup_valid == 2137 0, this field will be set to 0 2138 2139 2140 2141 Address (lower 32 bits) of the REO queue descriptor. 2142 2143 2144 2145 If no Peer entry lookup happened for this frame, the 2146 value wil be set to 0, and the frame shall never be pushed 2147 to REO entrance ring. 2148 2149 <legal all> 2150 */ 2151 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000028 2152 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 2153 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 2154 2155 /* Description RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32 2156 2157 In case of ndp or phy_err or AST_based_lookup_valid == 2158 0, this field will be set to 0 2159 2160 2161 2162 Address (upper 8 bits) of the REO queue descriptor. 2163 2164 2165 2166 If no Peer entry lookup happened for this frame, the 2167 value wil be set to 0, and the frame shall never be pushed 2168 to REO entrance ring. 2169 2170 <legal all> 2171 */ 2172 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000002c 2173 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 2174 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 2175 2176 /* Description RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER 2177 2178 In case of ndp or phy_err or AST_based_lookup_valid == 2179 0, this field will be set to 0 2180 2181 2182 2183 Indicates the MPDU queue ID to which this MPDU link 2184 descriptor belongs 2185 2186 Used for tracking and debugging 2187 2188 <legal all> 2189 */ 2190 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000002c 2191 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB 8 2192 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 2193 2194 /* Description RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING 2195 2196 Indicates that a delimiter FCS error was found in 2197 between the Previous MPDU and this MPDU. 2198 2199 2200 2201 Note that this is just a warning, and does not mean that 2202 this MPDU is corrupted in any way. If it is, there will be 2203 other errors indicated such as FCS or decrypt errors 2204 2205 2206 2207 In case of ndp or phy_err, this field will indicate at 2208 least one of delimiters located after the last MPDU in the 2209 previous PPDU has been corrupted. 2210 */ 2211 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c 2212 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB 24 2213 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK 0x01000000 2214 2215 /* Description RX_MPDU_INFO_11_FIRST_DELIM_ERR 2216 2217 Indicates that the first delimiter had a FCS failure. 2218 Only valid when first_mpdu and first_msdu are set. 2219 2220 2221 2222 */ 2223 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET 0x0000002c 2224 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB 25 2225 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK 0x02000000 2226 2227 /* Description RX_MPDU_INFO_11_RESERVED_11 2228 2229 <legal 0> 2230 */ 2231 #define RX_MPDU_INFO_11_RESERVED_11_OFFSET 0x0000002c 2232 #define RX_MPDU_INFO_11_RESERVED_11_LSB 26 2233 #define RX_MPDU_INFO_11_RESERVED_11_MASK 0xfc000000 2234 2235 /* Description RX_MPDU_INFO_12_KEY_ID_OCTET 2236 2237 2238 2239 2240 The key ID octet from the IV. 2241 2242 2243 2244 In case of ndp or phy_err or AST_based_lookup_valid == 2245 0, this field will be set to 0 2246 2247 <legal all> 2248 */ 2249 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 2250 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 2251 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 2252 2253 /* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY 2254 2255 In case of ndp or phy_err or AST_based_lookup_valid == 2256 0, this field will be set to 0 2257 2258 2259 2260 Set if new RX_PEER_ENTRY TLV follows. If clear, 2261 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 2262 uses old peer entry or not decrypt. 2263 2264 <legal all> 2265 */ 2266 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 2267 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 2268 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 2269 2270 /* Description RX_MPDU_INFO_12_DECRYPT_NEEDED 2271 2272 In case of ndp or phy_err or AST_based_lookup_valid == 2273 0, this field will be set to 0 2274 2275 2276 2277 Set if decryption is needed. 2278 2279 2280 2281 Note: 2282 2283 When RXPCU sets bit 'ast_index_not_found' and/or 2284 ast_index_timeout', RXPCU will also ensure that this bit is 2285 NOT set 2286 2287 CRYPTO for that reason only needs to evaluate this bit 2288 and non of the other ones. 2289 2290 <legal all> 2291 */ 2292 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 2293 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 2294 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 2295 2296 /* Description RX_MPDU_INFO_12_DECAP_TYPE 2297 2298 In case of ndp or phy_err or AST_based_lookup_valid == 2299 0, this field will be set to 0 2300 2301 2302 2303 Used by the OLE during decapsulation. 2304 2305 2306 2307 Indicates the decapsulation that HW will perform: 2308 2309 2310 2311 <enum 0 PTE_DECAP_RAW> No encapsulation 2312 2313 <enum 1 PTE_DECAP_Native_WiFi> 2314 2315 <enum 2 PTE_DECAP_Ethernet_802_3> Ethernet 2 (DIX) or 2316 802.3 (uses SNAP/LLC) 2317 2318 <legal 0-2> 2319 */ 2320 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 2321 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 2322 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 2323 2324 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING 2325 2326 In case of ndp or phy_err or AST_based_lookup_valid == 2327 0, this field will be set to 0 2328 2329 2330 2331 Insert 4 byte of all zeros as VLAN tag if the rx payload 2332 does not have VLAN. Used during decapsulation. 2333 2334 <legal all> 2335 */ 2336 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 2337 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 2338 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 2339 2340 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING 2341 2342 In case of ndp or phy_err or AST_based_lookup_valid == 2343 0, this field will be set to 0 2344 2345 2346 2347 Insert 4 byte of all zeros as double VLAN tag if the rx 2348 payload does not have VLAN. Used during 2349 2350 <legal all> 2351 */ 2352 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 2353 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 2354 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 2355 2356 /* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP 2357 2358 In case of ndp or phy_err or AST_based_lookup_valid == 2359 0, this field will be set to 0 2360 2361 2362 2363 Strip the VLAN during decapsulation. Used by the OLE. 2364 2365 <legal all> 2366 */ 2367 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 2368 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 2369 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 2370 2371 /* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP 2372 2373 In case of ndp or phy_err or AST_based_lookup_valid == 2374 0, this field will be set to 0 2375 2376 2377 2378 Strip the double VLAN during decapsulation. Used by 2379 the OLE. 2380 2381 <legal all> 2382 */ 2383 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 2384 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 2385 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 2386 2387 /* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT 2388 2389 The number of delimiters before this MPDU. 2390 2391 2392 2393 Note that this number is cleared at PPDU start. 2394 2395 2396 2397 If this MPDU is the first received MPDU in the PPDU and 2398 this MPDU gets filtered-in, this field will indicate the 2399 number of delimiters located after the last MPDU in the 2400 previous PPDU. 2401 2402 2403 2404 If this MPDU is located after the first received MPDU in 2405 an PPDU, this field will indicate the number of delimiters 2406 located between the previous MPDU and this MPDU. 2407 2408 2409 2410 In case of ndp or phy_err, this field will indicate the 2411 number of delimiters located after the last MPDU in the 2412 previous PPDU. 2413 2414 <legal all> 2415 */ 2416 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 2417 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 2418 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 2419 2420 /* Description RX_MPDU_INFO_12_AMPDU_FLAG 2421 2422 When set, received frame was part of an A-MPDU. 2423 2424 2425 2426 2427 <legal all> 2428 */ 2429 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 2430 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 2431 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 2432 2433 /* Description RX_MPDU_INFO_12_BAR_FRAME 2434 2435 In case of ndp or phy_err or AST_based_lookup_valid == 2436 0, this field will be set to 0 2437 2438 2439 2440 When set, received frame is a BAR frame 2441 2442 <legal all> 2443 */ 2444 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 2445 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 2446 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 2447 2448 /* Description RX_MPDU_INFO_12_RESERVED_12 2449 2450 <legal 0>. 2451 */ 2452 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 2453 #define RX_MPDU_INFO_12_RESERVED_12_LSB 30 2454 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0xc0000000 2455 2456 /* Description RX_MPDU_INFO_13_MPDU_LENGTH 2457 2458 In case of ndp or phy_err this field will be set to 0 2459 2460 2461 2462 MPDU length before decapsulation. 2463 2464 <legal all> 2465 */ 2466 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 2467 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 2468 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 2469 2470 /* Description RX_MPDU_INFO_13_FIRST_MPDU 2471 2472 See definition in RX attention descriptor 2473 2474 2475 2476 In case of ndp or phy_err, this field will be set. Note 2477 however that there will not actually be any data contents in 2478 the MPDU. 2479 2480 <legal all> 2481 */ 2482 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 2483 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 2484 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 2485 2486 /* Description RX_MPDU_INFO_13_MCAST_BCAST 2487 2488 In case of ndp or phy_err or Phy_err_during_mpdu_header 2489 this field will be set to 0 2490 2491 2492 2493 See definition in RX attention descriptor 2494 2495 <legal all> 2496 */ 2497 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 2498 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 2499 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 2500 2501 /* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND 2502 2503 In case of ndp or phy_err or Phy_err_during_mpdu_header 2504 this field will be set to 0 2505 2506 2507 2508 See definition in RX attention descriptor 2509 2510 <legal all> 2511 */ 2512 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 2513 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 2514 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 2515 2516 /* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT 2517 2518 In case of ndp or phy_err or Phy_err_during_mpdu_header 2519 this field will be set to 0 2520 2521 2522 2523 See definition in RX attention descriptor 2524 2525 <legal all> 2526 */ 2527 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 2528 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 2529 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 2530 2531 /* Description RX_MPDU_INFO_13_POWER_MGMT 2532 2533 In case of ndp or phy_err or Phy_err_during_mpdu_header 2534 this field will be set to 0 2535 2536 2537 2538 See definition in RX attention descriptor 2539 2540 <legal all> 2541 */ 2542 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 2543 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 2544 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 2545 2546 /* Description RX_MPDU_INFO_13_NON_QOS 2547 2548 In case of ndp or phy_err or Phy_err_during_mpdu_header 2549 this field will be set to 1 2550 2551 2552 2553 See definition in RX attention descriptor 2554 2555 <legal all> 2556 */ 2557 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 2558 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 2559 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 2560 2561 /* Description RX_MPDU_INFO_13_NULL_DATA 2562 2563 In case of ndp or phy_err or Phy_err_during_mpdu_header 2564 this field will be set to 0 2565 2566 2567 2568 See definition in RX attention descriptor 2569 2570 <legal all> 2571 */ 2572 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 2573 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 2574 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 2575 2576 /* Description RX_MPDU_INFO_13_MGMT_TYPE 2577 2578 In case of ndp or phy_err or Phy_err_during_mpdu_header 2579 this field will be set to 0 2580 2581 2582 2583 See definition in RX attention descriptor 2584 2585 <legal all> 2586 */ 2587 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 2588 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 2589 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 2590 2591 /* Description RX_MPDU_INFO_13_CTRL_TYPE 2592 2593 In case of ndp or phy_err or Phy_err_during_mpdu_header 2594 this field will be set to 0 2595 2596 2597 2598 See definition in RX attention descriptor 2599 2600 <legal all> 2601 */ 2602 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 2603 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 2604 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 2605 2606 /* Description RX_MPDU_INFO_13_MORE_DATA 2607 2608 In case of ndp or phy_err or Phy_err_during_mpdu_header 2609 this field will be set to 0 2610 2611 2612 2613 See definition in RX attention descriptor 2614 2615 <legal all> 2616 */ 2617 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 2618 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 2619 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 2620 2621 /* Description RX_MPDU_INFO_13_EOSP 2622 2623 In case of ndp or phy_err or Phy_err_during_mpdu_header 2624 this field will be set to 0 2625 2626 2627 2628 See definition in RX attention descriptor 2629 2630 <legal all> 2631 */ 2632 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 2633 #define RX_MPDU_INFO_13_EOSP_LSB 24 2634 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 2635 2636 /* Description RX_MPDU_INFO_13_FRAGMENT_FLAG 2637 2638 In case of ndp or phy_err or Phy_err_during_mpdu_header 2639 this field will be set to 0 2640 2641 2642 2643 See definition in RX attention descriptor 2644 2645 <legal all> 2646 */ 2647 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 2648 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 2649 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 2650 2651 /* Description RX_MPDU_INFO_13_ORDER 2652 2653 In case of ndp or phy_err or Phy_err_during_mpdu_header 2654 this field will be set to 0 2655 2656 2657 2658 See definition in RX attention descriptor 2659 2660 2661 2662 <legal all> 2663 */ 2664 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 2665 #define RX_MPDU_INFO_13_ORDER_LSB 26 2666 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 2667 2668 /* Description RX_MPDU_INFO_13_U_APSD_TRIGGER 2669 2670 In case of ndp or phy_err or Phy_err_during_mpdu_header 2671 this field will be set to 0 2672 2673 2674 2675 See definition in RX attention descriptor 2676 2677 <legal all> 2678 */ 2679 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 2680 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 2681 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 2682 2683 /* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED 2684 2685 In case of ndp or phy_err or Phy_err_during_mpdu_header 2686 this field will be set to 0 2687 2688 2689 2690 See definition in RX attention descriptor 2691 2692 <legal all> 2693 */ 2694 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 2695 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 2696 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 2697 2698 /* Description RX_MPDU_INFO_13_DIRECTED 2699 2700 In case of ndp or phy_err or Phy_err_during_mpdu_header 2701 this field will be set to 0 2702 2703 2704 2705 See definition in RX attention descriptor 2706 2707 <legal all> 2708 */ 2709 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 2710 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 2711 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 2712 2713 /* Description RX_MPDU_INFO_13_RESERVED_13 2714 2715 <legal 0> 2716 */ 2717 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 2718 #define RX_MPDU_INFO_13_RESERVED_13_LSB 30 2719 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0xc0000000 2720 2721 /* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD 2722 2723 Field only valid when Mpdu_frame_control_valid is set 2724 2725 2726 2727 The frame control field of this received MPDU. 2728 2729 2730 2731 Field only valid when Ndp_frame and phy_err are NOT set 2732 2733 2734 2735 Bytes 0 + 1 of the received MPDU 2736 2737 <legal all> 2738 */ 2739 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 2740 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 2741 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 2742 2743 /* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD 2744 2745 Field only valid when Mpdu_duration_valid is set 2746 2747 2748 2749 The duration field of this received MPDU. 2750 2751 <legal all> 2752 */ 2753 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 2754 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 2755 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 2756 2757 /* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 2758 2759 Field only valid when mac_addr_ad1_valid is set 2760 2761 2762 2763 The Least Significant 4 bytes of the Received Frames MAC 2764 Address AD1 2765 2766 <legal all> 2767 */ 2768 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 2769 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 2770 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 2771 2772 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 2773 2774 Field only valid when mac_addr_ad1_valid is set 2775 2776 2777 2778 The 2 most significant bytes of the Received Frames MAC 2779 Address AD1 2780 2781 <legal all> 2782 */ 2783 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 2784 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 2785 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 2786 2787 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 2788 2789 Field only valid when mac_addr_ad2_valid is set 2790 2791 2792 2793 The Least Significant 2 bytes of the Received Frames MAC 2794 Address AD2 2795 2796 <legal all> 2797 */ 2798 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 2799 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 2800 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 2801 2802 /* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 2803 2804 Field only valid when mac_addr_ad2_valid is set 2805 2806 2807 2808 The 4 most significant bytes of the Received Frames MAC 2809 Address AD2 2810 2811 <legal all> 2812 */ 2813 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 2814 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 2815 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 2816 2817 /* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 2818 2819 Field only valid when mac_addr_ad3_valid is set 2820 2821 2822 2823 The Least Significant 4 bytes of the Received Frames MAC 2824 Address AD3 2825 2826 <legal all> 2827 */ 2828 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 2829 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 2830 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 2831 2832 /* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 2833 2834 Field only valid when mac_addr_ad3_valid is set 2835 2836 2837 2838 The 2 most significant bytes of the Received Frames MAC 2839 Address AD3 2840 2841 <legal all> 2842 */ 2843 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 2844 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 2845 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 2846 2847 /* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD 2848 2849 2850 2851 2852 The sequence control field of the MPDU 2853 2854 <legal all> 2855 */ 2856 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 2857 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 2858 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 2859 2860 /* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 2861 2862 Field only valid when mac_addr_ad4_valid is set 2863 2864 2865 2866 The Least Significant 4 bytes of the Received Frames MAC 2867 Address AD4 2868 2869 <legal all> 2870 */ 2871 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 2872 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 2873 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 2874 2875 /* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 2876 2877 Field only valid when mac_addr_ad4_valid is set 2878 2879 2880 2881 The 2 most significant bytes of the Received Frames MAC 2882 Address AD4 2883 2884 <legal all> 2885 */ 2886 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 2887 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 2888 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 2889 2890 /* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD 2891 2892 Field only valid when mpdu_qos_control_valid is set 2893 2894 2895 2896 The sequence control field of the MPDU 2897 2898 <legal all> 2899 */ 2900 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 2901 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 2902 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 2903 2904 /* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD 2905 2906 Field only valid when mpdu_qos_control_valid is set 2907 2908 2909 2910 The HT control field of the MPDU 2911 2912 <legal all> 2913 */ 2914 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 2915 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 2916 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 2917 2918 2919 #endif // _RX_MPDU_INFO_H_ 2920