1 /* 2 * Copyright (c) 2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ 20 #define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 filter_pass_mpdus[0], filter_pass_mpdus_fcs_ok[1], monitor_direct_mpdus[2], monitor_direct_mpdus_fcs_ok[3], monitor_other_mpdus[4], monitor_other_mpdus_fcs_ok[5], reserved_0[15:6], phy_ppdu_id[31:16] 29 // 30 // ################ END SUMMARY ################# 31 32 #define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 33 34 struct rx_rxpcu_classification_overview { 35 uint32_t filter_pass_mpdus : 1, //[0] 36 filter_pass_mpdus_fcs_ok : 1, //[1] 37 monitor_direct_mpdus : 1, //[2] 38 monitor_direct_mpdus_fcs_ok : 1, //[3] 39 monitor_other_mpdus : 1, //[4] 40 monitor_other_mpdus_fcs_ok : 1, //[5] 41 reserved_0 : 10, //[15:6] 42 phy_ppdu_id : 16; //[31:16] 43 }; 44 45 /* 46 47 filter_pass_mpdus 48 49 When set, at least one Filter Pass MPDU has been 50 received. FCS might or might not have been passing 51 52 <legal all> 53 54 filter_pass_mpdus_fcs_ok 55 56 When set, at least one Filter Pass MPDU has been 57 received that has a correct FCS. 58 59 <legal all> 60 61 monitor_direct_mpdus 62 63 When set, at least one Monitor Direct MPDU has been 64 received. FCS might or might not have been passing 65 66 <legal all> 67 68 monitor_direct_mpdus_fcs_ok 69 70 When set, at least one Monitor Direct MPDU has been 71 received that has a correct FCS. 72 73 <legal all> 74 75 monitor_other_mpdus 76 77 When set, at least one Monitor Direct MPDU has been 78 received. FCS might or might not have been passing 79 80 <legal all> 81 82 monitor_other_mpdus_fcs_ok 83 84 When set, at least one Monitor Direct MPDU has been 85 received that has a correct FCS. 86 87 <legal all> 88 89 reserved_0 90 91 <legal 0> 92 93 phy_ppdu_id 94 95 A ppdu counter value that PHY increments for every PPDU 96 received. The counter value wraps around 97 98 <legal all> 99 */ 100 101 102 /* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS 103 104 When set, at least one Filter Pass MPDU has been 105 received. FCS might or might not have been passing 106 107 <legal all> 108 */ 109 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000 110 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0 111 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001 112 113 /* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK 114 115 When set, at least one Filter Pass MPDU has been 116 received that has a correct FCS. 117 118 <legal all> 119 */ 120 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 121 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1 122 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 123 124 /* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS 125 126 When set, at least one Monitor Direct MPDU has been 127 received. FCS might or might not have been passing 128 129 <legal all> 130 */ 131 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 132 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2 133 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004 134 135 /* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK 136 137 When set, at least one Monitor Direct MPDU has been 138 received that has a correct FCS. 139 140 <legal all> 141 */ 142 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 143 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 144 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 145 146 /* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS 147 148 When set, at least one Monitor Direct MPDU has been 149 received. FCS might or might not have been passing 150 151 <legal all> 152 */ 153 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 154 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4 155 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010 156 157 /* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK 158 159 When set, at least one Monitor Direct MPDU has been 160 received that has a correct FCS. 161 162 <legal all> 163 */ 164 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 165 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 166 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 167 168 /* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0 169 170 <legal 0> 171 */ 172 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000 173 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 6 174 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ffc0 175 176 /* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID 177 178 A ppdu counter value that PHY increments for every PPDU 179 received. The counter value wraps around 180 181 <legal all> 182 */ 183 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000 184 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16 185 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000 186 187 188 #endif // _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ 189