1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2017 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _PHYRX_PKT_END_INFO_H_ 20*5113495bSYour Name #define _PHYRX_PKT_END_INFO_H_ 21*5113495bSYour Name #if !defined(__ASSEMBLER__) 22*5113495bSYour Name #endif 23*5113495bSYour Name 24*5113495bSYour Name #include "rx_location_info.h" 25*5113495bSYour Name #include "rx_timing_offset_info.h" 26*5113495bSYour Name #include "receive_rssi_info.h" 27*5113495bSYour Name 28*5113495bSYour Name // ################ START SUMMARY ################# 29*5113495bSYour Name // 30*5113495bSYour Name // Dword Fields 31*5113495bSYour Name // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[31:6] 32*5113495bSYour Name // 1 phy_timestamp_1_lower_32[31:0] 33*5113495bSYour Name // 2 phy_timestamp_1_upper_32[31:0] 34*5113495bSYour Name // 3 phy_timestamp_2_lower_32[31:0] 35*5113495bSYour Name // 4 phy_timestamp_2_upper_32[31:0] 36*5113495bSYour Name // 5-13 struct rx_location_info rx_location_info_details; 37*5113495bSYour Name // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 38*5113495bSYour Name // 15-30 struct receive_rssi_info post_rssi_info_details; 39*5113495bSYour Name // 31 phy_sw_status_31_0[31:0] 40*5113495bSYour Name // 32 phy_sw_status_63_32[31:0] 41*5113495bSYour Name // 42*5113495bSYour Name // ################ END SUMMARY ################# 43*5113495bSYour Name 44*5113495bSYour Name #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 45*5113495bSYour Name 46*5113495bSYour Name struct phyrx_pkt_end_info { 47*5113495bSYour Name uint32_t phy_internal_nap : 1, //[0] 48*5113495bSYour Name location_info_valid : 1, //[1] 49*5113495bSYour Name timing_info_valid : 1, //[2] 50*5113495bSYour Name rssi_info_valid : 1, //[3] 51*5113495bSYour Name rx_frame_correction_needed : 1, //[4] 52*5113495bSYour Name frameless_frame_received : 1, //[5] 53*5113495bSYour Name reserved_0a : 26; //[31:6] 54*5113495bSYour Name uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 55*5113495bSYour Name uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 56*5113495bSYour Name uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 57*5113495bSYour Name uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 58*5113495bSYour Name struct rx_location_info rx_location_info_details; 59*5113495bSYour Name struct rx_timing_offset_info rx_timing_offset_info_details; 60*5113495bSYour Name struct receive_rssi_info post_rssi_info_details; 61*5113495bSYour Name uint32_t phy_sw_status_31_0 : 32; //[31:0] 62*5113495bSYour Name uint32_t phy_sw_status_63_32 : 32; //[31:0] 63*5113495bSYour Name }; 64*5113495bSYour Name 65*5113495bSYour Name /* 66*5113495bSYour Name 67*5113495bSYour Name phy_internal_nap 68*5113495bSYour Name 69*5113495bSYour Name When set, PHY RX entered an internal NAP state, as PHY 70*5113495bSYour Name determined that this reception was not destined to this 71*5113495bSYour Name device 72*5113495bSYour Name 73*5113495bSYour Name location_info_valid 74*5113495bSYour Name 75*5113495bSYour Name Indicates that the RX_LOCATION_INFO structure later on 76*5113495bSYour Name in the TLV contains valid info 77*5113495bSYour Name 78*5113495bSYour Name timing_info_valid 79*5113495bSYour Name 80*5113495bSYour Name Indicates that the RX_TIMING_OFFSET_INFO structure later 81*5113495bSYour Name on in the TLV contains valid info 82*5113495bSYour Name 83*5113495bSYour Name rssi_info_valid 84*5113495bSYour Name 85*5113495bSYour Name Indicates that the RECEIVE_RSSI_INFO structure later on 86*5113495bSYour Name in the TLV contains valid info 87*5113495bSYour Name 88*5113495bSYour Name rx_frame_correction_needed 89*5113495bSYour Name 90*5113495bSYour Name When clear, no action is needed in the MAC. 91*5113495bSYour Name 92*5113495bSYour Name 93*5113495bSYour Name 94*5113495bSYour Name When set, the falling edge of the rx_frame happened 4us 95*5113495bSYour Name too late. MAC will need to compensate for this delay in 96*5113495bSYour Name order to maintain proper SIFS timing and/or not to get 97*5113495bSYour Name de-slotted. 98*5113495bSYour Name 99*5113495bSYour Name 100*5113495bSYour Name 101*5113495bSYour Name PHY uses this for very short 11a frames. 102*5113495bSYour Name 103*5113495bSYour Name 104*5113495bSYour Name 105*5113495bSYour Name When set, PHY will have passed this TLV to the MAC up to 106*5113495bSYour Name 8 us into the 'real SIFS' time, and thus within 4us from the 107*5113495bSYour Name falling edge of the rx_frame. 108*5113495bSYour Name 109*5113495bSYour Name 110*5113495bSYour Name 111*5113495bSYour Name <legal all> 112*5113495bSYour Name 113*5113495bSYour Name frameless_frame_received 114*5113495bSYour Name 115*5113495bSYour Name When set, PHY has received the 'frameless frame' . Can 116*5113495bSYour Name be used in the 'MU-RTS -CTS exchange where CTS reception can 117*5113495bSYour Name be problematic. 118*5113495bSYour Name 119*5113495bSYour Name <legal all> 120*5113495bSYour Name 121*5113495bSYour Name reserved_0a 122*5113495bSYour Name 123*5113495bSYour Name <legal 0> 124*5113495bSYour Name 125*5113495bSYour Name phy_timestamp_1_lower_32 126*5113495bSYour Name 127*5113495bSYour Name TODO PHY: cleanup descriptionThe PHY timestamp in the 128*5113495bSYour Name AMPI of the first rising edge of rx_clear_pri after 129*5113495bSYour Name TX_PHY_DESC. . This field should set to 0 by the PHY and 130*5113495bSYour Name should be updated by the AMPI before being forwarded to the 131*5113495bSYour Name rest of the MAC. This field indicates the lower 32 bits of 132*5113495bSYour Name the timestamp 133*5113495bSYour Name 134*5113495bSYour Name phy_timestamp_1_upper_32 135*5113495bSYour Name 136*5113495bSYour Name TODO PHY: cleanup description 137*5113495bSYour Name 138*5113495bSYour Name The PHY timestamp in the AMPI of the first rising edge 139*5113495bSYour Name of rx_clear_pri after TX_PHY_DESC. This field should set to 140*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 141*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 142*5113495bSYour Name upper 32 bits of the timestamp 143*5113495bSYour Name 144*5113495bSYour Name phy_timestamp_2_lower_32 145*5113495bSYour Name 146*5113495bSYour Name TODO PHY: cleanup description 147*5113495bSYour Name 148*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 149*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 150*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 151*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 152*5113495bSYour Name lower 32 bits of the timestamp 153*5113495bSYour Name 154*5113495bSYour Name phy_timestamp_2_upper_32 155*5113495bSYour Name 156*5113495bSYour Name TODO PHY: cleanup description 157*5113495bSYour Name 158*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 159*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 160*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 161*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 162*5113495bSYour Name upper 32 bits of the timestamp 163*5113495bSYour Name 164*5113495bSYour Name struct rx_location_info rx_location_info_details 165*5113495bSYour Name 166*5113495bSYour Name Overview of location related info 167*5113495bSYour Name 168*5113495bSYour Name struct rx_timing_offset_info rx_timing_offset_info_details 169*5113495bSYour Name 170*5113495bSYour Name Overview of timing offset related info 171*5113495bSYour Name 172*5113495bSYour Name struct receive_rssi_info post_rssi_info_details 173*5113495bSYour Name 174*5113495bSYour Name Overview of the post-RSSI values. 175*5113495bSYour Name 176*5113495bSYour Name phy_sw_status_31_0 177*5113495bSYour Name 178*5113495bSYour Name Some PHY micro code status that can be put in here. 179*5113495bSYour Name Details of definition within SW specification 180*5113495bSYour Name 181*5113495bSYour Name This field can be used for debugging, FW - SW message 182*5113495bSYour Name exchange, etc. 183*5113495bSYour Name 184*5113495bSYour Name It could for example be a pointer to a DDR memory 185*5113495bSYour Name location where PHY FW put some debug info. 186*5113495bSYour Name 187*5113495bSYour Name <legal all> 188*5113495bSYour Name 189*5113495bSYour Name phy_sw_status_63_32 190*5113495bSYour Name 191*5113495bSYour Name Some PHY micro code status that can be put in here. 192*5113495bSYour Name Details of definition within SW specification 193*5113495bSYour Name 194*5113495bSYour Name This field can be used for debugging, FW - SW message 195*5113495bSYour Name exchange, etc. 196*5113495bSYour Name 197*5113495bSYour Name It could for example be a pointer to a DDR memory 198*5113495bSYour Name location where PHY FW put some debug info. 199*5113495bSYour Name 200*5113495bSYour Name <legal all> 201*5113495bSYour Name */ 202*5113495bSYour Name 203*5113495bSYour Name 204*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP 205*5113495bSYour Name 206*5113495bSYour Name When set, PHY RX entered an internal NAP state, as PHY 207*5113495bSYour Name determined that this reception was not destined to this 208*5113495bSYour Name device 209*5113495bSYour Name */ 210*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 211*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 212*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 213*5113495bSYour Name 214*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID 215*5113495bSYour Name 216*5113495bSYour Name Indicates that the RX_LOCATION_INFO structure later on 217*5113495bSYour Name in the TLV contains valid info 218*5113495bSYour Name */ 219*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 220*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 221*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 222*5113495bSYour Name 223*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID 224*5113495bSYour Name 225*5113495bSYour Name Indicates that the RX_TIMING_OFFSET_INFO structure later 226*5113495bSYour Name on in the TLV contains valid info 227*5113495bSYour Name */ 228*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 229*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 230*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 231*5113495bSYour Name 232*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID 233*5113495bSYour Name 234*5113495bSYour Name Indicates that the RECEIVE_RSSI_INFO structure later on 235*5113495bSYour Name in the TLV contains valid info 236*5113495bSYour Name */ 237*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 238*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 239*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 240*5113495bSYour Name 241*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED 242*5113495bSYour Name 243*5113495bSYour Name When clear, no action is needed in the MAC. 244*5113495bSYour Name 245*5113495bSYour Name 246*5113495bSYour Name 247*5113495bSYour Name When set, the falling edge of the rx_frame happened 4us 248*5113495bSYour Name too late. MAC will need to compensate for this delay in 249*5113495bSYour Name order to maintain proper SIFS timing and/or not to get 250*5113495bSYour Name de-slotted. 251*5113495bSYour Name 252*5113495bSYour Name 253*5113495bSYour Name 254*5113495bSYour Name PHY uses this for very short 11a frames. 255*5113495bSYour Name 256*5113495bSYour Name 257*5113495bSYour Name 258*5113495bSYour Name When set, PHY will have passed this TLV to the MAC up to 259*5113495bSYour Name 8 us into the 'real SIFS' time, and thus within 4us from the 260*5113495bSYour Name falling edge of the rx_frame. 261*5113495bSYour Name 262*5113495bSYour Name 263*5113495bSYour Name 264*5113495bSYour Name <legal all> 265*5113495bSYour Name */ 266*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 267*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 268*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 269*5113495bSYour Name 270*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED 271*5113495bSYour Name 272*5113495bSYour Name When set, PHY has received the 'frameless frame' . Can 273*5113495bSYour Name be used in the 'MU-RTS -CTS exchange where CTS reception can 274*5113495bSYour Name be problematic. 275*5113495bSYour Name 276*5113495bSYour Name <legal all> 277*5113495bSYour Name */ 278*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 279*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 280*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 281*5113495bSYour Name 282*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_0_RESERVED_0A 283*5113495bSYour Name 284*5113495bSYour Name <legal 0> 285*5113495bSYour Name */ 286*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 287*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 288*5113495bSYour Name #define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0xffffffc0 289*5113495bSYour Name 290*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 291*5113495bSYour Name 292*5113495bSYour Name TODO PHY: cleanup descriptionThe PHY timestamp in the 293*5113495bSYour Name AMPI of the first rising edge of rx_clear_pri after 294*5113495bSYour Name TX_PHY_DESC. . This field should set to 0 by the PHY and 295*5113495bSYour Name should be updated by the AMPI before being forwarded to the 296*5113495bSYour Name rest of the MAC. This field indicates the lower 32 bits of 297*5113495bSYour Name the timestamp 298*5113495bSYour Name */ 299*5113495bSYour Name #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 300*5113495bSYour Name #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 301*5113495bSYour Name #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 302*5113495bSYour Name 303*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 304*5113495bSYour Name 305*5113495bSYour Name TODO PHY: cleanup description 306*5113495bSYour Name 307*5113495bSYour Name The PHY timestamp in the AMPI of the first rising edge 308*5113495bSYour Name of rx_clear_pri after TX_PHY_DESC. This field should set to 309*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 310*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 311*5113495bSYour Name upper 32 bits of the timestamp 312*5113495bSYour Name */ 313*5113495bSYour Name #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 314*5113495bSYour Name #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 315*5113495bSYour Name #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 316*5113495bSYour Name 317*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 318*5113495bSYour Name 319*5113495bSYour Name TODO PHY: cleanup description 320*5113495bSYour Name 321*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 322*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 323*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 324*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 325*5113495bSYour Name lower 32 bits of the timestamp 326*5113495bSYour Name */ 327*5113495bSYour Name #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 328*5113495bSYour Name #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 329*5113495bSYour Name #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 330*5113495bSYour Name 331*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 332*5113495bSYour Name 333*5113495bSYour Name TODO PHY: cleanup description 334*5113495bSYour Name 335*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 336*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 337*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 338*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 339*5113495bSYour Name upper 32 bits of the timestamp 340*5113495bSYour Name */ 341*5113495bSYour Name #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 342*5113495bSYour Name #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 343*5113495bSYour Name #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 344*5113495bSYour Name #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000014 345*5113495bSYour Name #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 346*5113495bSYour Name #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 347*5113495bSYour Name #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000018 348*5113495bSYour Name #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 349*5113495bSYour Name #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 350*5113495bSYour Name #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000001c 351*5113495bSYour Name #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 352*5113495bSYour Name #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 353*5113495bSYour Name #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000020 354*5113495bSYour Name #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 355*5113495bSYour Name #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 356*5113495bSYour Name #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000024 357*5113495bSYour Name #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 358*5113495bSYour Name #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 359*5113495bSYour Name #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000028 360*5113495bSYour Name #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 361*5113495bSYour Name #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 362*5113495bSYour Name #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000002c 363*5113495bSYour Name #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 364*5113495bSYour Name #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 365*5113495bSYour Name #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000030 366*5113495bSYour Name #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 367*5113495bSYour Name #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 368*5113495bSYour Name #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000034 369*5113495bSYour Name #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 370*5113495bSYour Name #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 371*5113495bSYour Name #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_OFFSET 0x00000038 372*5113495bSYour Name #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_LSB 0 373*5113495bSYour Name #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_MASK 0xffffffff 374*5113495bSYour Name #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000003c 375*5113495bSYour Name #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 376*5113495bSYour Name #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 377*5113495bSYour Name #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000040 378*5113495bSYour Name #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 379*5113495bSYour Name #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 380*5113495bSYour Name #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000044 381*5113495bSYour Name #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 382*5113495bSYour Name #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 383*5113495bSYour Name #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000048 384*5113495bSYour Name #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 385*5113495bSYour Name #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 386*5113495bSYour Name #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000004c 387*5113495bSYour Name #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 388*5113495bSYour Name #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 389*5113495bSYour Name #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000050 390*5113495bSYour Name #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 391*5113495bSYour Name #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 392*5113495bSYour Name #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000054 393*5113495bSYour Name #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 394*5113495bSYour Name #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 395*5113495bSYour Name #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000058 396*5113495bSYour Name #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 397*5113495bSYour Name #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 398*5113495bSYour Name #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000005c 399*5113495bSYour Name #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 400*5113495bSYour Name #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 401*5113495bSYour Name #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000060 402*5113495bSYour Name #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 403*5113495bSYour Name #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 404*5113495bSYour Name #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000064 405*5113495bSYour Name #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 406*5113495bSYour Name #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 407*5113495bSYour Name #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000068 408*5113495bSYour Name #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 409*5113495bSYour Name #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 410*5113495bSYour Name #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000006c 411*5113495bSYour Name #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 412*5113495bSYour Name #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 413*5113495bSYour Name #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000070 414*5113495bSYour Name #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 415*5113495bSYour Name #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 416*5113495bSYour Name #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000074 417*5113495bSYour Name #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 418*5113495bSYour Name #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 419*5113495bSYour Name #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000078 420*5113495bSYour Name #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 421*5113495bSYour Name #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 422*5113495bSYour Name 423*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 424*5113495bSYour Name 425*5113495bSYour Name Some PHY micro code status that can be put in here. 426*5113495bSYour Name Details of definition within SW specification 427*5113495bSYour Name 428*5113495bSYour Name This field can be used for debugging, FW - SW message 429*5113495bSYour Name exchange, etc. 430*5113495bSYour Name 431*5113495bSYour Name It could for example be a pointer to a DDR memory 432*5113495bSYour Name location where PHY FW put some debug info. 433*5113495bSYour Name 434*5113495bSYour Name <legal all> 435*5113495bSYour Name */ 436*5113495bSYour Name #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 437*5113495bSYour Name #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 438*5113495bSYour Name #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 439*5113495bSYour Name 440*5113495bSYour Name /* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 441*5113495bSYour Name 442*5113495bSYour Name Some PHY micro code status that can be put in here. 443*5113495bSYour Name Details of definition within SW specification 444*5113495bSYour Name 445*5113495bSYour Name This field can be used for debugging, FW - SW message 446*5113495bSYour Name exchange, etc. 447*5113495bSYour Name 448*5113495bSYour Name It could for example be a pointer to a DDR memory 449*5113495bSYour Name location where PHY FW put some debug info. 450*5113495bSYour Name 451*5113495bSYour Name <legal all> 452*5113495bSYour Name */ 453*5113495bSYour Name #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 454*5113495bSYour Name #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 455*5113495bSYour Name #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 456*5113495bSYour Name 457*5113495bSYour Name 458*5113495bSYour Name #endif // _PHYRX_PKT_END_INFO_H_ 459