1 /* 2 * Copyright (c) 2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _PHYRX_PKT_END_INFO_H_ 20 #define _PHYRX_PKT_END_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "rx_location_info.h" 25 #include "rx_timing_offset_info.h" 26 #include "receive_rssi_info.h" 27 28 // ################ START SUMMARY ################# 29 // 30 // Dword Fields 31 // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[31:6] 32 // 1 phy_timestamp_1_lower_32[31:0] 33 // 2 phy_timestamp_1_upper_32[31:0] 34 // 3 phy_timestamp_2_lower_32[31:0] 35 // 4 phy_timestamp_2_upper_32[31:0] 36 // 5-13 struct rx_location_info rx_location_info_details; 37 // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 38 // 15-30 struct receive_rssi_info post_rssi_info_details; 39 // 31 phy_sw_status_31_0[31:0] 40 // 32 phy_sw_status_63_32[31:0] 41 // 42 // ################ END SUMMARY ################# 43 44 #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 45 46 struct phyrx_pkt_end_info { 47 uint32_t phy_internal_nap : 1, //[0] 48 location_info_valid : 1, //[1] 49 timing_info_valid : 1, //[2] 50 rssi_info_valid : 1, //[3] 51 rx_frame_correction_needed : 1, //[4] 52 frameless_frame_received : 1, //[5] 53 reserved_0a : 26; //[31:6] 54 uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 55 uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 56 uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 57 uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 58 struct rx_location_info rx_location_info_details; 59 struct rx_timing_offset_info rx_timing_offset_info_details; 60 struct receive_rssi_info post_rssi_info_details; 61 uint32_t phy_sw_status_31_0 : 32; //[31:0] 62 uint32_t phy_sw_status_63_32 : 32; //[31:0] 63 }; 64 65 /* 66 67 phy_internal_nap 68 69 When set, PHY RX entered an internal NAP state, as PHY 70 determined that this reception was not destined to this 71 device 72 73 location_info_valid 74 75 Indicates that the RX_LOCATION_INFO structure later on 76 in the TLV contains valid info 77 78 timing_info_valid 79 80 Indicates that the RX_TIMING_OFFSET_INFO structure later 81 on in the TLV contains valid info 82 83 rssi_info_valid 84 85 Indicates that the RECEIVE_RSSI_INFO structure later on 86 in the TLV contains valid info 87 88 rx_frame_correction_needed 89 90 When clear, no action is needed in the MAC. 91 92 93 94 When set, the falling edge of the rx_frame happened 4us 95 too late. MAC will need to compensate for this delay in 96 order to maintain proper SIFS timing and/or not to get 97 de-slotted. 98 99 100 101 PHY uses this for very short 11a frames. 102 103 104 105 When set, PHY will have passed this TLV to the MAC up to 106 8 us into the 'real SIFS' time, and thus within 4us from the 107 falling edge of the rx_frame. 108 109 110 111 <legal all> 112 113 frameless_frame_received 114 115 When set, PHY has received the 'frameless frame' . Can 116 be used in the 'MU-RTS -CTS exchange where CTS reception can 117 be problematic. 118 119 <legal all> 120 121 reserved_0a 122 123 <legal 0> 124 125 phy_timestamp_1_lower_32 126 127 TODO PHY: cleanup descriptionThe PHY timestamp in the 128 AMPI of the first rising edge of rx_clear_pri after 129 TX_PHY_DESC. . This field should set to 0 by the PHY and 130 should be updated by the AMPI before being forwarded to the 131 rest of the MAC. This field indicates the lower 32 bits of 132 the timestamp 133 134 phy_timestamp_1_upper_32 135 136 TODO PHY: cleanup description 137 138 The PHY timestamp in the AMPI of the first rising edge 139 of rx_clear_pri after TX_PHY_DESC. This field should set to 140 0 by the PHY and should be updated by the AMPI before being 141 forwarded to the rest of the MAC. This field indicates the 142 upper 32 bits of the timestamp 143 144 phy_timestamp_2_lower_32 145 146 TODO PHY: cleanup description 147 148 The PHY timestamp in the AMPI of the rising edge of 149 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 150 0 by the PHY and should be updated by the AMPI before being 151 forwarded to the rest of the MAC. This field indicates the 152 lower 32 bits of the timestamp 153 154 phy_timestamp_2_upper_32 155 156 TODO PHY: cleanup description 157 158 The PHY timestamp in the AMPI of the rising edge of 159 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 160 0 by the PHY and should be updated by the AMPI before being 161 forwarded to the rest of the MAC. This field indicates the 162 upper 32 bits of the timestamp 163 164 struct rx_location_info rx_location_info_details 165 166 Overview of location related info 167 168 struct rx_timing_offset_info rx_timing_offset_info_details 169 170 Overview of timing offset related info 171 172 struct receive_rssi_info post_rssi_info_details 173 174 Overview of the post-RSSI values. 175 176 phy_sw_status_31_0 177 178 Some PHY micro code status that can be put in here. 179 Details of definition within SW specification 180 181 This field can be used for debugging, FW - SW message 182 exchange, etc. 183 184 It could for example be a pointer to a DDR memory 185 location where PHY FW put some debug info. 186 187 <legal all> 188 189 phy_sw_status_63_32 190 191 Some PHY micro code status that can be put in here. 192 Details of definition within SW specification 193 194 This field can be used for debugging, FW - SW message 195 exchange, etc. 196 197 It could for example be a pointer to a DDR memory 198 location where PHY FW put some debug info. 199 200 <legal all> 201 */ 202 203 204 /* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP 205 206 When set, PHY RX entered an internal NAP state, as PHY 207 determined that this reception was not destined to this 208 device 209 */ 210 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 211 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 212 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 213 214 /* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID 215 216 Indicates that the RX_LOCATION_INFO structure later on 217 in the TLV contains valid info 218 */ 219 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 220 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 221 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 222 223 /* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID 224 225 Indicates that the RX_TIMING_OFFSET_INFO structure later 226 on in the TLV contains valid info 227 */ 228 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 229 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 230 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 231 232 /* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID 233 234 Indicates that the RECEIVE_RSSI_INFO structure later on 235 in the TLV contains valid info 236 */ 237 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 238 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 239 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 240 241 /* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED 242 243 When clear, no action is needed in the MAC. 244 245 246 247 When set, the falling edge of the rx_frame happened 4us 248 too late. MAC will need to compensate for this delay in 249 order to maintain proper SIFS timing and/or not to get 250 de-slotted. 251 252 253 254 PHY uses this for very short 11a frames. 255 256 257 258 When set, PHY will have passed this TLV to the MAC up to 259 8 us into the 'real SIFS' time, and thus within 4us from the 260 falling edge of the rx_frame. 261 262 263 264 <legal all> 265 */ 266 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 267 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 268 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 269 270 /* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED 271 272 When set, PHY has received the 'frameless frame' . Can 273 be used in the 'MU-RTS -CTS exchange where CTS reception can 274 be problematic. 275 276 <legal all> 277 */ 278 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 279 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 280 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 281 282 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0A 283 284 <legal 0> 285 */ 286 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 287 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 288 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0xffffffc0 289 290 /* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 291 292 TODO PHY: cleanup descriptionThe PHY timestamp in the 293 AMPI of the first rising edge of rx_clear_pri after 294 TX_PHY_DESC. . This field should set to 0 by the PHY and 295 should be updated by the AMPI before being forwarded to the 296 rest of the MAC. This field indicates the lower 32 bits of 297 the timestamp 298 */ 299 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 300 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 301 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 302 303 /* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 304 305 TODO PHY: cleanup description 306 307 The PHY timestamp in the AMPI of the first rising edge 308 of rx_clear_pri after TX_PHY_DESC. This field should set to 309 0 by the PHY and should be updated by the AMPI before being 310 forwarded to the rest of the MAC. This field indicates the 311 upper 32 bits of the timestamp 312 */ 313 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 314 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 315 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 316 317 /* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 318 319 TODO PHY: cleanup description 320 321 The PHY timestamp in the AMPI of the rising edge of 322 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 323 0 by the PHY and should be updated by the AMPI before being 324 forwarded to the rest of the MAC. This field indicates the 325 lower 32 bits of the timestamp 326 */ 327 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 328 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 329 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 330 331 /* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 332 333 TODO PHY: cleanup description 334 335 The PHY timestamp in the AMPI of the rising edge of 336 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 337 0 by the PHY and should be updated by the AMPI before being 338 forwarded to the rest of the MAC. This field indicates the 339 upper 32 bits of the timestamp 340 */ 341 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 342 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 343 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 344 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000014 345 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 346 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 347 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000018 348 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 349 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 350 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000001c 351 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 352 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 353 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000020 354 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 355 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 356 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000024 357 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 358 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 359 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000028 360 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 361 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 362 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000002c 363 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 364 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 365 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000030 366 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 367 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 368 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000034 369 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 370 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 371 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_OFFSET 0x00000038 372 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_LSB 0 373 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_MASK 0xffffffff 374 #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000003c 375 #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 376 #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 377 #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000040 378 #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 379 #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 380 #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000044 381 #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 382 #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 383 #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000048 384 #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 385 #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 386 #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000004c 387 #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 388 #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 389 #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000050 390 #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 391 #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 392 #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000054 393 #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 394 #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 395 #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000058 396 #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 397 #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 398 #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000005c 399 #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 400 #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 401 #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000060 402 #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 403 #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 404 #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000064 405 #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 406 #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 407 #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000068 408 #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 409 #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 410 #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000006c 411 #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 412 #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 413 #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000070 414 #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 415 #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 416 #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000074 417 #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 418 #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 419 #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000078 420 #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 421 #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 422 423 /* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 424 425 Some PHY micro code status that can be put in here. 426 Details of definition within SW specification 427 428 This field can be used for debugging, FW - SW message 429 exchange, etc. 430 431 It could for example be a pointer to a DDR memory 432 location where PHY FW put some debug info. 433 434 <legal all> 435 */ 436 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 437 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 438 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 439 440 /* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 441 442 Some PHY micro code status that can be put in here. 443 Details of definition within SW specification 444 445 This field can be used for debugging, FW - SW message 446 exchange, etc. 447 448 It could for example be a pointer to a DDR memory 449 location where PHY FW put some debug info. 450 451 <legal all> 452 */ 453 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 454 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 455 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 456 457 458 #endif // _PHYRX_PKT_END_INFO_H_ 459