1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 25 #define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_reo_status_header.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0-1 struct uniform_reo_status_header status_header; 35 // 2 threshold_index[1:0], reserved_2[31:2] 36 // 3 link_descriptor_counter0[23:0], reserved_3[31:24] 37 // 4 link_descriptor_counter1[23:0], reserved_4[31:24] 38 // 5 link_descriptor_counter2[23:0], reserved_5[31:24] 39 // 6 link_descriptor_counter_sum[25:0], reserved_6[31:26] 40 // 7 reserved_7[31:0] 41 // 8 reserved_8[31:0] 42 // 9 reserved_9a[31:0] 43 // 10 reserved_10a[31:0] 44 // 11 reserved_11a[31:0] 45 // 12 reserved_12a[31:0] 46 // 13 reserved_13a[31:0] 47 // 14 reserved_14a[31:0] 48 // 15 reserved_15a[31:0] 49 // 16 reserved_16a[31:0] 50 // 17 reserved_17a[31:0] 51 // 18 reserved_18a[31:0] 52 // 19 reserved_19a[31:0] 53 // 20 reserved_20a[31:0] 54 // 21 reserved_21a[31:0] 55 // 22 reserved_22a[31:0] 56 // 23 reserved_23a[31:0] 57 // 24 reserved_24a[27:0], looping_count[31:28] 58 // 59 // ################ END SUMMARY ################# 60 61 #define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25 62 63 struct reo_descriptor_threshold_reached_status { 64 struct uniform_reo_status_header status_header; 65 uint32_t threshold_index : 2, //[1:0] 66 reserved_2 : 30; //[31:2] 67 uint32_t link_descriptor_counter0 : 24, //[23:0] 68 reserved_3 : 8; //[31:24] 69 uint32_t link_descriptor_counter1 : 24, //[23:0] 70 reserved_4 : 8; //[31:24] 71 uint32_t link_descriptor_counter2 : 24, //[23:0] 72 reserved_5 : 8; //[31:24] 73 uint32_t link_descriptor_counter_sum : 26, //[25:0] 74 reserved_6 : 6; //[31:26] 75 uint32_t reserved_7 : 32; //[31:0] 76 uint32_t reserved_8 : 32; //[31:0] 77 uint32_t reserved_9a : 32; //[31:0] 78 uint32_t reserved_10a : 32; //[31:0] 79 uint32_t reserved_11a : 32; //[31:0] 80 uint32_t reserved_12a : 32; //[31:0] 81 uint32_t reserved_13a : 32; //[31:0] 82 uint32_t reserved_14a : 32; //[31:0] 83 uint32_t reserved_15a : 32; //[31:0] 84 uint32_t reserved_16a : 32; //[31:0] 85 uint32_t reserved_17a : 32; //[31:0] 86 uint32_t reserved_18a : 32; //[31:0] 87 uint32_t reserved_19a : 32; //[31:0] 88 uint32_t reserved_20a : 32; //[31:0] 89 uint32_t reserved_21a : 32; //[31:0] 90 uint32_t reserved_22a : 32; //[31:0] 91 uint32_t reserved_23a : 32; //[31:0] 92 uint32_t reserved_24a : 28, //[27:0] 93 looping_count : 4; //[31:28] 94 }; 95 96 /* 97 98 struct uniform_reo_status_header status_header 99 100 Consumer: SW 101 102 Producer: REO 103 104 105 106 Details that can link this status with the original 107 command. It also contains info on how long REO took to 108 execute this command. 109 110 threshold_index 111 112 The index of the threshold register whose value got 113 reached 114 115 116 117 <enum 0 reo_desc_counter0_threshold> 118 119 <enum 1 reo_desc_counter1_threshold> 120 121 <enum 2 reo_desc_counter2_threshold> 122 123 <enum 3 reo_desc_counter_sum_threshold> 124 125 126 127 <legal all> 128 129 reserved_2 130 131 <legal 0> 132 133 link_descriptor_counter0 134 135 Value of this counter at generation of this message 136 137 <legal all> 138 139 reserved_3 140 141 <legal 0> 142 143 link_descriptor_counter1 144 145 Value of this counter at generation of this message 146 147 <legal all> 148 149 reserved_4 150 151 <legal 0> 152 153 link_descriptor_counter2 154 155 Value of this counter at generation of this message 156 157 <legal all> 158 159 reserved_5 160 161 <legal 0> 162 163 link_descriptor_counter_sum 164 165 Value of this counter at generation of this message 166 167 <legal all> 168 169 reserved_6 170 171 <legal 0> 172 173 reserved_7 174 175 <legal 0> 176 177 reserved_8 178 179 <legal 0> 180 181 reserved_9a 182 183 <legal 0> 184 185 reserved_10a 186 187 <legal 0> 188 189 reserved_11a 190 191 <legal 0> 192 193 reserved_12a 194 195 <legal 0> 196 197 reserved_13a 198 199 <legal 0> 200 201 reserved_14a 202 203 <legal 0> 204 205 reserved_15a 206 207 <legal 0> 208 209 reserved_16a 210 211 <legal 0> 212 213 reserved_17a 214 215 <legal 0> 216 217 reserved_18a 218 219 <legal 0> 220 221 reserved_19a 222 223 <legal 0> 224 225 reserved_20a 226 227 <legal 0> 228 229 reserved_21a 230 231 <legal 0> 232 233 reserved_22a 234 235 <legal 0> 236 237 reserved_23a 238 239 <legal 0> 240 241 reserved_24a 242 243 <legal 0> 244 245 looping_count 246 247 A count value that indicates the number of times the 248 producer of entries into this Ring has looped around the 249 ring. 250 251 At initialization time, this value is set to 0. On the 252 first loop, this value is set to 1. After the max value is 253 reached allowed by the number of bits for this field, the 254 count value continues with 0 again. 255 256 257 258 In case SW is the consumer of the ring entries, it can 259 use this field to figure out up to where the producer of 260 entries has created new entries. This eliminates the need to 261 check where the head pointer' of the ring is located once 262 the SW starts processing an interrupt indicating that new 263 entries have been put into this ring... 264 265 266 267 Also note that SW if it wants only needs to look at the 268 LSB bit of this count value. 269 270 <legal all> 271 */ 272 273 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000 274 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 275 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff 276 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004 277 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 278 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff 279 280 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX 281 282 The index of the threshold register whose value got 283 reached 284 285 286 287 <enum 0 reo_desc_counter0_threshold> 288 289 <enum 1 reo_desc_counter1_threshold> 290 291 <enum 2 reo_desc_counter2_threshold> 292 293 <enum 3 reo_desc_counter_sum_threshold> 294 295 296 297 <legal all> 298 */ 299 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008 300 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0 301 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003 302 303 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2 304 305 <legal 0> 306 */ 307 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008 308 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2 309 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc 310 311 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0 312 313 Value of this counter at generation of this message 314 315 <legal all> 316 */ 317 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c 318 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0 319 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff 320 321 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3 322 323 <legal 0> 324 */ 325 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c 326 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24 327 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000 328 329 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1 330 331 Value of this counter at generation of this message 332 333 <legal all> 334 */ 335 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010 336 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0 337 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff 338 339 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4 340 341 <legal 0> 342 */ 343 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010 344 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24 345 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000 346 347 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2 348 349 Value of this counter at generation of this message 350 351 <legal all> 352 */ 353 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014 354 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0 355 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff 356 357 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5 358 359 <legal 0> 360 */ 361 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014 362 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24 363 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000 364 365 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM 366 367 Value of this counter at generation of this message 368 369 <legal all> 370 */ 371 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018 372 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 373 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff 374 375 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6 376 377 <legal 0> 378 */ 379 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018 380 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26 381 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000 382 383 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7 384 385 <legal 0> 386 */ 387 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c 388 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0 389 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff 390 391 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8 392 393 <legal 0> 394 */ 395 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020 396 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0 397 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff 398 399 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A 400 401 <legal 0> 402 */ 403 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024 404 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0 405 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff 406 407 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A 408 409 <legal 0> 410 */ 411 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028 412 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0 413 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff 414 415 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A 416 417 <legal 0> 418 */ 419 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c 420 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0 421 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff 422 423 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A 424 425 <legal 0> 426 */ 427 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030 428 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0 429 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff 430 431 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A 432 433 <legal 0> 434 */ 435 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034 436 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0 437 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff 438 439 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A 440 441 <legal 0> 442 */ 443 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038 444 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0 445 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff 446 447 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A 448 449 <legal 0> 450 */ 451 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c 452 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0 453 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff 454 455 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A 456 457 <legal 0> 458 */ 459 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040 460 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0 461 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff 462 463 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A 464 465 <legal 0> 466 */ 467 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044 468 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0 469 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff 470 471 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A 472 473 <legal 0> 474 */ 475 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048 476 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0 477 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff 478 479 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A 480 481 <legal 0> 482 */ 483 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c 484 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0 485 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff 486 487 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A 488 489 <legal 0> 490 */ 491 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050 492 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0 493 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff 494 495 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A 496 497 <legal 0> 498 */ 499 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054 500 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0 501 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff 502 503 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A 504 505 <legal 0> 506 */ 507 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058 508 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0 509 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff 510 511 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A 512 513 <legal 0> 514 */ 515 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c 516 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0 517 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff 518 519 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A 520 521 <legal 0> 522 */ 523 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060 524 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0 525 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff 526 527 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT 528 529 A count value that indicates the number of times the 530 producer of entries into this Ring has looped around the 531 ring. 532 533 At initialization time, this value is set to 0. On the 534 first loop, this value is set to 1. After the max value is 535 reached allowed by the number of bits for this field, the 536 count value continues with 0 again. 537 538 539 540 In case SW is the consumer of the ring entries, it can 541 use this field to figure out up to where the producer of 542 entries has created new entries. This eliminates the need to 543 check where the head pointer' of the ring is located once 544 the SW starts processing an interrupt indicating that new 545 entries have been put into this ring... 546 547 548 549 Also note that SW if it wants only needs to look at the 550 LSB bit of this count value. 551 552 <legal all> 553 */ 554 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 555 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28 556 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 557 558 559 #endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 560