1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_ENTRANCE_RING_H_ 25 #define _REO_ENTRANCE_RING_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rx_mpdu_details.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; 35 // 4 rx_reo_queue_desc_addr_31_0[31:0] 36 // 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] 37 // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7] 38 // 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] 39 // 40 // ################ END SUMMARY ################# 41 42 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 43 44 struct reo_entrance_ring { 45 struct rx_mpdu_details reo_level_mpdu_frame_info; 46 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 47 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 48 rounded_mpdu_byte_count : 14, //[21:8] 49 reo_destination_indication : 5, //[26:22] 50 frameless_bar : 1, //[27] 51 reserved_5a : 4; //[31:28] 52 uint32_t rxdma_push_reason : 2, //[1:0] 53 rxdma_error_code : 5, //[6:2] 54 reserved_6a : 25; //[31:7] 55 uint32_t reserved_7a : 20, //[19:0] 56 ring_id : 8, //[27:20] 57 looping_count : 4; //[31:28] 58 }; 59 60 /* 61 62 struct rx_mpdu_details reo_level_mpdu_frame_info 63 64 Consumer: REO 65 66 Producer: RXDMA 67 68 69 70 Details related to the MPDU being pushed into the REO 71 72 rx_reo_queue_desc_addr_31_0 73 74 Consumer: REO 75 76 Producer: RXDMA 77 78 79 80 Address (lower 32 bits) of the REO queue descriptor. 81 82 <legal all> 83 84 rx_reo_queue_desc_addr_39_32 85 86 Consumer: REO 87 88 Producer: RXDMA 89 90 91 92 Address (upper 8 bits) of the REO queue descriptor. 93 94 <legal all> 95 96 rounded_mpdu_byte_count 97 98 An approximation of the number of bytes received in this 99 MPDU. 100 101 Used to keeps stats on the amount of data flowing 102 through a queue. 103 104 <legal all> 105 106 reo_destination_indication 107 108 RXDMA copy the MPDU's first MSDU's destination 109 indication field here. This is used for REO to be able to 110 re-route the packet to a different SW destination ring if 111 the packet is detected as error in REO. 112 113 114 115 The ID of the REO exit ring where the MSDU frame shall 116 push after (MPDU level) reordering has finished. 117 118 119 120 <enum 0 reo_destination_tcl> Reo will push the frame 121 into the REO2TCL ring 122 123 <enum 1 reo_destination_sw1> Reo will push the frame 124 into the REO2SW1 ring 125 126 <enum 2 reo_destination_sw2> Reo will push the frame 127 into the REO2SW1 ring 128 129 <enum 3 reo_destination_sw3> Reo will push the frame 130 into the REO2SW1 ring 131 132 <enum 4 reo_destination_sw4> Reo will push the frame 133 into the REO2SW1 ring 134 135 <enum 5 reo_destination_release> Reo will push the frame 136 into the REO_release ring 137 138 <enum 6 reo_destination_fw> Reo will push the frame into 139 the REO2FW ring 140 141 <enum 7 reo_destination_7> REO remaps this 142 143 <enum 8 reo_destination_8> REO remaps this <enum 9 144 reo_destination_9> REO remaps this <enum 10 145 reo_destination_10> REO remaps this 146 147 <enum 11 reo_destination_11> REO remaps this 148 149 <enum 12 reo_destination_12> REO remaps this <enum 13 150 reo_destination_13> REO remaps this 151 152 <enum 14 reo_destination_14> REO remaps this 153 154 <enum 15 reo_destination_15> REO remaps this 155 156 <enum 16 reo_destination_16> REO remaps this 157 158 <enum 17 reo_destination_17> REO remaps this 159 160 <enum 18 reo_destination_18> REO remaps this 161 162 <enum 19 reo_destination_19> REO remaps this 163 164 <enum 20 reo_destination_20> REO remaps this 165 166 <enum 21 reo_destination_21> REO remaps this 167 168 <enum 22 reo_destination_22> REO remaps this 169 170 <enum 23 reo_destination_23> REO remaps this 171 172 <enum 24 reo_destination_24> REO remaps this 173 174 <enum 25 reo_destination_25> REO remaps this 175 176 <enum 26 reo_destination_26> REO remaps this 177 178 <enum 27 reo_destination_27> REO remaps this 179 180 <enum 28 reo_destination_28> REO remaps this 181 182 <enum 29 reo_destination_29> REO remaps this 183 184 <enum 30 reo_destination_30> REO remaps this 185 186 <enum 31 reo_destination_31> REO remaps this 187 188 189 190 <legal all> 191 192 frameless_bar 193 194 When set, this REO entrance ring struct contains BAR 195 info from a multi TID BAR frame. The original multi TID BAR 196 frame itself contained all the REO info for the first TID, 197 but all the subsequent TID info and their linkage to the REO 198 descriptors is passed down as 'frameless' BAR info. 199 200 201 202 The only fields valid in this descriptor when this bit 203 is set are: 204 205 Rx_reo_queue_desc_addr_31_0 206 207 RX_reo_queue_desc_addr_39_32 208 209 210 211 And within the 212 213 Reo_level_mpdu_frame_info: 214 215 Within Rx_mpdu_desc_info_details: 216 217 Mpdu_Sequence_number 218 219 BAR_frame 220 221 Peer_meta_data 222 223 All other fields shall be set to 0 224 225 226 227 <legal all> 228 229 reserved_5a 230 231 <legal 0> 232 233 rxdma_push_reason 234 235 Indicates why rxdma pushed the frame to this ring 236 237 238 239 <enum 0 rxdma_error_detected> RXDMA detected an error an 240 pushed this frame to this queue 241 242 <enum 1 rxdma_routing_instruction> RXDMA pushed the 243 frame to this queue per received routing instructions. No 244 error within RXDMA was detected 245 246 247 248 This field is ignored by REO. 249 250 <legal 0 - 1> 251 252 rxdma_error_code 253 254 Field only valid when 'rxdma_push_reason' set to 255 'rxdma_error_detected'. 256 257 258 259 This field is ignored by REO. 260 261 262 263 <enum 0 rxdma_overflow_err>MPDU frame is not complete 264 due to a FIFO overflow error in RXPCU. 265 266 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 267 due to receiving incomplete MPDU from the PHY 268 269 270 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 271 error or CRYPTO received an encrypted frame, but did not get 272 a valid corresponding key id in the peer entry. 273 274 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 275 error 276 277 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 278 unencrypted frame error when encrypted was expected 279 280 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 281 length error 282 283 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 284 number of MSDUs allowed in an MPDU got exceeded 285 286 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 287 error 288 289 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 290 parsing error 291 292 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 293 during SA search 294 295 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 296 during DA search 297 298 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 299 timeout during flow search 300 301 <enum 13 Rxdma_flush_request>RXDMA received a flush 302 request 303 304 reserved_6a 305 306 <legal 0> 307 308 reserved_7a 309 310 <legal 0> 311 312 ring_id 313 314 Consumer: SW/REO/DEBUG 315 316 Producer: SRNG (of RXDMA) 317 318 319 320 For debugging. 321 322 This field is filled in by the SRNG module. 323 324 It help to identify the ring that is being looked <legal 325 all> 326 327 looping_count 328 329 Consumer: SW/REO/DEBUG 330 331 Producer: SRNG (of RXDMA) 332 333 334 335 For debugging. 336 337 This field is filled in by the SRNG module. 338 339 340 341 A count value that indicates the number of times the 342 producer of entries into this Ring has looped around the 343 ring. 344 345 At initialization time, this value is set to 0. On the 346 first loop, this value is set to 1. After the max value is 347 reached allowed by the number of bits for this field, the 348 count value continues with 0 again. 349 350 351 352 In case SW is the consumer of the ring entries, it can 353 use this field to figure out up to where the producer of 354 entries has created new entries. This eliminates the need to 355 check where the head pointer' of the ring is located once 356 the SW starts processing an interrupt indicating that new 357 entries have been put into this ring... 358 359 360 361 Also note that SW if it wants only needs to look at the 362 LSB bit of this count value. 363 364 <legal all> 365 */ 366 367 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000 368 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 369 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff 370 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004 371 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 372 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff 373 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008 374 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 375 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff 376 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c 377 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 378 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff 379 380 /* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 381 382 Consumer: REO 383 384 Producer: RXDMA 385 386 387 388 Address (lower 32 bits) of the REO queue descriptor. 389 390 <legal all> 391 */ 392 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 393 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 394 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 395 396 /* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 397 398 Consumer: REO 399 400 Producer: RXDMA 401 402 403 404 Address (upper 8 bits) of the REO queue descriptor. 405 406 <legal all> 407 */ 408 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 409 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 410 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 411 412 /* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT 413 414 An approximation of the number of bytes received in this 415 MPDU. 416 417 Used to keeps stats on the amount of data flowing 418 through a queue. 419 420 <legal all> 421 */ 422 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 423 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 424 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 425 426 /* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION 427 428 RXDMA copy the MPDU's first MSDU's destination 429 indication field here. This is used for REO to be able to 430 re-route the packet to a different SW destination ring if 431 the packet is detected as error in REO. 432 433 434 435 The ID of the REO exit ring where the MSDU frame shall 436 push after (MPDU level) reordering has finished. 437 438 439 440 <enum 0 reo_destination_tcl> Reo will push the frame 441 into the REO2TCL ring 442 443 <enum 1 reo_destination_sw1> Reo will push the frame 444 into the REO2SW1 ring 445 446 <enum 2 reo_destination_sw2> Reo will push the frame 447 into the REO2SW1 ring 448 449 <enum 3 reo_destination_sw3> Reo will push the frame 450 into the REO2SW1 ring 451 452 <enum 4 reo_destination_sw4> Reo will push the frame 453 into the REO2SW1 ring 454 455 <enum 5 reo_destination_release> Reo will push the frame 456 into the REO_release ring 457 458 <enum 6 reo_destination_fw> Reo will push the frame into 459 the REO2FW ring 460 461 <enum 7 reo_destination_7> REO remaps this 462 463 <enum 8 reo_destination_8> REO remaps this <enum 9 464 reo_destination_9> REO remaps this <enum 10 465 reo_destination_10> REO remaps this 466 467 <enum 11 reo_destination_11> REO remaps this 468 469 <enum 12 reo_destination_12> REO remaps this <enum 13 470 reo_destination_13> REO remaps this 471 472 <enum 14 reo_destination_14> REO remaps this 473 474 <enum 15 reo_destination_15> REO remaps this 475 476 <enum 16 reo_destination_16> REO remaps this 477 478 <enum 17 reo_destination_17> REO remaps this 479 480 <enum 18 reo_destination_18> REO remaps this 481 482 <enum 19 reo_destination_19> REO remaps this 483 484 <enum 20 reo_destination_20> REO remaps this 485 486 <enum 21 reo_destination_21> REO remaps this 487 488 <enum 22 reo_destination_22> REO remaps this 489 490 <enum 23 reo_destination_23> REO remaps this 491 492 <enum 24 reo_destination_24> REO remaps this 493 494 <enum 25 reo_destination_25> REO remaps this 495 496 <enum 26 reo_destination_26> REO remaps this 497 498 <enum 27 reo_destination_27> REO remaps this 499 500 <enum 28 reo_destination_28> REO remaps this 501 502 <enum 29 reo_destination_29> REO remaps this 503 504 <enum 30 reo_destination_30> REO remaps this 505 506 <enum 31 reo_destination_31> REO remaps this 507 508 509 510 <legal all> 511 */ 512 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 513 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 514 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 515 516 /* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR 517 518 When set, this REO entrance ring struct contains BAR 519 info from a multi TID BAR frame. The original multi TID BAR 520 frame itself contained all the REO info for the first TID, 521 but all the subsequent TID info and their linkage to the REO 522 descriptors is passed down as 'frameless' BAR info. 523 524 525 526 The only fields valid in this descriptor when this bit 527 is set are: 528 529 Rx_reo_queue_desc_addr_31_0 530 531 RX_reo_queue_desc_addr_39_32 532 533 534 535 And within the 536 537 Reo_level_mpdu_frame_info: 538 539 Within Rx_mpdu_desc_info_details: 540 541 Mpdu_Sequence_number 542 543 BAR_frame 544 545 Peer_meta_data 546 547 All other fields shall be set to 0 548 549 550 551 <legal all> 552 */ 553 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 554 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 555 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 556 557 /* Description REO_ENTRANCE_RING_5_RESERVED_5A 558 559 <legal 0> 560 */ 561 #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 562 #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 563 #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 564 565 /* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON 566 567 Indicates why rxdma pushed the frame to this ring 568 569 570 571 <enum 0 rxdma_error_detected> RXDMA detected an error an 572 pushed this frame to this queue 573 574 <enum 1 rxdma_routing_instruction> RXDMA pushed the 575 frame to this queue per received routing instructions. No 576 error within RXDMA was detected 577 578 579 580 This field is ignored by REO. 581 582 <legal 0 - 1> 583 */ 584 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 585 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 586 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 587 588 /* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE 589 590 Field only valid when 'rxdma_push_reason' set to 591 'rxdma_error_detected'. 592 593 594 595 This field is ignored by REO. 596 597 598 599 <enum 0 rxdma_overflow_err>MPDU frame is not complete 600 due to a FIFO overflow error in RXPCU. 601 602 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 603 due to receiving incomplete MPDU from the PHY 604 605 606 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 607 error or CRYPTO received an encrypted frame, but did not get 608 a valid corresponding key id in the peer entry. 609 610 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 611 error 612 613 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 614 unencrypted frame error when encrypted was expected 615 616 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 617 length error 618 619 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 620 number of MSDUs allowed in an MPDU got exceeded 621 622 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 623 error 624 625 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 626 parsing error 627 628 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 629 during SA search 630 631 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 632 during DA search 633 634 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 635 timeout during flow search 636 637 <enum 13 Rxdma_flush_request>RXDMA received a flush 638 request 639 */ 640 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 641 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 642 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c 643 644 /* Description REO_ENTRANCE_RING_6_RESERVED_6A 645 646 <legal 0> 647 */ 648 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 649 #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 7 650 #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xffffff80 651 652 /* Description REO_ENTRANCE_RING_7_RESERVED_7A 653 654 <legal 0> 655 */ 656 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c 657 #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0 658 #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff 659 660 /* Description REO_ENTRANCE_RING_7_RING_ID 661 662 Consumer: SW/REO/DEBUG 663 664 Producer: SRNG (of RXDMA) 665 666 667 668 For debugging. 669 670 This field is filled in by the SRNG module. 671 672 It help to identify the ring that is being looked <legal 673 all> 674 */ 675 #define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c 676 #define REO_ENTRANCE_RING_7_RING_ID_LSB 20 677 #define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 678 679 /* Description REO_ENTRANCE_RING_7_LOOPING_COUNT 680 681 Consumer: SW/REO/DEBUG 682 683 Producer: SRNG (of RXDMA) 684 685 686 687 For debugging. 688 689 This field is filled in by the SRNG module. 690 691 692 693 A count value that indicates the number of times the 694 producer of entries into this Ring has looped around the 695 ring. 696 697 At initialization time, this value is set to 0. On the 698 first loop, this value is set to 1. After the max value is 699 reached allowed by the number of bits for this field, the 700 count value continues with 0 again. 701 702 703 704 In case SW is the consumer of the ring entries, it can 705 use this field to figure out up to where the producer of 706 entries has created new entries. This eliminates the need to 707 check where the head pointer' of the ring is located once 708 the SW starts processing an interrupt indicating that new 709 entries have been put into this ring... 710 711 712 713 Also note that SW if it wants only needs to look at the 714 LSB bit of this count value. 715 716 <legal all> 717 */ 718 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 719 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 720 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 721 722 723 #endif // _REO_ENTRANCE_RING_H_ 724