1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_FLUSH_QUEUE_H_ 25 #define _REO_FLUSH_QUEUE_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_reo_cmd_header.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct uniform_reo_cmd_header cmd_header; 35 // 1 flush_desc_addr_31_0[31:0] 36 // 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], reserved_2a[31:11] 37 // 3 reserved_3a[31:0] 38 // 4 reserved_4a[31:0] 39 // 5 reserved_5a[31:0] 40 // 6 reserved_6a[31:0] 41 // 7 reserved_7a[31:0] 42 // 8 reserved_8a[31:0] 43 // 44 // ################ END SUMMARY ################# 45 46 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 47 48 struct reo_flush_queue { 49 struct uniform_reo_cmd_header cmd_header; 50 uint32_t flush_desc_addr_31_0 : 32; //[31:0] 51 uint32_t flush_desc_addr_39_32 : 8, //[7:0] 52 block_desc_addr_usage_after_flush: 1, //[8] 53 block_resource_index : 2, //[10:9] 54 reserved_2a : 21; //[31:11] 55 uint32_t reserved_3a : 32; //[31:0] 56 uint32_t reserved_4a : 32; //[31:0] 57 uint32_t reserved_5a : 32; //[31:0] 58 uint32_t reserved_6a : 32; //[31:0] 59 uint32_t reserved_7a : 32; //[31:0] 60 uint32_t reserved_8a : 32; //[31:0] 61 }; 62 63 /* 64 65 struct uniform_reo_cmd_header cmd_header 66 67 Consumer: REO 68 69 Producer: SW 70 71 72 73 Details for command execution tracking purposes. 74 75 flush_desc_addr_31_0 76 77 Consumer: REO 78 79 Producer: SW 80 81 82 83 Address (lower 32 bits) of the descriptor to flush 84 85 <legal all> 86 87 flush_desc_addr_39_32 88 89 Consumer: REO 90 91 Producer: SW 92 93 94 95 Address (upper 8 bits) of the descriptor to flush 96 97 <legal all> 98 99 block_desc_addr_usage_after_flush 100 101 When set, REO shall not re-fetch this address till SW 102 explicitly unblocked this address 103 104 105 106 If the blocking resource was already used, this command 107 shall fail and an error is reported 108 109 110 111 <legal all> 112 113 block_resource_index 114 115 Field only valid when 'Block_desc_addr_usage_after_flush 116 ' is set. 117 118 119 120 Indicates which of the four blocking resources in REO 121 will be assigned for managing the blocking of this address. 122 123 <legal all> 124 125 reserved_2a 126 127 <legal 0> 128 129 reserved_3a 130 131 <legal 0> 132 133 reserved_4a 134 135 <legal 0> 136 137 reserved_5a 138 139 <legal 0> 140 141 reserved_6a 142 143 <legal 0> 144 145 reserved_7a 146 147 <legal 0> 148 149 reserved_8a 150 151 <legal 0> 152 */ 153 154 #define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000 155 #define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0 156 #define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff 157 158 /* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0 159 160 Consumer: REO 161 162 Producer: SW 163 164 165 166 Address (lower 32 bits) of the descriptor to flush 167 168 <legal all> 169 */ 170 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 171 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0 172 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff 173 174 /* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32 175 176 Consumer: REO 177 178 Producer: SW 179 180 181 182 Address (upper 8 bits) of the descriptor to flush 183 184 <legal all> 185 */ 186 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 187 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0 188 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff 189 190 /* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH 191 192 When set, REO shall not re-fetch this address till SW 193 explicitly unblocked this address 194 195 196 197 If the blocking resource was already used, this command 198 shall fail and an error is reported 199 200 201 202 <legal all> 203 */ 204 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 205 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 206 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 207 208 /* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX 209 210 Field only valid when 'Block_desc_addr_usage_after_flush 211 ' is set. 212 213 214 215 Indicates which of the four blocking resources in REO 216 will be assigned for managing the blocking of this address. 217 218 <legal all> 219 */ 220 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 221 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9 222 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600 223 224 /* Description REO_FLUSH_QUEUE_2_RESERVED_2A 225 226 <legal 0> 227 */ 228 #define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008 229 #define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 11 230 #define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff800 231 232 /* Description REO_FLUSH_QUEUE_3_RESERVED_3A 233 234 <legal 0> 235 */ 236 #define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 237 #define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0 238 #define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff 239 240 /* Description REO_FLUSH_QUEUE_4_RESERVED_4A 241 242 <legal 0> 243 */ 244 #define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 245 #define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0 246 #define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff 247 248 /* Description REO_FLUSH_QUEUE_5_RESERVED_5A 249 250 <legal 0> 251 */ 252 #define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014 253 #define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0 254 #define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff 255 256 /* Description REO_FLUSH_QUEUE_6_RESERVED_6A 257 258 <legal 0> 259 */ 260 #define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018 261 #define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0 262 #define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff 263 264 /* Description REO_FLUSH_QUEUE_7_RESERVED_7A 265 266 <legal 0> 267 */ 268 #define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c 269 #define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0 270 #define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff 271 272 /* Description REO_FLUSH_QUEUE_8_RESERVED_8A 273 274 <legal 0> 275 */ 276 #define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020 277 #define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0 278 #define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff 279 280 281 #endif // _REO_FLUSH_QUEUE_H_ 282