1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 25 #define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_reo_status_header.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0-1 struct uniform_reo_status_header status_header; 35 // 2 reserved_2a[31:0] 36 // 3 reserved_3a[31:0] 37 // 4 reserved_4a[31:0] 38 // 5 reserved_5a[31:0] 39 // 6 reserved_6a[31:0] 40 // 7 reserved_7a[31:0] 41 // 8 reserved_8a[31:0] 42 // 9 reserved_9a[31:0] 43 // 10 reserved_10a[31:0] 44 // 11 reserved_11a[31:0] 45 // 12 reserved_12a[31:0] 46 // 13 reserved_13a[31:0] 47 // 14 reserved_14a[31:0] 48 // 15 reserved_15a[31:0] 49 // 16 reserved_16a[31:0] 50 // 17 reserved_17a[31:0] 51 // 18 reserved_18a[31:0] 52 // 19 reserved_19a[31:0] 53 // 20 reserved_20a[31:0] 54 // 21 reserved_21a[31:0] 55 // 22 reserved_22a[31:0] 56 // 23 reserved_23a[31:0] 57 // 24 reserved_24a[27:0], looping_count[31:28] 58 // 59 // ################ END SUMMARY ################# 60 61 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25 62 63 struct reo_update_rx_reo_queue_status { 64 struct uniform_reo_status_header status_header; 65 uint32_t reserved_2a : 32; //[31:0] 66 uint32_t reserved_3a : 32; //[31:0] 67 uint32_t reserved_4a : 32; //[31:0] 68 uint32_t reserved_5a : 32; //[31:0] 69 uint32_t reserved_6a : 32; //[31:0] 70 uint32_t reserved_7a : 32; //[31:0] 71 uint32_t reserved_8a : 32; //[31:0] 72 uint32_t reserved_9a : 32; //[31:0] 73 uint32_t reserved_10a : 32; //[31:0] 74 uint32_t reserved_11a : 32; //[31:0] 75 uint32_t reserved_12a : 32; //[31:0] 76 uint32_t reserved_13a : 32; //[31:0] 77 uint32_t reserved_14a : 32; //[31:0] 78 uint32_t reserved_15a : 32; //[31:0] 79 uint32_t reserved_16a : 32; //[31:0] 80 uint32_t reserved_17a : 32; //[31:0] 81 uint32_t reserved_18a : 32; //[31:0] 82 uint32_t reserved_19a : 32; //[31:0] 83 uint32_t reserved_20a : 32; //[31:0] 84 uint32_t reserved_21a : 32; //[31:0] 85 uint32_t reserved_22a : 32; //[31:0] 86 uint32_t reserved_23a : 32; //[31:0] 87 uint32_t reserved_24a : 28, //[27:0] 88 looping_count : 4; //[31:28] 89 }; 90 91 /* 92 93 struct uniform_reo_status_header status_header 94 95 Consumer: SW 96 97 Producer: REO 98 99 100 101 Details that can link this status with the original 102 command. It also contains info on how long REO took to 103 execute this command. 104 105 reserved_2a 106 107 <legal 0> 108 109 reserved_3a 110 111 <legal 0> 112 113 reserved_4a 114 115 <legal 0> 116 117 reserved_5a 118 119 <legal 0> 120 121 reserved_6a 122 123 <legal 0> 124 125 reserved_7a 126 127 <legal 0> 128 129 reserved_8a 130 131 <legal 0> 132 133 reserved_9a 134 135 <legal 0> 136 137 reserved_10a 138 139 <legal 0> 140 141 reserved_11a 142 143 <legal 0> 144 145 reserved_12a 146 147 <legal 0> 148 149 reserved_13a 150 151 <legal 0> 152 153 reserved_14a 154 155 <legal 0> 156 157 reserved_15a 158 159 <legal 0> 160 161 reserved_16a 162 163 <legal 0> 164 165 reserved_17a 166 167 <legal 0> 168 169 reserved_18a 170 171 <legal 0> 172 173 reserved_19a 174 175 <legal 0> 176 177 reserved_20a 178 179 <legal 0> 180 181 reserved_21a 182 183 <legal 0> 184 185 reserved_22a 186 187 <legal 0> 188 189 reserved_23a 190 191 <legal 0> 192 193 reserved_24a 194 195 <legal 0> 196 197 looping_count 198 199 A count value that indicates the number of times the 200 producer of entries into this Ring has looped around the 201 ring. 202 203 At initialization time, this value is set to 0. On the 204 first loop, this value is set to 1. After the max value is 205 reached allowed by the number of bits for this field, the 206 count value continues with 0 again. 207 208 209 210 In case SW is the consumer of the ring entries, it can 211 use this field to figure out up to where the producer of 212 entries has created new entries. This eliminates the need to 213 check where the head pointer' of the ring is located once 214 the SW starts processing an interrupt indicating that new 215 entries have been put into this ring... 216 217 218 219 Also note that SW if it wants only needs to look at the 220 LSB bit of this count value. 221 222 <legal all> 223 */ 224 225 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000 226 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 227 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff 228 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004 229 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 230 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff 231 232 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A 233 234 <legal 0> 235 */ 236 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 237 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0 238 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff 239 240 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A 241 242 <legal 0> 243 */ 244 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c 245 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0 246 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff 247 248 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A 249 250 <legal 0> 251 */ 252 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 253 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0 254 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff 255 256 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A 257 258 <legal 0> 259 */ 260 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 261 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0 262 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff 263 264 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A 265 266 <legal 0> 267 */ 268 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 269 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0 270 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff 271 272 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A 273 274 <legal 0> 275 */ 276 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c 277 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0 278 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff 279 280 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A 281 282 <legal 0> 283 */ 284 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 285 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0 286 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff 287 288 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A 289 290 <legal 0> 291 */ 292 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 293 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0 294 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff 295 296 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A 297 298 <legal 0> 299 */ 300 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 301 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0 302 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff 303 304 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A 305 306 <legal 0> 307 */ 308 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c 309 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0 310 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff 311 312 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A 313 314 <legal 0> 315 */ 316 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 317 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0 318 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff 319 320 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A 321 322 <legal 0> 323 */ 324 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 325 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0 326 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff 327 328 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A 329 330 <legal 0> 331 */ 332 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 333 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0 334 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff 335 336 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A 337 338 <legal 0> 339 */ 340 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c 341 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0 342 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff 343 344 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A 345 346 <legal 0> 347 */ 348 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 349 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0 350 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff 351 352 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A 353 354 <legal 0> 355 */ 356 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 357 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0 358 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff 359 360 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A 361 362 <legal 0> 363 */ 364 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 365 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0 366 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff 367 368 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A 369 370 <legal 0> 371 */ 372 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c 373 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0 374 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff 375 376 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A 377 378 <legal 0> 379 */ 380 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 381 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0 382 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff 383 384 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A 385 386 <legal 0> 387 */ 388 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 389 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0 390 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff 391 392 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A 393 394 <legal 0> 395 */ 396 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 397 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0 398 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff 399 400 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A 401 402 <legal 0> 403 */ 404 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c 405 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0 406 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff 407 408 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A 409 410 <legal 0> 411 */ 412 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 413 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0 414 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff 415 416 /* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT 417 418 A count value that indicates the number of times the 419 producer of entries into this Ring has looped around the 420 ring. 421 422 At initialization time, this value is set to 0. On the 423 first loop, this value is set to 1. After the max value is 424 reached allowed by the number of bits for this field, the 425 count value continues with 0 again. 426 427 428 429 In case SW is the consumer of the ring entries, it can 430 use this field to figure out up to where the producer of 431 entries has created new entries. This eliminates the need to 432 check where the head pointer' of the ring is located once 433 the SW starts processing an interrupt indicating that new 434 entries have been put into this ring... 435 436 437 438 Also note that SW if it wants only needs to look at the 439 LSB bit of this count value. 440 441 <legal all> 442 */ 443 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 444 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 445 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 446 447 448 #endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 449