xref: /wlan-driver/fw-api/hw/qca6290/v2/rx_attention.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 //
20 // DO NOT EDIT!  This file is automatically generated
21 //               These definitions are tied to a particular hardware layout
22 
23 
24 #ifndef _RX_ATTENTION_H_
25 #define _RX_ATTENTION_H_
26 #if !defined(__ASSEMBLER__)
27 #endif
28 
29 
30 // ################ START SUMMARY #################
31 //
32 //	Dword	Fields
33 //	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
34 //	1	first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31]
35 //	2	flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31]
36 //
37 // ################ END SUMMARY #################
38 
39 #define NUM_OF_DWORDS_RX_ATTENTION 3
40 
41 struct rx_attention {
42              uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
43                       sw_frame_group_id               :  7, //[8:2]
44                       reserved_0                      :  7, //[15:9]
45                       phy_ppdu_id                     : 16; //[31:16]
46              uint32_t first_mpdu                      :  1, //[0]
47                       reserved_1a                     :  1, //[1]
48                       mcast_bcast                     :  1, //[2]
49                       ast_index_not_found             :  1, //[3]
50                       ast_index_timeout               :  1, //[4]
51                       power_mgmt                      :  1, //[5]
52                       non_qos                         :  1, //[6]
53                       null_data                       :  1, //[7]
54                       mgmt_type                       :  1, //[8]
55                       ctrl_type                       :  1, //[9]
56                       more_data                       :  1, //[10]
57                       eosp                            :  1, //[11]
58                       a_msdu_error                    :  1, //[12]
59                       fragment_flag                   :  1, //[13]
60                       order                           :  1, //[14]
61                       cce_match                       :  1, //[15]
62                       overflow_err                    :  1, //[16]
63                       msdu_length_err                 :  1, //[17]
64                       tcp_udp_chksum_fail             :  1, //[18]
65                       ip_chksum_fail                  :  1, //[19]
66                       sa_idx_invalid                  :  1, //[20]
67                       da_idx_invalid                  :  1, //[21]
68                       reserved_1b                     :  1, //[22]
69                       rx_in_tx_decrypt_byp            :  1, //[23]
70                       encrypt_required                :  1, //[24]
71                       directed                        :  1, //[25]
72                       buffer_fragment                 :  1, //[26]
73                       mpdu_length_err                 :  1, //[27]
74                       tkip_mic_err                    :  1, //[28]
75                       decrypt_err                     :  1, //[29]
76                       unencrypted_frame_err           :  1, //[30]
77                       fcs_err                         :  1; //[31]
78              uint32_t flow_idx_timeout                :  1, //[0]
79                       flow_idx_invalid                :  1, //[1]
80                       wifi_parser_error               :  1, //[2]
81                       amsdu_parser_error              :  1, //[3]
82                       sa_idx_timeout                  :  1, //[4]
83                       da_idx_timeout                  :  1, //[5]
84                       msdu_limit_error                :  1, //[6]
85                       da_is_valid                     :  1, //[7]
86                       da_is_mcbc                      :  1, //[8]
87                       sa_is_valid                     :  1, //[9]
88                       decrypt_status_code             :  3, //[12:10]
89                       rx_bitmap_not_updated           :  1, //[13]
90                       reserved_2                      : 17, //[30:14]
91                       msdu_done                       :  1; //[31]
92 };
93 
94 /*
95 
96 rxpcu_mpdu_filter_in_category
97 
98 			Field indicates what the reason was that this MPDU frame
99 			was allowed to come into the receive path by RXPCU
100 
101 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
102 			frame filter programming of rxpcu
103 
104 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
105 			regular frame filter and would have been dropped, were it
106 			not for the frame fitting into the 'monitor_client'
107 			category.
108 
109 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
110 			regular frame filter and also did not pass the
111 			rxpcu_monitor_client filter. It would have been dropped
112 			accept that it did pass the 'monitor_other' category.
113 
114 			<legal 0-2>
115 
116 sw_frame_group_id
117 
118 			SW processes frames based on certain classifications.
119 			This field indicates to what sw classification this MPDU is
120 			mapped.
121 
122 			The classification is given in priority order
123 
124 
125 
126 			<enum 0 sw_frame_group_NDP_frame>
127 
128 
129 
130 			<enum 1 sw_frame_group_Multicast_data>
131 
132 			<enum 2 sw_frame_group_Unicast_data>
133 
134 			<enum 3 sw_frame_group_Null_data > This includes mpdus
135 			of type Data Null as well as QoS Data Null
136 
137 
138 
139 			<enum 4 sw_frame_group_mgmt_0000 >
140 
141 			<enum 5 sw_frame_group_mgmt_0001 >
142 
143 			<enum 6 sw_frame_group_mgmt_0010 >
144 
145 			<enum 7 sw_frame_group_mgmt_0011 >
146 
147 			<enum 8 sw_frame_group_mgmt_0100 >
148 
149 			<enum 9 sw_frame_group_mgmt_0101 >
150 
151 			<enum 10 sw_frame_group_mgmt_0110 >
152 
153 			<enum 11 sw_frame_group_mgmt_0111 >
154 
155 			<enum 12 sw_frame_group_mgmt_1000 >
156 
157 			<enum 13 sw_frame_group_mgmt_1001 >
158 
159 			<enum 14 sw_frame_group_mgmt_1010 >
160 
161 			<enum 15 sw_frame_group_mgmt_1011 >
162 
163 			<enum 16 sw_frame_group_mgmt_1100 >
164 
165 			<enum 17 sw_frame_group_mgmt_1101 >
166 
167 			<enum 18 sw_frame_group_mgmt_1110 >
168 
169 			<enum 19 sw_frame_group_mgmt_1111 >
170 
171 
172 
173 			<enum 20 sw_frame_group_ctrl_0000 >
174 
175 			<enum 21 sw_frame_group_ctrl_0001 >
176 
177 			<enum 22 sw_frame_group_ctrl_0010 >
178 
179 			<enum 23 sw_frame_group_ctrl_0011 >
180 
181 			<enum 24 sw_frame_group_ctrl_0100 >
182 
183 			<enum 25 sw_frame_group_ctrl_0101 >
184 
185 			<enum 26 sw_frame_group_ctrl_0110 >
186 
187 			<enum 27 sw_frame_group_ctrl_0111 >
188 
189 			<enum 28 sw_frame_group_ctrl_1000 >
190 
191 			<enum 29 sw_frame_group_ctrl_1001 >
192 
193 			<enum 30 sw_frame_group_ctrl_1010 >
194 
195 			<enum 31 sw_frame_group_ctrl_1011 >
196 
197 			<enum 32 sw_frame_group_ctrl_1100 >
198 
199 			<enum 33 sw_frame_group_ctrl_1101 >
200 
201 			<enum 34 sw_frame_group_ctrl_1110 >
202 
203 			<enum 35 sw_frame_group_ctrl_1111 >
204 
205 
206 
207 			<enum 36 sw_frame_group_unsupported> This covers type 3
208 			and protocol version != 0
209 
210 
211 
212 
213 
214 
215 			<legal 0-37>
216 
217 reserved_0
218 
219 			<legal 0>
220 
221 phy_ppdu_id
222 
223 			A ppdu counter value that PHY increments for every PPDU
224 			received. The counter value wraps around
225 
226 			<legal all>
227 
228 first_mpdu
229 
230 			Indicates the first MSDU of the PPDU.  If both
231 			first_mpdu and last_mpdu are set in the MSDU then this is a
232 			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
233 			in an A-MPDU shall have both first_mpdu and last_mpdu bits
234 			set to 0.  The PPDU start status will only be valid when
235 			this bit is set.
236 
237 reserved_1a
238 
239 			<legal 0>
240 
241 mcast_bcast
242 
243 			Multicast / broadcast indicator.  Only set when the MAC
244 			address 1 bit 0 is set indicating mcast/bcast and the BSSID
245 			matches one of the 4 BSSID registers. Only set when
246 			first_msdu is set.
247 
248 ast_index_not_found
249 
250 			Only valid when first_msdu is set.
251 
252 
253 
254 			Indicates no AST matching entries within the the max
255 			search count.
256 
257 ast_index_timeout
258 
259 			Only valid when first_msdu is set.
260 
261 
262 
263 			Indicates an unsuccessful search in the address seach
264 			table due to timeout.
265 
266 power_mgmt
267 
268 			Power management bit set in the 802.11 header.  Only set
269 			when first_msdu is set.
270 
271 non_qos
272 
273 			Set if packet is not a non-QoS data frame.  Only set
274 			when first_msdu is set.
275 
276 null_data
277 
278 			Set if frame type indicates either null data or QoS null
279 			data format.  Only set when first_msdu is set.
280 
281 mgmt_type
282 
283 			Set if packet is a management packet.  Only set when
284 			first_msdu is set.
285 
286 ctrl_type
287 
288 			Set if packet is a control packet.  Only set when
289 			first_msdu is set.
290 
291 more_data
292 
293 			Set if more bit in frame control is set.  Only set when
294 			first_msdu is set.
295 
296 eosp
297 
298 			Set if the EOSP (end of service period) bit in the QoS
299 			control field is set.  Only set when first_msdu is set.
300 
301 a_msdu_error
302 
303 			Set if number of MSDUs in A-MSDU is above a threshold or
304 			if the size of the MSDU is invalid.  This receive buffer
305 			will contain all of the remainder of the MSDUs in this MPDU
306 			without decapsulation.
307 
308 fragment_flag
309 
310 			Indicates that this is an 802.11 fragment frame.  This
311 			is set when either the more_frag bit is set in the frame
312 			control or the fragment number is not zero.  Only set when
313 			first_msdu is set.
314 
315 order
316 
317 			Set if the order bit in the frame control is set.  Only
318 			set when first_msdu is set.
319 
320 cce_match
321 
322 			Indicates that this status has a corresponding MSDU that
323 			requires FW processing.  The OLE will have classification
324 			ring mask registers which will indicate the ring(s) for
325 			packets and descriptors which need FW attention.
326 
327 overflow_err
328 
329 			RXPCU Receive FIFO ran out of space to receive the full
330 			MPDU. Therefor this MPDU is terminated early and is thus
331 			corrupted.
332 
333 
334 
335 			This MPDU will not be ACKed.
336 
337 			RXPCU might still be able to correctly receive the
338 			following MPDUs in the PPDU if enough fifo space became
339 			available in time
340 
341 msdu_length_err
342 
343 			Indicates that the MSDU length from the 802.3
344 			encapsulated length field extends beyond the MPDU boundary
345 			or if the length is less than 14 bytes.
346 
347 			Merged with original other_msdu_err: Indicates that the
348 			MSDU threshold was exceeded and thus all the rest of the
349 			MSDUs will not be scattered and will not be decasulated but
350 			will be DMA'ed in RAW format as a single MSDU buffer
351 
352 tcp_udp_chksum_fail
353 
354 			Indicates that the computed checksum (tcp_udp_chksum)
355 			did not match the checksum in the TCP/UDP header.
356 
357 ip_chksum_fail
358 
359 			Indicates that the computed checksum did not match the
360 			checksum in the IP header.
361 
362 sa_idx_invalid
363 
364 			Indicates no matching entry was found in the address
365 			search table for the source MAC address.
366 
367 da_idx_invalid
368 
369 			Indicates no matching entry was found in the address
370 			search table for the destination MAC address.
371 
372 reserved_1b
373 
374 
375 rx_in_tx_decrypt_byp
376 
377 			Indicates that RX packet is not decrypted as Crypto is
378 			busy with TX packet processing.
379 
380 encrypt_required
381 
382 			Indicates that this data type frame is not encrypted
383 			even if the policy for this MPDU requires encryption as
384 			indicated in the peer entry key type.
385 
386 directed
387 
388 			MPDU is a directed packet which means that the RA
389 			matched our STA addresses.  In proxySTA it means that the TA
390 			matched an entry in our address search table with the
391 			corresponding no_ack bit is the address search entry
392 			cleared.
393 
394 buffer_fragment
395 
396 			Indicates that at least one of the rx buffers has been
397 			fragmented.  If set the FW should look at the rx_frag_info
398 			descriptor described below.
399 
400 mpdu_length_err
401 
402 			Indicates that the MPDU was pre-maturely terminated
403 			resulting in a truncated MPDU.  Don't trust the MPDU length
404 			field.
405 
406 tkip_mic_err
407 
408 			Indicates that the MPDU Michael integrity check failed
409 
410 decrypt_err
411 
412 			Indicates that the MPDU decrypt integrity check failed
413 			or CRYPTO received an encrypted frame, but did not get a
414 			valid corresponding key id in the peer entry.
415 
416 unencrypted_frame_err
417 
418 			Copied here by RX OLE from the RX_MPDU_END TLV
419 
420 fcs_err
421 
422 			Indicates that the MPDU FCS check failed
423 
424 flow_idx_timeout
425 
426 			Indicates an unsuccessful flow search due to the
427 			expiring of the search timer.
428 
429 			<legal all>
430 
431 flow_idx_invalid
432 
433 			flow id is not valid
434 
435 			<legal all>
436 
437 wifi_parser_error
438 
439 			Indicates that the WiFi frame has one of the following
440 			errors
441 
442 			o has less than minimum allowed bytes as per standard
443 
444 			o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
445 
446 			<legal all>
447 
448 amsdu_parser_error
449 
450 			A-MSDU could not be properly de-agregated.
451 
452 			<legal all>
453 
454 sa_idx_timeout
455 
456 			Indicates an unsuccessful MAC source address search due
457 			to the expiring of the search timer.
458 
459 da_idx_timeout
460 
461 			Indicates an unsuccessful MAC destination address search
462 			due to the expiring of the search timer.
463 
464 msdu_limit_error
465 
466 			Indicates that the MSDU threshold was exceeded and thus
467 			all the rest of the MSDUs will not be scattered and will not
468 			be decasulated but will be DMA'ed in RAW format as a single
469 			MSDU buffer
470 
471 da_is_valid
472 
473 			Indicates that OLE found a valid DA entry
474 
475 da_is_mcbc
476 
477 			Field Only valid if da_is_valid is set
478 
479 
480 
481 			Indicates the DA address was a Multicast of Broadcast
482 			address.
483 
484 sa_is_valid
485 
486 			Indicates that OLE found a valid SA entry
487 
488 decrypt_status_code
489 
490 			Field provides insight into the decryption performed
491 
492 
493 
494 			<enum 0 decrypt_ok> Frame had protection enabled and
495 			decrypted properly
496 
497 			<enum 1 decrypt_unprotected_frame > Frame is unprotected
498 			and hence bypassed
499 
500 			<enum 2 decrypt_data_err > Frame has protection enabled
501 			and could not be properly decrypted due to MIC/ICV mismatch
502 			etc.
503 
504 			<enum 3 decrypt_key_invalid > Frame has protection
505 			enabled but the key that was required to decrypt this frame
506 			was not valid
507 
508 			<enum 4 decrypt_peer_entry_invalid > Frame has
509 			protection enabled but the key that was required to decrypt
510 			this frame was not valid
511 
512 			<enum 5 decrypt_other > Reserved for other indications
513 
514 
515 
516 			<legal 0 - 5>
517 
518 rx_bitmap_not_updated
519 
520 			Frame is received, but RXPCU could not update the
521 			receive bitmap due to (temporary) fifo contraints.
522 
523 			<legal all>
524 
525 reserved_2
526 
527 			<legal 0>
528 
529 msdu_done
530 
531 			If set indicates that the RX packet data, RX header
532 			data, RX PPDU start descriptor, RX MPDU start/end
533 			descriptor, RX MSDU start/end descriptors and RX Attention
534 			descriptor are all valid.  This bit must be in the last
535 			octet of the descriptor.
536 */
537 
538 
539 /* Description		RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY
540 
541 			Field indicates what the reason was that this MPDU frame
542 			was allowed to come into the receive path by RXPCU
543 
544 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
545 			frame filter programming of rxpcu
546 
547 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
548 			regular frame filter and would have been dropped, were it
549 			not for the frame fitting into the 'monitor_client'
550 			category.
551 
552 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
553 			regular frame filter and also did not pass the
554 			rxpcu_monitor_client filter. It would have been dropped
555 			accept that it did pass the 'monitor_other' category.
556 
557 			<legal 0-2>
558 */
559 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000000
560 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
561 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
562 
563 /* Description		RX_ATTENTION_0_SW_FRAME_GROUP_ID
564 
565 			SW processes frames based on certain classifications.
566 			This field indicates to what sw classification this MPDU is
567 			mapped.
568 
569 			The classification is given in priority order
570 
571 
572 
573 			<enum 0 sw_frame_group_NDP_frame>
574 
575 
576 
577 			<enum 1 sw_frame_group_Multicast_data>
578 
579 			<enum 2 sw_frame_group_Unicast_data>
580 
581 			<enum 3 sw_frame_group_Null_data > This includes mpdus
582 			of type Data Null as well as QoS Data Null
583 
584 
585 
586 			<enum 4 sw_frame_group_mgmt_0000 >
587 
588 			<enum 5 sw_frame_group_mgmt_0001 >
589 
590 			<enum 6 sw_frame_group_mgmt_0010 >
591 
592 			<enum 7 sw_frame_group_mgmt_0011 >
593 
594 			<enum 8 sw_frame_group_mgmt_0100 >
595 
596 			<enum 9 sw_frame_group_mgmt_0101 >
597 
598 			<enum 10 sw_frame_group_mgmt_0110 >
599 
600 			<enum 11 sw_frame_group_mgmt_0111 >
601 
602 			<enum 12 sw_frame_group_mgmt_1000 >
603 
604 			<enum 13 sw_frame_group_mgmt_1001 >
605 
606 			<enum 14 sw_frame_group_mgmt_1010 >
607 
608 			<enum 15 sw_frame_group_mgmt_1011 >
609 
610 			<enum 16 sw_frame_group_mgmt_1100 >
611 
612 			<enum 17 sw_frame_group_mgmt_1101 >
613 
614 			<enum 18 sw_frame_group_mgmt_1110 >
615 
616 			<enum 19 sw_frame_group_mgmt_1111 >
617 
618 
619 
620 			<enum 20 sw_frame_group_ctrl_0000 >
621 
622 			<enum 21 sw_frame_group_ctrl_0001 >
623 
624 			<enum 22 sw_frame_group_ctrl_0010 >
625 
626 			<enum 23 sw_frame_group_ctrl_0011 >
627 
628 			<enum 24 sw_frame_group_ctrl_0100 >
629 
630 			<enum 25 sw_frame_group_ctrl_0101 >
631 
632 			<enum 26 sw_frame_group_ctrl_0110 >
633 
634 			<enum 27 sw_frame_group_ctrl_0111 >
635 
636 			<enum 28 sw_frame_group_ctrl_1000 >
637 
638 			<enum 29 sw_frame_group_ctrl_1001 >
639 
640 			<enum 30 sw_frame_group_ctrl_1010 >
641 
642 			<enum 31 sw_frame_group_ctrl_1011 >
643 
644 			<enum 32 sw_frame_group_ctrl_1100 >
645 
646 			<enum 33 sw_frame_group_ctrl_1101 >
647 
648 			<enum 34 sw_frame_group_ctrl_1110 >
649 
650 			<enum 35 sw_frame_group_ctrl_1111 >
651 
652 
653 
654 			<enum 36 sw_frame_group_unsupported> This covers type 3
655 			and protocol version != 0
656 
657 
658 
659 
660 
661 
662 			<legal 0-37>
663 */
664 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET                      0x00000000
665 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB                         2
666 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK                        0x000001fc
667 
668 /* Description		RX_ATTENTION_0_RESERVED_0
669 
670 			<legal 0>
671 */
672 #define RX_ATTENTION_0_RESERVED_0_OFFSET                             0x00000000
673 #define RX_ATTENTION_0_RESERVED_0_LSB                                9
674 #define RX_ATTENTION_0_RESERVED_0_MASK                               0x0000fe00
675 
676 /* Description		RX_ATTENTION_0_PHY_PPDU_ID
677 
678 			A ppdu counter value that PHY increments for every PPDU
679 			received. The counter value wraps around
680 
681 			<legal all>
682 */
683 #define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET                            0x00000000
684 #define RX_ATTENTION_0_PHY_PPDU_ID_LSB                               16
685 #define RX_ATTENTION_0_PHY_PPDU_ID_MASK                              0xffff0000
686 
687 /* Description		RX_ATTENTION_1_FIRST_MPDU
688 
689 			Indicates the first MSDU of the PPDU.  If both
690 			first_mpdu and last_mpdu are set in the MSDU then this is a
691 			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
692 			in an A-MPDU shall have both first_mpdu and last_mpdu bits
693 			set to 0.  The PPDU start status will only be valid when
694 			this bit is set.
695 */
696 #define RX_ATTENTION_1_FIRST_MPDU_OFFSET                             0x00000004
697 #define RX_ATTENTION_1_FIRST_MPDU_LSB                                0
698 #define RX_ATTENTION_1_FIRST_MPDU_MASK                               0x00000001
699 
700 /* Description		RX_ATTENTION_1_RESERVED_1A
701 
702 			<legal 0>
703 */
704 #define RX_ATTENTION_1_RESERVED_1A_OFFSET                            0x00000004
705 #define RX_ATTENTION_1_RESERVED_1A_LSB                               1
706 #define RX_ATTENTION_1_RESERVED_1A_MASK                              0x00000002
707 
708 /* Description		RX_ATTENTION_1_MCAST_BCAST
709 
710 			Multicast / broadcast indicator.  Only set when the MAC
711 			address 1 bit 0 is set indicating mcast/bcast and the BSSID
712 			matches one of the 4 BSSID registers. Only set when
713 			first_msdu is set.
714 */
715 #define RX_ATTENTION_1_MCAST_BCAST_OFFSET                            0x00000004
716 #define RX_ATTENTION_1_MCAST_BCAST_LSB                               2
717 #define RX_ATTENTION_1_MCAST_BCAST_MASK                              0x00000004
718 
719 /* Description		RX_ATTENTION_1_AST_INDEX_NOT_FOUND
720 
721 			Only valid when first_msdu is set.
722 
723 
724 
725 			Indicates no AST matching entries within the the max
726 			search count.
727 */
728 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET                    0x00000004
729 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB                       3
730 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK                      0x00000008
731 
732 /* Description		RX_ATTENTION_1_AST_INDEX_TIMEOUT
733 
734 			Only valid when first_msdu is set.
735 
736 
737 
738 			Indicates an unsuccessful search in the address seach
739 			table due to timeout.
740 */
741 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET                      0x00000004
742 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB                         4
743 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK                        0x00000010
744 
745 /* Description		RX_ATTENTION_1_POWER_MGMT
746 
747 			Power management bit set in the 802.11 header.  Only set
748 			when first_msdu is set.
749 */
750 #define RX_ATTENTION_1_POWER_MGMT_OFFSET                             0x00000004
751 #define RX_ATTENTION_1_POWER_MGMT_LSB                                5
752 #define RX_ATTENTION_1_POWER_MGMT_MASK                               0x00000020
753 
754 /* Description		RX_ATTENTION_1_NON_QOS
755 
756 			Set if packet is not a non-QoS data frame.  Only set
757 			when first_msdu is set.
758 */
759 #define RX_ATTENTION_1_NON_QOS_OFFSET                                0x00000004
760 #define RX_ATTENTION_1_NON_QOS_LSB                                   6
761 #define RX_ATTENTION_1_NON_QOS_MASK                                  0x00000040
762 
763 /* Description		RX_ATTENTION_1_NULL_DATA
764 
765 			Set if frame type indicates either null data or QoS null
766 			data format.  Only set when first_msdu is set.
767 */
768 #define RX_ATTENTION_1_NULL_DATA_OFFSET                              0x00000004
769 #define RX_ATTENTION_1_NULL_DATA_LSB                                 7
770 #define RX_ATTENTION_1_NULL_DATA_MASK                                0x00000080
771 
772 /* Description		RX_ATTENTION_1_MGMT_TYPE
773 
774 			Set if packet is a management packet.  Only set when
775 			first_msdu is set.
776 */
777 #define RX_ATTENTION_1_MGMT_TYPE_OFFSET                              0x00000004
778 #define RX_ATTENTION_1_MGMT_TYPE_LSB                                 8
779 #define RX_ATTENTION_1_MGMT_TYPE_MASK                                0x00000100
780 
781 /* Description		RX_ATTENTION_1_CTRL_TYPE
782 
783 			Set if packet is a control packet.  Only set when
784 			first_msdu is set.
785 */
786 #define RX_ATTENTION_1_CTRL_TYPE_OFFSET                              0x00000004
787 #define RX_ATTENTION_1_CTRL_TYPE_LSB                                 9
788 #define RX_ATTENTION_1_CTRL_TYPE_MASK                                0x00000200
789 
790 /* Description		RX_ATTENTION_1_MORE_DATA
791 
792 			Set if more bit in frame control is set.  Only set when
793 			first_msdu is set.
794 */
795 #define RX_ATTENTION_1_MORE_DATA_OFFSET                              0x00000004
796 #define RX_ATTENTION_1_MORE_DATA_LSB                                 10
797 #define RX_ATTENTION_1_MORE_DATA_MASK                                0x00000400
798 
799 /* Description		RX_ATTENTION_1_EOSP
800 
801 			Set if the EOSP (end of service period) bit in the QoS
802 			control field is set.  Only set when first_msdu is set.
803 */
804 #define RX_ATTENTION_1_EOSP_OFFSET                                   0x00000004
805 #define RX_ATTENTION_1_EOSP_LSB                                      11
806 #define RX_ATTENTION_1_EOSP_MASK                                     0x00000800
807 
808 /* Description		RX_ATTENTION_1_A_MSDU_ERROR
809 
810 			Set if number of MSDUs in A-MSDU is above a threshold or
811 			if the size of the MSDU is invalid.  This receive buffer
812 			will contain all of the remainder of the MSDUs in this MPDU
813 			without decapsulation.
814 */
815 #define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET                           0x00000004
816 #define RX_ATTENTION_1_A_MSDU_ERROR_LSB                              12
817 #define RX_ATTENTION_1_A_MSDU_ERROR_MASK                             0x00001000
818 
819 /* Description		RX_ATTENTION_1_FRAGMENT_FLAG
820 
821 			Indicates that this is an 802.11 fragment frame.  This
822 			is set when either the more_frag bit is set in the frame
823 			control or the fragment number is not zero.  Only set when
824 			first_msdu is set.
825 */
826 #define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET                          0x00000004
827 #define RX_ATTENTION_1_FRAGMENT_FLAG_LSB                             13
828 #define RX_ATTENTION_1_FRAGMENT_FLAG_MASK                            0x00002000
829 
830 /* Description		RX_ATTENTION_1_ORDER
831 
832 			Set if the order bit in the frame control is set.  Only
833 			set when first_msdu is set.
834 */
835 #define RX_ATTENTION_1_ORDER_OFFSET                                  0x00000004
836 #define RX_ATTENTION_1_ORDER_LSB                                     14
837 #define RX_ATTENTION_1_ORDER_MASK                                    0x00004000
838 
839 /* Description		RX_ATTENTION_1_CCE_MATCH
840 
841 			Indicates that this status has a corresponding MSDU that
842 			requires FW processing.  The OLE will have classification
843 			ring mask registers which will indicate the ring(s) for
844 			packets and descriptors which need FW attention.
845 */
846 #define RX_ATTENTION_1_CCE_MATCH_OFFSET                              0x00000004
847 #define RX_ATTENTION_1_CCE_MATCH_LSB                                 15
848 #define RX_ATTENTION_1_CCE_MATCH_MASK                                0x00008000
849 
850 /* Description		RX_ATTENTION_1_OVERFLOW_ERR
851 
852 			RXPCU Receive FIFO ran out of space to receive the full
853 			MPDU. Therefor this MPDU is terminated early and is thus
854 			corrupted.
855 
856 
857 
858 			This MPDU will not be ACKed.
859 
860 			RXPCU might still be able to correctly receive the
861 			following MPDUs in the PPDU if enough fifo space became
862 			available in time
863 */
864 #define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET                           0x00000004
865 #define RX_ATTENTION_1_OVERFLOW_ERR_LSB                              16
866 #define RX_ATTENTION_1_OVERFLOW_ERR_MASK                             0x00010000
867 
868 /* Description		RX_ATTENTION_1_MSDU_LENGTH_ERR
869 
870 			Indicates that the MSDU length from the 802.3
871 			encapsulated length field extends beyond the MPDU boundary
872 			or if the length is less than 14 bytes.
873 
874 			Merged with original other_msdu_err: Indicates that the
875 			MSDU threshold was exceeded and thus all the rest of the
876 			MSDUs will not be scattered and will not be decasulated but
877 			will be DMA'ed in RAW format as a single MSDU buffer
878 */
879 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET                        0x00000004
880 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB                           17
881 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK                          0x00020000
882 
883 /* Description		RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL
884 
885 			Indicates that the computed checksum (tcp_udp_chksum)
886 			did not match the checksum in the TCP/UDP header.
887 */
888 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET                    0x00000004
889 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB                       18
890 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK                      0x00040000
891 
892 /* Description		RX_ATTENTION_1_IP_CHKSUM_FAIL
893 
894 			Indicates that the computed checksum did not match the
895 			checksum in the IP header.
896 */
897 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET                         0x00000004
898 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB                            19
899 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK                           0x00080000
900 
901 /* Description		RX_ATTENTION_1_SA_IDX_INVALID
902 
903 			Indicates no matching entry was found in the address
904 			search table for the source MAC address.
905 */
906 #define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET                         0x00000004
907 #define RX_ATTENTION_1_SA_IDX_INVALID_LSB                            20
908 #define RX_ATTENTION_1_SA_IDX_INVALID_MASK                           0x00100000
909 
910 /* Description		RX_ATTENTION_1_DA_IDX_INVALID
911 
912 			Indicates no matching entry was found in the address
913 			search table for the destination MAC address.
914 */
915 #define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET                         0x00000004
916 #define RX_ATTENTION_1_DA_IDX_INVALID_LSB                            21
917 #define RX_ATTENTION_1_DA_IDX_INVALID_MASK                           0x00200000
918 
919 /* Description		RX_ATTENTION_1_RESERVED_1B
920 
921 */
922 #define RX_ATTENTION_1_RESERVED_1B_OFFSET                            0x00000004
923 #define RX_ATTENTION_1_RESERVED_1B_LSB                               22
924 #define RX_ATTENTION_1_RESERVED_1B_MASK                              0x00400000
925 
926 /* Description		RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP
927 
928 			Indicates that RX packet is not decrypted as Crypto is
929 			busy with TX packet processing.
930 */
931 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET                   0x00000004
932 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB                      23
933 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK                     0x00800000
934 
935 /* Description		RX_ATTENTION_1_ENCRYPT_REQUIRED
936 
937 			Indicates that this data type frame is not encrypted
938 			even if the policy for this MPDU requires encryption as
939 			indicated in the peer entry key type.
940 */
941 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET                       0x00000004
942 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB                          24
943 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK                         0x01000000
944 
945 /* Description		RX_ATTENTION_1_DIRECTED
946 
947 			MPDU is a directed packet which means that the RA
948 			matched our STA addresses.  In proxySTA it means that the TA
949 			matched an entry in our address search table with the
950 			corresponding no_ack bit is the address search entry
951 			cleared.
952 */
953 #define RX_ATTENTION_1_DIRECTED_OFFSET                               0x00000004
954 #define RX_ATTENTION_1_DIRECTED_LSB                                  25
955 #define RX_ATTENTION_1_DIRECTED_MASK                                 0x02000000
956 
957 /* Description		RX_ATTENTION_1_BUFFER_FRAGMENT
958 
959 			Indicates that at least one of the rx buffers has been
960 			fragmented.  If set the FW should look at the rx_frag_info
961 			descriptor described below.
962 */
963 #define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET                        0x00000004
964 #define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB                           26
965 #define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK                          0x04000000
966 
967 /* Description		RX_ATTENTION_1_MPDU_LENGTH_ERR
968 
969 			Indicates that the MPDU was pre-maturely terminated
970 			resulting in a truncated MPDU.  Don't trust the MPDU length
971 			field.
972 */
973 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET                        0x00000004
974 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB                           27
975 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK                          0x08000000
976 
977 /* Description		RX_ATTENTION_1_TKIP_MIC_ERR
978 
979 			Indicates that the MPDU Michael integrity check failed
980 */
981 #define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET                           0x00000004
982 #define RX_ATTENTION_1_TKIP_MIC_ERR_LSB                              28
983 #define RX_ATTENTION_1_TKIP_MIC_ERR_MASK                             0x10000000
984 
985 /* Description		RX_ATTENTION_1_DECRYPT_ERR
986 
987 			Indicates that the MPDU decrypt integrity check failed
988 			or CRYPTO received an encrypted frame, but did not get a
989 			valid corresponding key id in the peer entry.
990 */
991 #define RX_ATTENTION_1_DECRYPT_ERR_OFFSET                            0x00000004
992 #define RX_ATTENTION_1_DECRYPT_ERR_LSB                               29
993 #define RX_ATTENTION_1_DECRYPT_ERR_MASK                              0x20000000
994 
995 /* Description		RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR
996 
997 			Copied here by RX OLE from the RX_MPDU_END TLV
998 */
999 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET                  0x00000004
1000 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB                     30
1001 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK                    0x40000000
1002 
1003 /* Description		RX_ATTENTION_1_FCS_ERR
1004 
1005 			Indicates that the MPDU FCS check failed
1006 */
1007 #define RX_ATTENTION_1_FCS_ERR_OFFSET                                0x00000004
1008 #define RX_ATTENTION_1_FCS_ERR_LSB                                   31
1009 #define RX_ATTENTION_1_FCS_ERR_MASK                                  0x80000000
1010 
1011 /* Description		RX_ATTENTION_2_FLOW_IDX_TIMEOUT
1012 
1013 			Indicates an unsuccessful flow search due to the
1014 			expiring of the search timer.
1015 
1016 			<legal all>
1017 */
1018 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET                       0x00000008
1019 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB                          0
1020 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK                         0x00000001
1021 
1022 /* Description		RX_ATTENTION_2_FLOW_IDX_INVALID
1023 
1024 			flow id is not valid
1025 
1026 			<legal all>
1027 */
1028 #define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET                       0x00000008
1029 #define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB                          1
1030 #define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK                         0x00000002
1031 
1032 /* Description		RX_ATTENTION_2_WIFI_PARSER_ERROR
1033 
1034 			Indicates that the WiFi frame has one of the following
1035 			errors
1036 
1037 			o has less than minimum allowed bytes as per standard
1038 
1039 			o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
1040 
1041 			<legal all>
1042 */
1043 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET                      0x00000008
1044 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB                         2
1045 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK                        0x00000004
1046 
1047 /* Description		RX_ATTENTION_2_AMSDU_PARSER_ERROR
1048 
1049 			A-MSDU could not be properly de-agregated.
1050 
1051 			<legal all>
1052 */
1053 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET                     0x00000008
1054 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB                        3
1055 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK                       0x00000008
1056 
1057 /* Description		RX_ATTENTION_2_SA_IDX_TIMEOUT
1058 
1059 			Indicates an unsuccessful MAC source address search due
1060 			to the expiring of the search timer.
1061 */
1062 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET                         0x00000008
1063 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB                            4
1064 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK                           0x00000010
1065 
1066 /* Description		RX_ATTENTION_2_DA_IDX_TIMEOUT
1067 
1068 			Indicates an unsuccessful MAC destination address search
1069 			due to the expiring of the search timer.
1070 */
1071 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET                         0x00000008
1072 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB                            5
1073 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK                           0x00000020
1074 
1075 /* Description		RX_ATTENTION_2_MSDU_LIMIT_ERROR
1076 
1077 			Indicates that the MSDU threshold was exceeded and thus
1078 			all the rest of the MSDUs will not be scattered and will not
1079 			be decasulated but will be DMA'ed in RAW format as a single
1080 			MSDU buffer
1081 */
1082 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET                       0x00000008
1083 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB                          6
1084 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK                         0x00000040
1085 
1086 /* Description		RX_ATTENTION_2_DA_IS_VALID
1087 
1088 			Indicates that OLE found a valid DA entry
1089 */
1090 #define RX_ATTENTION_2_DA_IS_VALID_OFFSET                            0x00000008
1091 #define RX_ATTENTION_2_DA_IS_VALID_LSB                               7
1092 #define RX_ATTENTION_2_DA_IS_VALID_MASK                              0x00000080
1093 
1094 /* Description		RX_ATTENTION_2_DA_IS_MCBC
1095 
1096 			Field Only valid if da_is_valid is set
1097 
1098 
1099 
1100 			Indicates the DA address was a Multicast of Broadcast
1101 			address.
1102 */
1103 #define RX_ATTENTION_2_DA_IS_MCBC_OFFSET                             0x00000008
1104 #define RX_ATTENTION_2_DA_IS_MCBC_LSB                                8
1105 #define RX_ATTENTION_2_DA_IS_MCBC_MASK                               0x00000100
1106 
1107 /* Description		RX_ATTENTION_2_SA_IS_VALID
1108 
1109 			Indicates that OLE found a valid SA entry
1110 */
1111 #define RX_ATTENTION_2_SA_IS_VALID_OFFSET                            0x00000008
1112 #define RX_ATTENTION_2_SA_IS_VALID_LSB                               9
1113 #define RX_ATTENTION_2_SA_IS_VALID_MASK                              0x00000200
1114 
1115 /* Description		RX_ATTENTION_2_DECRYPT_STATUS_CODE
1116 
1117 			Field provides insight into the decryption performed
1118 
1119 
1120 
1121 			<enum 0 decrypt_ok> Frame had protection enabled and
1122 			decrypted properly
1123 
1124 			<enum 1 decrypt_unprotected_frame > Frame is unprotected
1125 			and hence bypassed
1126 
1127 			<enum 2 decrypt_data_err > Frame has protection enabled
1128 			and could not be properly decrypted due to MIC/ICV mismatch
1129 			etc.
1130 
1131 			<enum 3 decrypt_key_invalid > Frame has protection
1132 			enabled but the key that was required to decrypt this frame
1133 			was not valid
1134 
1135 			<enum 4 decrypt_peer_entry_invalid > Frame has
1136 			protection enabled but the key that was required to decrypt
1137 			this frame was not valid
1138 
1139 			<enum 5 decrypt_other > Reserved for other indications
1140 
1141 
1142 
1143 			<legal 0 - 5>
1144 */
1145 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET                    0x00000008
1146 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB                       10
1147 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK                      0x00001c00
1148 
1149 /* Description		RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED
1150 
1151 			Frame is received, but RXPCU could not update the
1152 			receive bitmap due to (temporary) fifo contraints.
1153 
1154 			<legal all>
1155 */
1156 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET                  0x00000008
1157 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB                     13
1158 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK                    0x00002000
1159 
1160 /* Description		RX_ATTENTION_2_RESERVED_2
1161 
1162 			<legal 0>
1163 */
1164 #define RX_ATTENTION_2_RESERVED_2_OFFSET                             0x00000008
1165 #define RX_ATTENTION_2_RESERVED_2_LSB                                14
1166 #define RX_ATTENTION_2_RESERVED_2_MASK                               0x7fffc000
1167 
1168 /* Description		RX_ATTENTION_2_MSDU_DONE
1169 
1170 			If set indicates that the RX packet data, RX header
1171 			data, RX PPDU start descriptor, RX MPDU start/end
1172 			descriptor, RX MSDU start/end descriptors and RX Attention
1173 			descriptor are all valid.  This bit must be in the last
1174 			octet of the descriptor.
1175 */
1176 #define RX_ATTENTION_2_MSDU_DONE_OFFSET                              0x00000008
1177 #define RX_ATTENTION_2_MSDU_DONE_LSB                                 31
1178 #define RX_ATTENTION_2_MSDU_DONE_MASK                                0x80000000
1179 
1180 
1181 #endif // _RX_ATTENTION_H_
1182