1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MPDU_INFO_H_ 25 #define _RX_MPDU_INFO_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rxpt_classify_info.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16] 35 // 1 ast_index[15:0], sw_peer_id[31:16] 36 // 2 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], reserved_2a[15:10], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] 37 // 3 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], mesh_sta[6], bssid_hit[7], bssid_number[11:8], tid[15:12], reserved_3a[31:16] 38 // 4 pn_31_0[31:0] 39 // 5 pn_63_32[31:0] 40 // 6 pn_95_64[31:0] 41 // 7 pn_127_96[31:0] 42 // 8 peer_meta_data[31:0] 43 // 9 struct rxpt_classify_info rxpt_classify_info_details; 44 // 10 rx_reo_queue_desc_addr_31_0[31:0] 45 // 11 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26] 46 // 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30] 47 // 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], reserved_13[31:30] 48 // 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] 49 // 15 mac_addr_ad1_31_0[31:0] 50 // 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] 51 // 17 mac_addr_ad2_47_16[31:0] 52 // 18 mac_addr_ad3_31_0[31:0] 53 // 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] 54 // 20 mac_addr_ad4_31_0[31:0] 55 // 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] 56 // 22 mpdu_ht_control_field[31:0] 57 // 58 // ################ END SUMMARY ################# 59 60 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 61 62 struct rx_mpdu_info { 63 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 64 sw_frame_group_id : 7, //[8:2] 65 ndp_frame : 1, //[9] 66 phy_err : 1, //[10] 67 phy_err_during_mpdu_header : 1, //[11] 68 protocol_version_err : 1, //[12] 69 ast_based_lookup_valid : 1, //[13] 70 reserved_0a : 2, //[15:14] 71 phy_ppdu_id : 16; //[31:16] 72 uint32_t ast_index : 16, //[15:0] 73 sw_peer_id : 16; //[31:16] 74 uint32_t mpdu_frame_control_valid : 1, //[0] 75 mpdu_duration_valid : 1, //[1] 76 mac_addr_ad1_valid : 1, //[2] 77 mac_addr_ad2_valid : 1, //[3] 78 mac_addr_ad3_valid : 1, //[4] 79 mac_addr_ad4_valid : 1, //[5] 80 mpdu_sequence_control_valid : 1, //[6] 81 mpdu_qos_control_valid : 1, //[7] 82 mpdu_ht_control_valid : 1, //[8] 83 frame_encryption_info_valid : 1, //[9] 84 reserved_2a : 6, //[15:10] 85 fr_ds : 1, //[16] 86 to_ds : 1, //[17] 87 encrypted : 1, //[18] 88 mpdu_retry : 1, //[19] 89 mpdu_sequence_number : 12; //[31:20] 90 uint32_t epd_en : 1, //[0] 91 all_frames_shall_be_encrypted : 1, //[1] 92 encrypt_type : 4, //[5:2] 93 mesh_sta : 1, //[6] 94 bssid_hit : 1, //[7] 95 bssid_number : 4, //[11:8] 96 tid : 4, //[15:12] 97 reserved_3a : 16; //[31:16] 98 uint32_t pn_31_0 : 32; //[31:0] 99 uint32_t pn_63_32 : 32; //[31:0] 100 uint32_t pn_95_64 : 32; //[31:0] 101 uint32_t pn_127_96 : 32; //[31:0] 102 uint32_t peer_meta_data : 32; //[31:0] 103 struct rxpt_classify_info rxpt_classify_info_details; 104 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 105 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 106 receive_queue_number : 16, //[23:8] 107 pre_delim_err_warning : 1, //[24] 108 first_delim_err : 1, //[25] 109 reserved_11 : 6; //[31:26] 110 uint32_t key_id_octet : 8, //[7:0] 111 new_peer_entry : 1, //[8] 112 decrypt_needed : 1, //[9] 113 decap_type : 2, //[11:10] 114 rx_insert_vlan_c_tag_padding : 1, //[12] 115 rx_insert_vlan_s_tag_padding : 1, //[13] 116 strip_vlan_c_tag_decap : 1, //[14] 117 strip_vlan_s_tag_decap : 1, //[15] 118 pre_delim_count : 12, //[27:16] 119 ampdu_flag : 1, //[28] 120 bar_frame : 1, //[29] 121 reserved_12 : 2; //[31:30] 122 uint32_t mpdu_length : 14, //[13:0] 123 first_mpdu : 1, //[14] 124 mcast_bcast : 1, //[15] 125 ast_index_not_found : 1, //[16] 126 ast_index_timeout : 1, //[17] 127 power_mgmt : 1, //[18] 128 non_qos : 1, //[19] 129 null_data : 1, //[20] 130 mgmt_type : 1, //[21] 131 ctrl_type : 1, //[22] 132 more_data : 1, //[23] 133 eosp : 1, //[24] 134 fragment_flag : 1, //[25] 135 order : 1, //[26] 136 u_apsd_trigger : 1, //[27] 137 encrypt_required : 1, //[28] 138 directed : 1, //[29] 139 reserved_13 : 2; //[31:30] 140 uint32_t mpdu_frame_control_field : 16, //[15:0] 141 mpdu_duration_field : 16; //[31:16] 142 uint32_t mac_addr_ad1_31_0 : 32; //[31:0] 143 uint32_t mac_addr_ad1_47_32 : 16, //[15:0] 144 mac_addr_ad2_15_0 : 16; //[31:16] 145 uint32_t mac_addr_ad2_47_16 : 32; //[31:0] 146 uint32_t mac_addr_ad3_31_0 : 32; //[31:0] 147 uint32_t mac_addr_ad3_47_32 : 16, //[15:0] 148 mpdu_sequence_control_field : 16; //[31:16] 149 uint32_t mac_addr_ad4_31_0 : 32; //[31:0] 150 uint32_t mac_addr_ad4_47_32 : 16, //[15:0] 151 mpdu_qos_control_field : 16; //[31:16] 152 uint32_t mpdu_ht_control_field : 32; //[31:0] 153 }; 154 155 /* 156 157 rxpcu_mpdu_filter_in_category 158 159 Field indicates what the reason was that this MPDU frame 160 was allowed to come into the receive path by RXPCU 161 162 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 163 frame filter programming of rxpcu 164 165 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 166 regular frame filter and would have been dropped, were it 167 not for the frame fitting into the 'monitor_client' 168 category. 169 170 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 171 regular frame filter and also did not pass the 172 rxpcu_monitor_client filter. It would have been dropped 173 accept that it did pass the 'monitor_other' category. 174 175 176 177 Note: for ndp frame, if it was expected because the 178 preceding NDPA was filter_pass, the setting 179 rxpcu_filter_pass will be used. This setting will also be 180 used for every ndp frame in case Promiscuous mode is 181 enabled. 182 183 184 185 In case promiscuous is not enabled, and an NDP is not 186 preceded by a NPDA filter pass frame, the only other setting 187 that could appear here for the NDP is rxpcu_monitor_other. 188 189 (rxpcu has a configuration bit specifically for this 190 scenario) 191 192 193 194 Note: for 195 196 <legal 0-2> 197 198 sw_frame_group_id 199 200 SW processes frames based on certain classifications. 201 This field indicates to what sw classification this MPDU is 202 mapped. 203 204 The classification is given in priority order 205 206 207 208 <enum 0 sw_frame_group_NDP_frame> Note: The 209 corresponding Rxpcu_Mpdu_filter_in_category can be 210 rxpcu_filter_pass or rxpcu_monitor_other 211 212 213 214 <enum 1 sw_frame_group_Multicast_data> 215 216 <enum 2 sw_frame_group_Unicast_data> 217 218 <enum 3 sw_frame_group_Null_data > This includes mpdus 219 of type Data Null as well as QoS Data Null 220 221 222 223 <enum 4 sw_frame_group_mgmt_0000 > 224 225 <enum 5 sw_frame_group_mgmt_0001 > 226 227 <enum 6 sw_frame_group_mgmt_0010 > 228 229 <enum 7 sw_frame_group_mgmt_0011 > 230 231 <enum 8 sw_frame_group_mgmt_0100 > 232 233 <enum 9 sw_frame_group_mgmt_0101 > 234 235 <enum 10 sw_frame_group_mgmt_0110 > 236 237 <enum 11 sw_frame_group_mgmt_0111 > 238 239 <enum 12 sw_frame_group_mgmt_1000 > 240 241 <enum 13 sw_frame_group_mgmt_1001 > 242 243 <enum 14 sw_frame_group_mgmt_1010 > 244 245 <enum 15 sw_frame_group_mgmt_1011 > 246 247 <enum 16 sw_frame_group_mgmt_1100 > 248 249 <enum 17 sw_frame_group_mgmt_1101 > 250 251 <enum 18 sw_frame_group_mgmt_1110 > 252 253 <enum 19 sw_frame_group_mgmt_1111 > 254 255 256 257 <enum 20 sw_frame_group_ctrl_0000 > 258 259 <enum 21 sw_frame_group_ctrl_0001 > 260 261 <enum 22 sw_frame_group_ctrl_0010 > 262 263 <enum 23 sw_frame_group_ctrl_0011 > 264 265 <enum 24 sw_frame_group_ctrl_0100 > 266 267 <enum 25 sw_frame_group_ctrl_0101 > 268 269 <enum 26 sw_frame_group_ctrl_0110 > 270 271 <enum 27 sw_frame_group_ctrl_0111 > 272 273 <enum 28 sw_frame_group_ctrl_1000 > 274 275 <enum 29 sw_frame_group_ctrl_1001 > 276 277 <enum 30 sw_frame_group_ctrl_1010 > 278 279 <enum 31 sw_frame_group_ctrl_1011 > 280 281 <enum 32 sw_frame_group_ctrl_1100 > 282 283 <enum 33 sw_frame_group_ctrl_1101 > 284 285 <enum 34 sw_frame_group_ctrl_1110 > 286 287 <enum 35 sw_frame_group_ctrl_1111 > 288 289 290 291 <enum 36 sw_frame_group_unsupported> This covers type 3 292 and protocol version != 0 293 294 Note: The corresponding Rxpcu_Mpdu_filter_in_category 295 can only be rxpcu_monitor_other 296 297 298 299 300 Note: The corresponding Rxpcu_Mpdu_filter_in_category 301 can be rxpcu_filter_pass 302 303 304 305 <legal 0-37> 306 307 ndp_frame 308 309 When set, the received frame was an NDP frame, and thus 310 there will be no MPDU data. 311 312 <legal all> 313 314 phy_err 315 316 When set, a PHY error was received before MAC received 317 any data, and thus there will be no MPDU data. 318 319 <legal all> 320 321 phy_err_during_mpdu_header 322 323 When set, a PHY error was received before MAC received 324 the complete MPDU header which was needed for proper 325 decoding 326 327 <legal all> 328 329 protocol_version_err 330 331 Set when RXPCU detected a version error in the Frame 332 control field 333 334 <legal all> 335 336 ast_based_lookup_valid 337 338 When set, AST based lookup for this frame has found a 339 valid result. 340 341 342 343 Note that for NDP frame this will never be set 344 345 <legal all> 346 347 reserved_0a 348 349 <legal 0> 350 351 phy_ppdu_id 352 353 A ppdu counter value that PHY increments for every PPDU 354 received. The counter value wraps around 355 356 <legal all> 357 358 ast_index 359 360 This field indicates the index of the AST entry 361 corresponding to this MPDU. It is provided by the GSE module 362 instantiated in RXPCU. 363 364 A value of 0xFFFF indicates an invalid AST index, 365 meaning that No AST entry was found or NO AST search was 366 performed 367 368 369 370 In case of ndp or phy_err, this field will be set to 371 0xFFFF 372 373 <legal all> 374 375 sw_peer_id 376 377 In case of ndp or phy_err or AST_based_lookup_valid == 378 0, this field will be set to 0 379 380 381 382 This field indicates a unique peer identifier. It is set 383 equal to field 'sw_peer_id' from the AST entry 384 385 386 387 <legal all> 388 389 mpdu_frame_control_valid 390 391 When set, the field Mpdu_Frame_control_field has valid 392 information 393 394 395 396 397 <legal all> 398 399 mpdu_duration_valid 400 401 When set, the field Mpdu_duration_field has valid 402 information 403 404 405 406 407 <legal all> 408 409 mac_addr_ad1_valid 410 411 When set, the fields mac_addr_ad1_..... have valid 412 information 413 414 415 416 417 <legal all> 418 419 mac_addr_ad2_valid 420 421 When set, the fields mac_addr_ad2_..... have valid 422 information 423 424 425 426 427 428 429 430 <legal all> 431 432 mac_addr_ad3_valid 433 434 When set, the fields mac_addr_ad3_..... have valid 435 information 436 437 438 439 440 441 442 443 <legal all> 444 445 mac_addr_ad4_valid 446 447 When set, the fields mac_addr_ad4_..... have valid 448 information 449 450 451 452 453 454 455 456 <legal all> 457 458 mpdu_sequence_control_valid 459 460 When set, the fields mpdu_sequence_control_field and 461 mpdu_sequence_number have valid information as well as field 462 463 464 465 For MPDUs without a sequence control field, this field 466 will not be set. 467 468 469 470 471 <legal all> 472 473 mpdu_qos_control_valid 474 475 When set, the field mpdu_qos_control_field has valid 476 information 477 478 479 480 For MPDUs without a QoS control field, this field will 481 not be set. 482 483 484 485 486 <legal all> 487 488 mpdu_ht_control_valid 489 490 When set, the field mpdu_HT_control_field has valid 491 information 492 493 494 495 For MPDUs without a HT control field, this field will 496 not be set. 497 498 499 500 501 <legal all> 502 503 frame_encryption_info_valid 504 505 When set, the encryption related info fields, like IV 506 and PN are valid 507 508 509 510 For MPDUs that are not encrypted, this will not be set. 511 512 513 514 515 <legal all> 516 517 reserved_2a 518 519 <legal 0> 520 521 fr_ds 522 523 Field only valid when Mpdu_frame_control_valid is set 524 525 526 527 Set if the from DS bit is set in the frame control. 528 529 <legal all> 530 531 to_ds 532 533 Field only valid when Mpdu_frame_control_valid is set 534 535 536 537 Set if the to DS bit is set in the frame control. 538 539 <legal all> 540 541 encrypted 542 543 Field only valid when Mpdu_frame_control_valid is set. 544 545 546 547 Protected bit from the frame control. 548 549 <legal all> 550 551 mpdu_retry 552 553 Field only valid when Mpdu_frame_control_valid is set. 554 555 556 557 Retry bit from the frame control. Only valid when 558 first_msdu is set. 559 560 <legal all> 561 562 mpdu_sequence_number 563 564 Field only valid when Mpdu_sequence_control_valid is 565 set. 566 567 568 569 The sequence number from the 802.11 header. 570 571 <legal all> 572 573 epd_en 574 575 Field only valid when AST_based_lookup_valid == 1. 576 577 578 579 580 581 In case of ndp or phy_err or AST_based_lookup_valid == 582 0, this field will be set to 0 583 584 585 586 If set to one use EPD instead of LPD 587 588 589 590 591 <legal all> 592 593 all_frames_shall_be_encrypted 594 595 In case of ndp or phy_err or AST_based_lookup_valid == 596 0, this field will be set to 0 597 598 599 600 When set, all frames (data only ?) shall be encrypted. 601 If not, RX CRYPTO shall set an error flag. 602 603 <legal all> 604 605 encrypt_type 606 607 In case of ndp or phy_err or AST_based_lookup_valid == 608 0, this field will be set to 0 609 610 611 612 Indicates type of decrypt cipher used (as defined in the 613 peer entry) 614 615 616 617 <enum 0 wep_40> WEP 40-bit 618 619 <enum 1 wep_104> WEP 104-bit 620 621 <enum 2 tkip_no_mic> TKIP without MIC 622 623 <enum 3 wep_128> WEP 128-bit 624 625 <enum 4 tkip_with_mic> TKIP with MIC 626 627 <enum 5 wapi> WAPI 628 629 <enum 6 aes_ccmp_128> AES CCMP 128 630 631 <enum 7 no_cipher> No crypto 632 633 <enum 8 aes_ccmp_256> AES CCMP 256 634 635 <enum 9 aes_gcmp_128> AES CCMP 128 636 637 <enum 10 aes_gcmp_256> AES CCMP 256 638 639 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 640 641 642 643 644 <legal 0-11> 645 646 mesh_sta 647 648 In case of ndp or phy_err or AST_based_lookup_valid == 649 0, this field will be set to 0 650 651 652 653 When set, this is a Mesh (11s) STA 654 655 <legal all> 656 657 bssid_hit 658 659 In case of ndp or phy_err or AST_based_lookup_valid == 660 0, this field will be set to 0 661 662 663 664 When set, the BSSID of the incoming frame matched one of 665 the 8 BSSID register values 666 667 668 669 <legal all> 670 671 bssid_number 672 673 Field only valid when bssid_hit is set. 674 675 676 677 This number indicates which one out of the 8 BSSID 678 register values matched the incoming frame 679 680 <legal all> 681 682 tid 683 684 Field only valid when mpdu_qos_control_valid is set 685 686 687 688 The TID field in the QoS control field 689 690 <legal all> 691 692 reserved_3a 693 694 <legal 0> 695 696 pn_31_0 697 698 699 700 701 702 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 703 is valid. 704 705 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 706 WEPSeed[1], pn1}. Only pn[47:0] is valid. 707 708 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 709 pn1, pn0}. Only pn[47:0] is valid. 710 711 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 712 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 713 pn0}. pn[127:0] are valid. 714 715 716 717 718 pn_63_32 719 720 721 722 723 Bits [63:32] of the PN number. See description for 724 pn_31_0. 725 726 727 728 729 pn_95_64 730 731 732 733 734 Bits [95:64] of the PN number. See description for 735 pn_31_0. 736 737 738 739 740 pn_127_96 741 742 743 744 745 Bits [127:96] of the PN number. See description for 746 pn_31_0. 747 748 749 750 751 peer_meta_data 752 753 In case of ndp or phy_err or AST_based_lookup_valid == 754 0, this field will be set to 0 755 756 757 758 Meta data that SW has programmed in the Peer table entry 759 of the transmitting STA. 760 761 <legal all> 762 763 struct rxpt_classify_info rxpt_classify_info_details 764 765 In case of ndp or phy_err or AST_based_lookup_valid == 766 0, this field will be set to 0 767 768 769 770 RXOLE related classification info 771 772 <legal all 773 774 rx_reo_queue_desc_addr_31_0 775 776 In case of ndp or phy_err or AST_based_lookup_valid == 777 0, this field will be set to 0 778 779 780 781 Address (lower 32 bits) of the REO queue descriptor. 782 783 784 785 If no Peer entry lookup happened for this frame, the 786 value wil be set to 0, and the frame shall never be pushed 787 to REO entrance ring. 788 789 <legal all> 790 791 rx_reo_queue_desc_addr_39_32 792 793 In case of ndp or phy_err or AST_based_lookup_valid == 794 0, this field will be set to 0 795 796 797 798 Address (upper 8 bits) of the REO queue descriptor. 799 800 801 802 If no Peer entry lookup happened for this frame, the 803 value wil be set to 0, and the frame shall never be pushed 804 to REO entrance ring. 805 806 <legal all> 807 808 receive_queue_number 809 810 In case of ndp or phy_err or AST_based_lookup_valid == 811 0, this field will be set to 0 812 813 814 815 Indicates the MPDU queue ID to which this MPDU link 816 descriptor belongs 817 818 Used for tracking and debugging 819 820 <legal all> 821 822 pre_delim_err_warning 823 824 Indicates that a delimiter FCS error was found in 825 between the Previous MPDU and this MPDU. 826 827 828 829 Note that this is just a warning, and does not mean that 830 this MPDU is corrupted in any way. If it is, there will be 831 other errors indicated such as FCS or decrypt errors 832 833 834 835 In case of ndp or phy_err, this field will indicate at 836 least one of delimiters located after the last MPDU in the 837 previous PPDU has been corrupted. 838 839 first_delim_err 840 841 Indicates that the first delimiter had a FCS failure. 842 Only valid when first_mpdu and first_msdu are set. 843 844 845 846 847 reserved_11 848 849 <legal 0> 850 851 key_id_octet 852 853 854 855 856 The key ID octet from the IV. 857 858 859 860 In case of ndp or phy_err or AST_based_lookup_valid == 861 0, this field will be set to 0 862 863 <legal all> 864 865 new_peer_entry 866 867 In case of ndp or phy_err or AST_based_lookup_valid == 868 0, this field will be set to 0 869 870 871 872 Set if new RX_PEER_ENTRY TLV follows. If clear, 873 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 874 uses old peer entry or not decrypt. 875 876 <legal all> 877 878 decrypt_needed 879 880 In case of ndp or phy_err or AST_based_lookup_valid == 881 0, this field will be set to 0 882 883 884 885 Set if decryption is needed. 886 887 888 889 Note: 890 891 When RXPCU sets bit 'ast_index_not_found' and/or 892 ast_index_timeout', RXPCU will also ensure that this bit is 893 NOT set 894 895 CRYPTO for that reason only needs to evaluate this bit 896 and non of the other ones. 897 898 <legal all> 899 900 decap_type 901 902 In case of ndp or phy_err or AST_based_lookup_valid == 903 0, this field will be set to 0 904 905 906 907 Used by the OLE during decapsulation. 908 909 910 911 Indicates the decapsulation that HW will perform: 912 913 914 915 <enum 0 RAW> No encapsulation 916 917 <enum 1 Native_WiFi> 918 919 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 920 SNAP/LLC) 921 922 <enum 3 802_3> Indicate Ethernet 923 924 925 926 <legal all> 927 928 rx_insert_vlan_c_tag_padding 929 930 In case of ndp or phy_err or AST_based_lookup_valid == 931 0, this field will be set to 0 932 933 934 935 Insert 4 byte of all zeros as VLAN tag if the rx payload 936 does not have VLAN. Used during decapsulation. 937 938 <legal all> 939 940 rx_insert_vlan_s_tag_padding 941 942 In case of ndp or phy_err or AST_based_lookup_valid == 943 0, this field will be set to 0 944 945 946 947 Insert 4 byte of all zeros as double VLAN tag if the rx 948 payload does not have VLAN. Used during 949 950 <legal all> 951 952 strip_vlan_c_tag_decap 953 954 In case of ndp or phy_err or AST_based_lookup_valid == 955 0, this field will be set to 0 956 957 958 959 Strip the VLAN during decapsulation. Used by the OLE. 960 961 <legal all> 962 963 strip_vlan_s_tag_decap 964 965 In case of ndp or phy_err or AST_based_lookup_valid == 966 0, this field will be set to 0 967 968 969 970 Strip the double VLAN during decapsulation. Used by 971 the OLE. 972 973 <legal all> 974 975 pre_delim_count 976 977 The number of delimiters before this MPDU. 978 979 980 981 Note that this number is cleared at PPDU start. 982 983 984 985 If this MPDU is the first received MPDU in the PPDU and 986 this MPDU gets filtered-in, this field will indicate the 987 number of delimiters located after the last MPDU in the 988 previous PPDU. 989 990 991 992 If this MPDU is located after the first received MPDU in 993 an PPDU, this field will indicate the number of delimiters 994 located between the previous MPDU and this MPDU. 995 996 997 998 In case of ndp or phy_err, this field will indicate the 999 number of delimiters located after the last MPDU in the 1000 previous PPDU. 1001 1002 <legal all> 1003 1004 ampdu_flag 1005 1006 When set, received frame was part of an A-MPDU. 1007 1008 1009 1010 1011 <legal all> 1012 1013 bar_frame 1014 1015 In case of ndp or phy_err or AST_based_lookup_valid == 1016 0, this field will be set to 0 1017 1018 1019 1020 When set, received frame is a BAR frame 1021 1022 <legal all> 1023 1024 reserved_12 1025 1026 <legal 0>. 1027 1028 mpdu_length 1029 1030 In case of ndp or phy_err this field will be set to 0 1031 1032 1033 1034 MPDU length before decapsulation. 1035 1036 <legal all> 1037 1038 first_mpdu 1039 1040 See definition in RX attention descriptor 1041 1042 1043 1044 In case of ndp or phy_err, this field will be set. Note 1045 however that there will not actually be any data contents in 1046 the MPDU. 1047 1048 <legal all> 1049 1050 mcast_bcast 1051 1052 In case of ndp or phy_err or Phy_err_during_mpdu_header 1053 this field will be set to 0 1054 1055 1056 1057 See definition in RX attention descriptor 1058 1059 <legal all> 1060 1061 ast_index_not_found 1062 1063 In case of ndp or phy_err or Phy_err_during_mpdu_header 1064 this field will be set to 0 1065 1066 1067 1068 See definition in RX attention descriptor 1069 1070 <legal all> 1071 1072 ast_index_timeout 1073 1074 In case of ndp or phy_err or Phy_err_during_mpdu_header 1075 this field will be set to 0 1076 1077 1078 1079 See definition in RX attention descriptor 1080 1081 <legal all> 1082 1083 power_mgmt 1084 1085 In case of ndp or phy_err or Phy_err_during_mpdu_header 1086 this field will be set to 0 1087 1088 1089 1090 See definition in RX attention descriptor 1091 1092 <legal all> 1093 1094 non_qos 1095 1096 In case of ndp or phy_err or Phy_err_during_mpdu_header 1097 this field will be set to 1 1098 1099 1100 1101 See definition in RX attention descriptor 1102 1103 <legal all> 1104 1105 null_data 1106 1107 In case of ndp or phy_err or Phy_err_during_mpdu_header 1108 this field will be set to 0 1109 1110 1111 1112 See definition in RX attention descriptor 1113 1114 <legal all> 1115 1116 mgmt_type 1117 1118 In case of ndp or phy_err or Phy_err_during_mpdu_header 1119 this field will be set to 0 1120 1121 1122 1123 See definition in RX attention descriptor 1124 1125 <legal all> 1126 1127 ctrl_type 1128 1129 In case of ndp or phy_err or Phy_err_during_mpdu_header 1130 this field will be set to 0 1131 1132 1133 1134 See definition in RX attention descriptor 1135 1136 <legal all> 1137 1138 more_data 1139 1140 In case of ndp or phy_err or Phy_err_during_mpdu_header 1141 this field will be set to 0 1142 1143 1144 1145 See definition in RX attention descriptor 1146 1147 <legal all> 1148 1149 eosp 1150 1151 In case of ndp or phy_err or Phy_err_during_mpdu_header 1152 this field will be set to 0 1153 1154 1155 1156 See definition in RX attention descriptor 1157 1158 <legal all> 1159 1160 fragment_flag 1161 1162 In case of ndp or phy_err or Phy_err_during_mpdu_header 1163 this field will be set to 0 1164 1165 1166 1167 See definition in RX attention descriptor 1168 1169 <legal all> 1170 1171 order 1172 1173 In case of ndp or phy_err or Phy_err_during_mpdu_header 1174 this field will be set to 0 1175 1176 1177 1178 See definition in RX attention descriptor 1179 1180 1181 1182 <legal all> 1183 1184 u_apsd_trigger 1185 1186 In case of ndp or phy_err or Phy_err_during_mpdu_header 1187 this field will be set to 0 1188 1189 1190 1191 See definition in RX attention descriptor 1192 1193 <legal all> 1194 1195 encrypt_required 1196 1197 In case of ndp or phy_err or Phy_err_during_mpdu_header 1198 this field will be set to 0 1199 1200 1201 1202 See definition in RX attention descriptor 1203 1204 <legal all> 1205 1206 directed 1207 1208 In case of ndp or phy_err or Phy_err_during_mpdu_header 1209 this field will be set to 0 1210 1211 1212 1213 See definition in RX attention descriptor 1214 1215 <legal all> 1216 1217 reserved_13 1218 1219 <legal 0> 1220 1221 mpdu_frame_control_field 1222 1223 Field only valid when Mpdu_frame_control_valid is set 1224 1225 1226 1227 The frame control field of this received MPDU. 1228 1229 1230 1231 Field only valid when Ndp_frame and phy_err are NOT set 1232 1233 1234 1235 Bytes 0 + 1 of the received MPDU 1236 1237 <legal all> 1238 1239 mpdu_duration_field 1240 1241 Field only valid when Mpdu_duration_valid is set 1242 1243 1244 1245 The duration field of this received MPDU. 1246 1247 <legal all> 1248 1249 mac_addr_ad1_31_0 1250 1251 Field only valid when mac_addr_ad1_valid is set 1252 1253 1254 1255 The Least Significant 4 bytes of the Received Frames MAC 1256 Address AD1 1257 1258 <legal all> 1259 1260 mac_addr_ad1_47_32 1261 1262 Field only valid when mac_addr_ad1_valid is set 1263 1264 1265 1266 The 2 most significant bytes of the Received Frames MAC 1267 Address AD1 1268 1269 <legal all> 1270 1271 mac_addr_ad2_15_0 1272 1273 Field only valid when mac_addr_ad2_valid is set 1274 1275 1276 1277 The Least Significant 2 bytes of the Received Frames MAC 1278 Address AD2 1279 1280 <legal all> 1281 1282 mac_addr_ad2_47_16 1283 1284 Field only valid when mac_addr_ad2_valid is set 1285 1286 1287 1288 The 4 most significant bytes of the Received Frames MAC 1289 Address AD2 1290 1291 <legal all> 1292 1293 mac_addr_ad3_31_0 1294 1295 Field only valid when mac_addr_ad3_valid is set 1296 1297 1298 1299 The Least Significant 4 bytes of the Received Frames MAC 1300 Address AD3 1301 1302 <legal all> 1303 1304 mac_addr_ad3_47_32 1305 1306 Field only valid when mac_addr_ad3_valid is set 1307 1308 1309 1310 The 2 most significant bytes of the Received Frames MAC 1311 Address AD3 1312 1313 <legal all> 1314 1315 mpdu_sequence_control_field 1316 1317 1318 1319 1320 The sequence control field of the MPDU 1321 1322 <legal all> 1323 1324 mac_addr_ad4_31_0 1325 1326 Field only valid when mac_addr_ad4_valid is set 1327 1328 1329 1330 The Least Significant 4 bytes of the Received Frames MAC 1331 Address AD4 1332 1333 <legal all> 1334 1335 mac_addr_ad4_47_32 1336 1337 Field only valid when mac_addr_ad4_valid is set 1338 1339 1340 1341 The 2 most significant bytes of the Received Frames MAC 1342 Address AD4 1343 1344 <legal all> 1345 1346 mpdu_qos_control_field 1347 1348 Field only valid when mpdu_qos_control_valid is set 1349 1350 1351 1352 The sequence control field of the MPDU 1353 1354 <legal all> 1355 1356 mpdu_ht_control_field 1357 1358 Field only valid when mpdu_qos_control_valid is set 1359 1360 1361 1362 The HT control field of the MPDU 1363 1364 <legal all> 1365 */ 1366 1367 1368 /* Description RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY 1369 1370 Field indicates what the reason was that this MPDU frame 1371 was allowed to come into the receive path by RXPCU 1372 1373 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 1374 frame filter programming of rxpcu 1375 1376 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 1377 regular frame filter and would have been dropped, were it 1378 not for the frame fitting into the 'monitor_client' 1379 category. 1380 1381 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 1382 regular frame filter and also did not pass the 1383 rxpcu_monitor_client filter. It would have been dropped 1384 accept that it did pass the 'monitor_other' category. 1385 1386 1387 1388 Note: for ndp frame, if it was expected because the 1389 preceding NDPA was filter_pass, the setting 1390 rxpcu_filter_pass will be used. This setting will also be 1391 used for every ndp frame in case Promiscuous mode is 1392 enabled. 1393 1394 1395 1396 In case promiscuous is not enabled, and an NDP is not 1397 preceded by a NPDA filter pass frame, the only other setting 1398 that could appear here for the NDP is rxpcu_monitor_other. 1399 1400 (rxpcu has a configuration bit specifically for this 1401 scenario) 1402 1403 1404 1405 Note: for 1406 1407 <legal 0-2> 1408 */ 1409 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 1410 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 1411 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 1412 1413 /* Description RX_MPDU_INFO_0_SW_FRAME_GROUP_ID 1414 1415 SW processes frames based on certain classifications. 1416 This field indicates to what sw classification this MPDU is 1417 mapped. 1418 1419 The classification is given in priority order 1420 1421 1422 1423 <enum 0 sw_frame_group_NDP_frame> Note: The 1424 corresponding Rxpcu_Mpdu_filter_in_category can be 1425 rxpcu_filter_pass or rxpcu_monitor_other 1426 1427 1428 1429 <enum 1 sw_frame_group_Multicast_data> 1430 1431 <enum 2 sw_frame_group_Unicast_data> 1432 1433 <enum 3 sw_frame_group_Null_data > This includes mpdus 1434 of type Data Null as well as QoS Data Null 1435 1436 1437 1438 <enum 4 sw_frame_group_mgmt_0000 > 1439 1440 <enum 5 sw_frame_group_mgmt_0001 > 1441 1442 <enum 6 sw_frame_group_mgmt_0010 > 1443 1444 <enum 7 sw_frame_group_mgmt_0011 > 1445 1446 <enum 8 sw_frame_group_mgmt_0100 > 1447 1448 <enum 9 sw_frame_group_mgmt_0101 > 1449 1450 <enum 10 sw_frame_group_mgmt_0110 > 1451 1452 <enum 11 sw_frame_group_mgmt_0111 > 1453 1454 <enum 12 sw_frame_group_mgmt_1000 > 1455 1456 <enum 13 sw_frame_group_mgmt_1001 > 1457 1458 <enum 14 sw_frame_group_mgmt_1010 > 1459 1460 <enum 15 sw_frame_group_mgmt_1011 > 1461 1462 <enum 16 sw_frame_group_mgmt_1100 > 1463 1464 <enum 17 sw_frame_group_mgmt_1101 > 1465 1466 <enum 18 sw_frame_group_mgmt_1110 > 1467 1468 <enum 19 sw_frame_group_mgmt_1111 > 1469 1470 1471 1472 <enum 20 sw_frame_group_ctrl_0000 > 1473 1474 <enum 21 sw_frame_group_ctrl_0001 > 1475 1476 <enum 22 sw_frame_group_ctrl_0010 > 1477 1478 <enum 23 sw_frame_group_ctrl_0011 > 1479 1480 <enum 24 sw_frame_group_ctrl_0100 > 1481 1482 <enum 25 sw_frame_group_ctrl_0101 > 1483 1484 <enum 26 sw_frame_group_ctrl_0110 > 1485 1486 <enum 27 sw_frame_group_ctrl_0111 > 1487 1488 <enum 28 sw_frame_group_ctrl_1000 > 1489 1490 <enum 29 sw_frame_group_ctrl_1001 > 1491 1492 <enum 30 sw_frame_group_ctrl_1010 > 1493 1494 <enum 31 sw_frame_group_ctrl_1011 > 1495 1496 <enum 32 sw_frame_group_ctrl_1100 > 1497 1498 <enum 33 sw_frame_group_ctrl_1101 > 1499 1500 <enum 34 sw_frame_group_ctrl_1110 > 1501 1502 <enum 35 sw_frame_group_ctrl_1111 > 1503 1504 1505 1506 <enum 36 sw_frame_group_unsupported> This covers type 3 1507 and protocol version != 0 1508 1509 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1510 can only be rxpcu_monitor_other 1511 1512 1513 1514 1515 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1516 can be rxpcu_filter_pass 1517 1518 1519 1520 <legal 0-37> 1521 */ 1522 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 1523 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB 2 1524 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 1525 1526 /* Description RX_MPDU_INFO_0_NDP_FRAME 1527 1528 When set, the received frame was an NDP frame, and thus 1529 there will be no MPDU data. 1530 1531 <legal all> 1532 */ 1533 #define RX_MPDU_INFO_0_NDP_FRAME_OFFSET 0x00000000 1534 #define RX_MPDU_INFO_0_NDP_FRAME_LSB 9 1535 #define RX_MPDU_INFO_0_NDP_FRAME_MASK 0x00000200 1536 1537 /* Description RX_MPDU_INFO_0_PHY_ERR 1538 1539 When set, a PHY error was received before MAC received 1540 any data, and thus there will be no MPDU data. 1541 1542 <legal all> 1543 */ 1544 #define RX_MPDU_INFO_0_PHY_ERR_OFFSET 0x00000000 1545 #define RX_MPDU_INFO_0_PHY_ERR_LSB 10 1546 #define RX_MPDU_INFO_0_PHY_ERR_MASK 0x00000400 1547 1548 /* Description RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER 1549 1550 When set, a PHY error was received before MAC received 1551 the complete MPDU header which was needed for proper 1552 decoding 1553 1554 <legal all> 1555 */ 1556 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000000 1557 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB 11 1558 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 1559 1560 /* Description RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR 1561 1562 Set when RXPCU detected a version error in the Frame 1563 control field 1564 1565 <legal all> 1566 */ 1567 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET 0x00000000 1568 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB 12 1569 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK 0x00001000 1570 1571 /* Description RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID 1572 1573 When set, AST based lookup for this frame has found a 1574 valid result. 1575 1576 1577 1578 Note that for NDP frame this will never be set 1579 1580 <legal all> 1581 */ 1582 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET 0x00000000 1583 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB 13 1584 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK 0x00002000 1585 1586 /* Description RX_MPDU_INFO_0_RESERVED_0A 1587 1588 <legal 0> 1589 */ 1590 #define RX_MPDU_INFO_0_RESERVED_0A_OFFSET 0x00000000 1591 #define RX_MPDU_INFO_0_RESERVED_0A_LSB 14 1592 #define RX_MPDU_INFO_0_RESERVED_0A_MASK 0x0000c000 1593 1594 /* Description RX_MPDU_INFO_0_PHY_PPDU_ID 1595 1596 A ppdu counter value that PHY increments for every PPDU 1597 received. The counter value wraps around 1598 1599 <legal all> 1600 */ 1601 #define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 1602 #define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB 16 1603 #define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK 0xffff0000 1604 1605 /* Description RX_MPDU_INFO_1_AST_INDEX 1606 1607 This field indicates the index of the AST entry 1608 corresponding to this MPDU. It is provided by the GSE module 1609 instantiated in RXPCU. 1610 1611 A value of 0xFFFF indicates an invalid AST index, 1612 meaning that No AST entry was found or NO AST search was 1613 performed 1614 1615 1616 1617 In case of ndp or phy_err, this field will be set to 1618 0xFFFF 1619 1620 <legal all> 1621 */ 1622 #define RX_MPDU_INFO_1_AST_INDEX_OFFSET 0x00000004 1623 #define RX_MPDU_INFO_1_AST_INDEX_LSB 0 1624 #define RX_MPDU_INFO_1_AST_INDEX_MASK 0x0000ffff 1625 1626 /* Description RX_MPDU_INFO_1_SW_PEER_ID 1627 1628 In case of ndp or phy_err or AST_based_lookup_valid == 1629 0, this field will be set to 0 1630 1631 1632 1633 This field indicates a unique peer identifier. It is set 1634 equal to field 'sw_peer_id' from the AST entry 1635 1636 1637 1638 <legal all> 1639 */ 1640 #define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET 0x00000004 1641 #define RX_MPDU_INFO_1_SW_PEER_ID_LSB 16 1642 #define RX_MPDU_INFO_1_SW_PEER_ID_MASK 0xffff0000 1643 1644 /* Description RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID 1645 1646 When set, the field Mpdu_Frame_control_field has valid 1647 information 1648 1649 1650 1651 1652 <legal all> 1653 */ 1654 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000008 1655 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB 0 1656 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 1657 1658 /* Description RX_MPDU_INFO_2_MPDU_DURATION_VALID 1659 1660 When set, the field Mpdu_duration_field has valid 1661 information 1662 1663 1664 1665 1666 <legal all> 1667 */ 1668 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET 0x00000008 1669 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB 1 1670 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK 0x00000002 1671 1672 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID 1673 1674 When set, the fields mac_addr_ad1_..... have valid 1675 information 1676 1677 1678 1679 1680 <legal all> 1681 */ 1682 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET 0x00000008 1683 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB 2 1684 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK 0x00000004 1685 1686 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID 1687 1688 When set, the fields mac_addr_ad2_..... have valid 1689 information 1690 1691 1692 1693 1694 1695 1696 1697 <legal all> 1698 */ 1699 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET 0x00000008 1700 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB 3 1701 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK 0x00000008 1702 1703 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID 1704 1705 When set, the fields mac_addr_ad3_..... have valid 1706 information 1707 1708 1709 1710 1711 1712 1713 1714 <legal all> 1715 */ 1716 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET 0x00000008 1717 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB 4 1718 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK 0x00000010 1719 1720 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID 1721 1722 When set, the fields mac_addr_ad4_..... have valid 1723 information 1724 1725 1726 1727 1728 1729 1730 1731 <legal all> 1732 */ 1733 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET 0x00000008 1734 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB 5 1735 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK 0x00000020 1736 1737 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID 1738 1739 When set, the fields mpdu_sequence_control_field and 1740 mpdu_sequence_number have valid information as well as field 1741 1742 1743 1744 For MPDUs without a sequence control field, this field 1745 will not be set. 1746 1747 1748 1749 1750 <legal all> 1751 */ 1752 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000008 1753 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1754 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1755 1756 /* Description RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID 1757 1758 When set, the field mpdu_qos_control_field has valid 1759 information 1760 1761 1762 1763 For MPDUs without a QoS control field, this field will 1764 not be set. 1765 1766 1767 1768 1769 <legal all> 1770 */ 1771 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 1772 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB 7 1773 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1774 1775 /* Description RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID 1776 1777 When set, the field mpdu_HT_control_field has valid 1778 information 1779 1780 1781 1782 For MPDUs without a HT control field, this field will 1783 not be set. 1784 1785 1786 1787 1788 <legal all> 1789 */ 1790 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET 0x00000008 1791 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB 8 1792 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1793 1794 /* Description RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID 1795 1796 When set, the encryption related info fields, like IV 1797 and PN are valid 1798 1799 1800 1801 For MPDUs that are not encrypted, this will not be set. 1802 1803 1804 1805 1806 <legal all> 1807 */ 1808 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000008 1809 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1810 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1811 1812 /* Description RX_MPDU_INFO_2_RESERVED_2A 1813 1814 <legal 0> 1815 */ 1816 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 1817 #define RX_MPDU_INFO_2_RESERVED_2A_LSB 10 1818 #define RX_MPDU_INFO_2_RESERVED_2A_MASK 0x0000fc00 1819 1820 /* Description RX_MPDU_INFO_2_FR_DS 1821 1822 Field only valid when Mpdu_frame_control_valid is set 1823 1824 1825 1826 Set if the from DS bit is set in the frame control. 1827 1828 <legal all> 1829 */ 1830 #define RX_MPDU_INFO_2_FR_DS_OFFSET 0x00000008 1831 #define RX_MPDU_INFO_2_FR_DS_LSB 16 1832 #define RX_MPDU_INFO_2_FR_DS_MASK 0x00010000 1833 1834 /* Description RX_MPDU_INFO_2_TO_DS 1835 1836 Field only valid when Mpdu_frame_control_valid is set 1837 1838 1839 1840 Set if the to DS bit is set in the frame control. 1841 1842 <legal all> 1843 */ 1844 #define RX_MPDU_INFO_2_TO_DS_OFFSET 0x00000008 1845 #define RX_MPDU_INFO_2_TO_DS_LSB 17 1846 #define RX_MPDU_INFO_2_TO_DS_MASK 0x00020000 1847 1848 /* Description RX_MPDU_INFO_2_ENCRYPTED 1849 1850 Field only valid when Mpdu_frame_control_valid is set. 1851 1852 1853 1854 Protected bit from the frame control. 1855 1856 <legal all> 1857 */ 1858 #define RX_MPDU_INFO_2_ENCRYPTED_OFFSET 0x00000008 1859 #define RX_MPDU_INFO_2_ENCRYPTED_LSB 18 1860 #define RX_MPDU_INFO_2_ENCRYPTED_MASK 0x00040000 1861 1862 /* Description RX_MPDU_INFO_2_MPDU_RETRY 1863 1864 Field only valid when Mpdu_frame_control_valid is set. 1865 1866 1867 1868 Retry bit from the frame control. Only valid when 1869 first_msdu is set. 1870 1871 <legal all> 1872 */ 1873 #define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET 0x00000008 1874 #define RX_MPDU_INFO_2_MPDU_RETRY_LSB 19 1875 #define RX_MPDU_INFO_2_MPDU_RETRY_MASK 0x00080000 1876 1877 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER 1878 1879 Field only valid when Mpdu_sequence_control_valid is 1880 set. 1881 1882 1883 1884 The sequence number from the 802.11 header. 1885 1886 <legal all> 1887 */ 1888 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 1889 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB 20 1890 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1891 1892 /* Description RX_MPDU_INFO_3_EPD_EN 1893 1894 Field only valid when AST_based_lookup_valid == 1. 1895 1896 1897 1898 1899 1900 In case of ndp or phy_err or AST_based_lookup_valid == 1901 0, this field will be set to 0 1902 1903 1904 1905 If set to one use EPD instead of LPD 1906 1907 1908 1909 1910 <legal all> 1911 */ 1912 #define RX_MPDU_INFO_3_EPD_EN_OFFSET 0x0000000c 1913 #define RX_MPDU_INFO_3_EPD_EN_LSB 0 1914 #define RX_MPDU_INFO_3_EPD_EN_MASK 0x00000001 1915 1916 /* Description RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED 1917 1918 In case of ndp or phy_err or AST_based_lookup_valid == 1919 0, this field will be set to 0 1920 1921 1922 1923 When set, all frames (data only ?) shall be encrypted. 1924 If not, RX CRYPTO shall set an error flag. 1925 1926 <legal all> 1927 */ 1928 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000c 1929 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 1930 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 1931 1932 /* Description RX_MPDU_INFO_3_ENCRYPT_TYPE 1933 1934 In case of ndp or phy_err or AST_based_lookup_valid == 1935 0, this field will be set to 0 1936 1937 1938 1939 Indicates type of decrypt cipher used (as defined in the 1940 peer entry) 1941 1942 1943 1944 <enum 0 wep_40> WEP 40-bit 1945 1946 <enum 1 wep_104> WEP 104-bit 1947 1948 <enum 2 tkip_no_mic> TKIP without MIC 1949 1950 <enum 3 wep_128> WEP 128-bit 1951 1952 <enum 4 tkip_with_mic> TKIP with MIC 1953 1954 <enum 5 wapi> WAPI 1955 1956 <enum 6 aes_ccmp_128> AES CCMP 128 1957 1958 <enum 7 no_cipher> No crypto 1959 1960 <enum 8 aes_ccmp_256> AES CCMP 256 1961 1962 <enum 9 aes_gcmp_128> AES CCMP 128 1963 1964 <enum 10 aes_gcmp_256> AES CCMP 256 1965 1966 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 1967 1968 1969 1970 1971 <legal 0-11> 1972 */ 1973 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET 0x0000000c 1974 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB 2 1975 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK 0x0000003c 1976 1977 /* Description RX_MPDU_INFO_3_MESH_STA 1978 1979 In case of ndp or phy_err or AST_based_lookup_valid == 1980 0, this field will be set to 0 1981 1982 1983 1984 When set, this is a Mesh (11s) STA 1985 1986 <legal all> 1987 */ 1988 #define RX_MPDU_INFO_3_MESH_STA_OFFSET 0x0000000c 1989 #define RX_MPDU_INFO_3_MESH_STA_LSB 6 1990 #define RX_MPDU_INFO_3_MESH_STA_MASK 0x00000040 1991 1992 /* Description RX_MPDU_INFO_3_BSSID_HIT 1993 1994 In case of ndp or phy_err or AST_based_lookup_valid == 1995 0, this field will be set to 0 1996 1997 1998 1999 When set, the BSSID of the incoming frame matched one of 2000 the 8 BSSID register values 2001 2002 2003 2004 <legal all> 2005 */ 2006 #define RX_MPDU_INFO_3_BSSID_HIT_OFFSET 0x0000000c 2007 #define RX_MPDU_INFO_3_BSSID_HIT_LSB 7 2008 #define RX_MPDU_INFO_3_BSSID_HIT_MASK 0x00000080 2009 2010 /* Description RX_MPDU_INFO_3_BSSID_NUMBER 2011 2012 Field only valid when bssid_hit is set. 2013 2014 2015 2016 This number indicates which one out of the 8 BSSID 2017 register values matched the incoming frame 2018 2019 <legal all> 2020 */ 2021 #define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET 0x0000000c 2022 #define RX_MPDU_INFO_3_BSSID_NUMBER_LSB 8 2023 #define RX_MPDU_INFO_3_BSSID_NUMBER_MASK 0x00000f00 2024 2025 /* Description RX_MPDU_INFO_3_TID 2026 2027 Field only valid when mpdu_qos_control_valid is set 2028 2029 2030 2031 The TID field in the QoS control field 2032 2033 <legal all> 2034 */ 2035 #define RX_MPDU_INFO_3_TID_OFFSET 0x0000000c 2036 #define RX_MPDU_INFO_3_TID_LSB 12 2037 #define RX_MPDU_INFO_3_TID_MASK 0x0000f000 2038 2039 /* Description RX_MPDU_INFO_3_RESERVED_3A 2040 2041 <legal 0> 2042 */ 2043 #define RX_MPDU_INFO_3_RESERVED_3A_OFFSET 0x0000000c 2044 #define RX_MPDU_INFO_3_RESERVED_3A_LSB 16 2045 #define RX_MPDU_INFO_3_RESERVED_3A_MASK 0xffff0000 2046 2047 /* Description RX_MPDU_INFO_4_PN_31_0 2048 2049 2050 2051 2052 2053 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 2054 is valid. 2055 2056 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 2057 WEPSeed[1], pn1}. Only pn[47:0] is valid. 2058 2059 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 2060 pn1, pn0}. Only pn[47:0] is valid. 2061 2062 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 2063 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 2064 pn0}. pn[127:0] are valid. 2065 2066 2067 2068 */ 2069 #define RX_MPDU_INFO_4_PN_31_0_OFFSET 0x00000010 2070 #define RX_MPDU_INFO_4_PN_31_0_LSB 0 2071 #define RX_MPDU_INFO_4_PN_31_0_MASK 0xffffffff 2072 2073 /* Description RX_MPDU_INFO_5_PN_63_32 2074 2075 2076 2077 2078 Bits [63:32] of the PN number. See description for 2079 pn_31_0. 2080 2081 2082 2083 */ 2084 #define RX_MPDU_INFO_5_PN_63_32_OFFSET 0x00000014 2085 #define RX_MPDU_INFO_5_PN_63_32_LSB 0 2086 #define RX_MPDU_INFO_5_PN_63_32_MASK 0xffffffff 2087 2088 /* Description RX_MPDU_INFO_6_PN_95_64 2089 2090 2091 2092 2093 Bits [95:64] of the PN number. See description for 2094 pn_31_0. 2095 2096 2097 2098 */ 2099 #define RX_MPDU_INFO_6_PN_95_64_OFFSET 0x00000018 2100 #define RX_MPDU_INFO_6_PN_95_64_LSB 0 2101 #define RX_MPDU_INFO_6_PN_95_64_MASK 0xffffffff 2102 2103 /* Description RX_MPDU_INFO_7_PN_127_96 2104 2105 2106 2107 2108 Bits [127:96] of the PN number. See description for 2109 pn_31_0. 2110 2111 2112 2113 */ 2114 #define RX_MPDU_INFO_7_PN_127_96_OFFSET 0x0000001c 2115 #define RX_MPDU_INFO_7_PN_127_96_LSB 0 2116 #define RX_MPDU_INFO_7_PN_127_96_MASK 0xffffffff 2117 2118 /* Description RX_MPDU_INFO_8_PEER_META_DATA 2119 2120 In case of ndp or phy_err or AST_based_lookup_valid == 2121 0, this field will be set to 0 2122 2123 2124 2125 Meta data that SW has programmed in the Peer table entry 2126 of the transmitting STA. 2127 2128 <legal all> 2129 */ 2130 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 2131 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 2132 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 2133 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_OFFSET 0x00000024 2134 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_LSB 0 2135 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_MASK 0xffffffff 2136 2137 /* Description RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0 2138 2139 In case of ndp or phy_err or AST_based_lookup_valid == 2140 0, this field will be set to 0 2141 2142 2143 2144 Address (lower 32 bits) of the REO queue descriptor. 2145 2146 2147 2148 If no Peer entry lookup happened for this frame, the 2149 value wil be set to 0, and the frame shall never be pushed 2150 to REO entrance ring. 2151 2152 <legal all> 2153 */ 2154 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000028 2155 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 2156 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 2157 2158 /* Description RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32 2159 2160 In case of ndp or phy_err or AST_based_lookup_valid == 2161 0, this field will be set to 0 2162 2163 2164 2165 Address (upper 8 bits) of the REO queue descriptor. 2166 2167 2168 2169 If no Peer entry lookup happened for this frame, the 2170 value wil be set to 0, and the frame shall never be pushed 2171 to REO entrance ring. 2172 2173 <legal all> 2174 */ 2175 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000002c 2176 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 2177 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 2178 2179 /* Description RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER 2180 2181 In case of ndp or phy_err or AST_based_lookup_valid == 2182 0, this field will be set to 0 2183 2184 2185 2186 Indicates the MPDU queue ID to which this MPDU link 2187 descriptor belongs 2188 2189 Used for tracking and debugging 2190 2191 <legal all> 2192 */ 2193 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000002c 2194 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB 8 2195 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 2196 2197 /* Description RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING 2198 2199 Indicates that a delimiter FCS error was found in 2200 between the Previous MPDU and this MPDU. 2201 2202 2203 2204 Note that this is just a warning, and does not mean that 2205 this MPDU is corrupted in any way. If it is, there will be 2206 other errors indicated such as FCS or decrypt errors 2207 2208 2209 2210 In case of ndp or phy_err, this field will indicate at 2211 least one of delimiters located after the last MPDU in the 2212 previous PPDU has been corrupted. 2213 */ 2214 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c 2215 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB 24 2216 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK 0x01000000 2217 2218 /* Description RX_MPDU_INFO_11_FIRST_DELIM_ERR 2219 2220 Indicates that the first delimiter had a FCS failure. 2221 Only valid when first_mpdu and first_msdu are set. 2222 2223 2224 2225 */ 2226 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET 0x0000002c 2227 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB 25 2228 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK 0x02000000 2229 2230 /* Description RX_MPDU_INFO_11_RESERVED_11 2231 2232 <legal 0> 2233 */ 2234 #define RX_MPDU_INFO_11_RESERVED_11_OFFSET 0x0000002c 2235 #define RX_MPDU_INFO_11_RESERVED_11_LSB 26 2236 #define RX_MPDU_INFO_11_RESERVED_11_MASK 0xfc000000 2237 2238 /* Description RX_MPDU_INFO_12_KEY_ID_OCTET 2239 2240 2241 2242 2243 The key ID octet from the IV. 2244 2245 2246 2247 In case of ndp or phy_err or AST_based_lookup_valid == 2248 0, this field will be set to 0 2249 2250 <legal all> 2251 */ 2252 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 2253 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 2254 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 2255 2256 /* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY 2257 2258 In case of ndp or phy_err or AST_based_lookup_valid == 2259 0, this field will be set to 0 2260 2261 2262 2263 Set if new RX_PEER_ENTRY TLV follows. If clear, 2264 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 2265 uses old peer entry or not decrypt. 2266 2267 <legal all> 2268 */ 2269 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 2270 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 2271 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 2272 2273 /* Description RX_MPDU_INFO_12_DECRYPT_NEEDED 2274 2275 In case of ndp or phy_err or AST_based_lookup_valid == 2276 0, this field will be set to 0 2277 2278 2279 2280 Set if decryption is needed. 2281 2282 2283 2284 Note: 2285 2286 When RXPCU sets bit 'ast_index_not_found' and/or 2287 ast_index_timeout', RXPCU will also ensure that this bit is 2288 NOT set 2289 2290 CRYPTO for that reason only needs to evaluate this bit 2291 and non of the other ones. 2292 2293 <legal all> 2294 */ 2295 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 2296 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 2297 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 2298 2299 /* Description RX_MPDU_INFO_12_DECAP_TYPE 2300 2301 In case of ndp or phy_err or AST_based_lookup_valid == 2302 0, this field will be set to 0 2303 2304 2305 2306 Used by the OLE during decapsulation. 2307 2308 2309 2310 Indicates the decapsulation that HW will perform: 2311 2312 2313 2314 <enum 0 RAW> No encapsulation 2315 2316 <enum 1 Native_WiFi> 2317 2318 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 2319 SNAP/LLC) 2320 2321 <enum 3 802_3> Indicate Ethernet 2322 2323 2324 2325 <legal all> 2326 */ 2327 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 2328 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 2329 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 2330 2331 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING 2332 2333 In case of ndp or phy_err or AST_based_lookup_valid == 2334 0, this field will be set to 0 2335 2336 2337 2338 Insert 4 byte of all zeros as VLAN tag if the rx payload 2339 does not have VLAN. Used during decapsulation. 2340 2341 <legal all> 2342 */ 2343 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 2344 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 2345 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 2346 2347 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING 2348 2349 In case of ndp or phy_err or AST_based_lookup_valid == 2350 0, this field will be set to 0 2351 2352 2353 2354 Insert 4 byte of all zeros as double VLAN tag if the rx 2355 payload does not have VLAN. Used during 2356 2357 <legal all> 2358 */ 2359 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 2360 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 2361 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 2362 2363 /* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP 2364 2365 In case of ndp or phy_err or AST_based_lookup_valid == 2366 0, this field will be set to 0 2367 2368 2369 2370 Strip the VLAN during decapsulation. Used by the OLE. 2371 2372 <legal all> 2373 */ 2374 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 2375 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 2376 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 2377 2378 /* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP 2379 2380 In case of ndp or phy_err or AST_based_lookup_valid == 2381 0, this field will be set to 0 2382 2383 2384 2385 Strip the double VLAN during decapsulation. Used by 2386 the OLE. 2387 2388 <legal all> 2389 */ 2390 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 2391 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 2392 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 2393 2394 /* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT 2395 2396 The number of delimiters before this MPDU. 2397 2398 2399 2400 Note that this number is cleared at PPDU start. 2401 2402 2403 2404 If this MPDU is the first received MPDU in the PPDU and 2405 this MPDU gets filtered-in, this field will indicate the 2406 number of delimiters located after the last MPDU in the 2407 previous PPDU. 2408 2409 2410 2411 If this MPDU is located after the first received MPDU in 2412 an PPDU, this field will indicate the number of delimiters 2413 located between the previous MPDU and this MPDU. 2414 2415 2416 2417 In case of ndp or phy_err, this field will indicate the 2418 number of delimiters located after the last MPDU in the 2419 previous PPDU. 2420 2421 <legal all> 2422 */ 2423 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 2424 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 2425 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 2426 2427 /* Description RX_MPDU_INFO_12_AMPDU_FLAG 2428 2429 When set, received frame was part of an A-MPDU. 2430 2431 2432 2433 2434 <legal all> 2435 */ 2436 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 2437 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 2438 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 2439 2440 /* Description RX_MPDU_INFO_12_BAR_FRAME 2441 2442 In case of ndp or phy_err or AST_based_lookup_valid == 2443 0, this field will be set to 0 2444 2445 2446 2447 When set, received frame is a BAR frame 2448 2449 <legal all> 2450 */ 2451 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 2452 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 2453 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 2454 2455 /* Description RX_MPDU_INFO_12_RESERVED_12 2456 2457 <legal 0>. 2458 */ 2459 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 2460 #define RX_MPDU_INFO_12_RESERVED_12_LSB 30 2461 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0xc0000000 2462 2463 /* Description RX_MPDU_INFO_13_MPDU_LENGTH 2464 2465 In case of ndp or phy_err this field will be set to 0 2466 2467 2468 2469 MPDU length before decapsulation. 2470 2471 <legal all> 2472 */ 2473 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 2474 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 2475 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 2476 2477 /* Description RX_MPDU_INFO_13_FIRST_MPDU 2478 2479 See definition in RX attention descriptor 2480 2481 2482 2483 In case of ndp or phy_err, this field will be set. Note 2484 however that there will not actually be any data contents in 2485 the MPDU. 2486 2487 <legal all> 2488 */ 2489 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 2490 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 2491 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 2492 2493 /* Description RX_MPDU_INFO_13_MCAST_BCAST 2494 2495 In case of ndp or phy_err or Phy_err_during_mpdu_header 2496 this field will be set to 0 2497 2498 2499 2500 See definition in RX attention descriptor 2501 2502 <legal all> 2503 */ 2504 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 2505 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 2506 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 2507 2508 /* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND 2509 2510 In case of ndp or phy_err or Phy_err_during_mpdu_header 2511 this field will be set to 0 2512 2513 2514 2515 See definition in RX attention descriptor 2516 2517 <legal all> 2518 */ 2519 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 2520 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 2521 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 2522 2523 /* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT 2524 2525 In case of ndp or phy_err or Phy_err_during_mpdu_header 2526 this field will be set to 0 2527 2528 2529 2530 See definition in RX attention descriptor 2531 2532 <legal all> 2533 */ 2534 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 2535 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 2536 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 2537 2538 /* Description RX_MPDU_INFO_13_POWER_MGMT 2539 2540 In case of ndp or phy_err or Phy_err_during_mpdu_header 2541 this field will be set to 0 2542 2543 2544 2545 See definition in RX attention descriptor 2546 2547 <legal all> 2548 */ 2549 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 2550 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 2551 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 2552 2553 /* Description RX_MPDU_INFO_13_NON_QOS 2554 2555 In case of ndp or phy_err or Phy_err_during_mpdu_header 2556 this field will be set to 1 2557 2558 2559 2560 See definition in RX attention descriptor 2561 2562 <legal all> 2563 */ 2564 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 2565 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 2566 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 2567 2568 /* Description RX_MPDU_INFO_13_NULL_DATA 2569 2570 In case of ndp or phy_err or Phy_err_during_mpdu_header 2571 this field will be set to 0 2572 2573 2574 2575 See definition in RX attention descriptor 2576 2577 <legal all> 2578 */ 2579 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 2580 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 2581 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 2582 2583 /* Description RX_MPDU_INFO_13_MGMT_TYPE 2584 2585 In case of ndp or phy_err or Phy_err_during_mpdu_header 2586 this field will be set to 0 2587 2588 2589 2590 See definition in RX attention descriptor 2591 2592 <legal all> 2593 */ 2594 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 2595 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 2596 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 2597 2598 /* Description RX_MPDU_INFO_13_CTRL_TYPE 2599 2600 In case of ndp or phy_err or Phy_err_during_mpdu_header 2601 this field will be set to 0 2602 2603 2604 2605 See definition in RX attention descriptor 2606 2607 <legal all> 2608 */ 2609 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 2610 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 2611 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 2612 2613 /* Description RX_MPDU_INFO_13_MORE_DATA 2614 2615 In case of ndp or phy_err or Phy_err_during_mpdu_header 2616 this field will be set to 0 2617 2618 2619 2620 See definition in RX attention descriptor 2621 2622 <legal all> 2623 */ 2624 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 2625 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 2626 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 2627 2628 /* Description RX_MPDU_INFO_13_EOSP 2629 2630 In case of ndp or phy_err or Phy_err_during_mpdu_header 2631 this field will be set to 0 2632 2633 2634 2635 See definition in RX attention descriptor 2636 2637 <legal all> 2638 */ 2639 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 2640 #define RX_MPDU_INFO_13_EOSP_LSB 24 2641 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 2642 2643 /* Description RX_MPDU_INFO_13_FRAGMENT_FLAG 2644 2645 In case of ndp or phy_err or Phy_err_during_mpdu_header 2646 this field will be set to 0 2647 2648 2649 2650 See definition in RX attention descriptor 2651 2652 <legal all> 2653 */ 2654 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 2655 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 2656 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 2657 2658 /* Description RX_MPDU_INFO_13_ORDER 2659 2660 In case of ndp or phy_err or Phy_err_during_mpdu_header 2661 this field will be set to 0 2662 2663 2664 2665 See definition in RX attention descriptor 2666 2667 2668 2669 <legal all> 2670 */ 2671 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 2672 #define RX_MPDU_INFO_13_ORDER_LSB 26 2673 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 2674 2675 /* Description RX_MPDU_INFO_13_U_APSD_TRIGGER 2676 2677 In case of ndp or phy_err or Phy_err_during_mpdu_header 2678 this field will be set to 0 2679 2680 2681 2682 See definition in RX attention descriptor 2683 2684 <legal all> 2685 */ 2686 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 2687 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 2688 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 2689 2690 /* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED 2691 2692 In case of ndp or phy_err or Phy_err_during_mpdu_header 2693 this field will be set to 0 2694 2695 2696 2697 See definition in RX attention descriptor 2698 2699 <legal all> 2700 */ 2701 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 2702 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 2703 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 2704 2705 /* Description RX_MPDU_INFO_13_DIRECTED 2706 2707 In case of ndp or phy_err or Phy_err_during_mpdu_header 2708 this field will be set to 0 2709 2710 2711 2712 See definition in RX attention descriptor 2713 2714 <legal all> 2715 */ 2716 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 2717 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 2718 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 2719 2720 /* Description RX_MPDU_INFO_13_RESERVED_13 2721 2722 <legal 0> 2723 */ 2724 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 2725 #define RX_MPDU_INFO_13_RESERVED_13_LSB 30 2726 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0xc0000000 2727 2728 /* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD 2729 2730 Field only valid when Mpdu_frame_control_valid is set 2731 2732 2733 2734 The frame control field of this received MPDU. 2735 2736 2737 2738 Field only valid when Ndp_frame and phy_err are NOT set 2739 2740 2741 2742 Bytes 0 + 1 of the received MPDU 2743 2744 <legal all> 2745 */ 2746 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 2747 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 2748 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 2749 2750 /* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD 2751 2752 Field only valid when Mpdu_duration_valid is set 2753 2754 2755 2756 The duration field of this received MPDU. 2757 2758 <legal all> 2759 */ 2760 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 2761 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 2762 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 2763 2764 /* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 2765 2766 Field only valid when mac_addr_ad1_valid is set 2767 2768 2769 2770 The Least Significant 4 bytes of the Received Frames MAC 2771 Address AD1 2772 2773 <legal all> 2774 */ 2775 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 2776 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 2777 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 2778 2779 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 2780 2781 Field only valid when mac_addr_ad1_valid is set 2782 2783 2784 2785 The 2 most significant bytes of the Received Frames MAC 2786 Address AD1 2787 2788 <legal all> 2789 */ 2790 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 2791 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 2792 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 2793 2794 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 2795 2796 Field only valid when mac_addr_ad2_valid is set 2797 2798 2799 2800 The Least Significant 2 bytes of the Received Frames MAC 2801 Address AD2 2802 2803 <legal all> 2804 */ 2805 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 2806 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 2807 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 2808 2809 /* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 2810 2811 Field only valid when mac_addr_ad2_valid is set 2812 2813 2814 2815 The 4 most significant bytes of the Received Frames MAC 2816 Address AD2 2817 2818 <legal all> 2819 */ 2820 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 2821 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 2822 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 2823 2824 /* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 2825 2826 Field only valid when mac_addr_ad3_valid is set 2827 2828 2829 2830 The Least Significant 4 bytes of the Received Frames MAC 2831 Address AD3 2832 2833 <legal all> 2834 */ 2835 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 2836 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 2837 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 2838 2839 /* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 2840 2841 Field only valid when mac_addr_ad3_valid is set 2842 2843 2844 2845 The 2 most significant bytes of the Received Frames MAC 2846 Address AD3 2847 2848 <legal all> 2849 */ 2850 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 2851 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 2852 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 2853 2854 /* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD 2855 2856 2857 2858 2859 The sequence control field of the MPDU 2860 2861 <legal all> 2862 */ 2863 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 2864 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 2865 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 2866 2867 /* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 2868 2869 Field only valid when mac_addr_ad4_valid is set 2870 2871 2872 2873 The Least Significant 4 bytes of the Received Frames MAC 2874 Address AD4 2875 2876 <legal all> 2877 */ 2878 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 2879 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 2880 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 2881 2882 /* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 2883 2884 Field only valid when mac_addr_ad4_valid is set 2885 2886 2887 2888 The 2 most significant bytes of the Received Frames MAC 2889 Address AD4 2890 2891 <legal all> 2892 */ 2893 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 2894 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 2895 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 2896 2897 /* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD 2898 2899 Field only valid when mpdu_qos_control_valid is set 2900 2901 2902 2903 The sequence control field of the MPDU 2904 2905 <legal all> 2906 */ 2907 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 2908 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 2909 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 2910 2911 /* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD 2912 2913 Field only valid when mpdu_qos_control_valid is set 2914 2915 2916 2917 The HT control field of the MPDU 2918 2919 <legal all> 2920 */ 2921 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 2922 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 2923 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 2924 2925 2926 #endif // _RX_MPDU_INFO_H_ 2927