1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MSDU_END_H_ 25 #define _RX_MSDU_END_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 34 // 1 ip_hdr_chksum[15:0], tcp_udp_chksum[31:16] 35 // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16] 36 // 3 ext_wapi_pn_95_64[31:0] 37 // 4 ext_wapi_pn_127_96[31:0] 38 // 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], reserved_5a[31:28] 39 // 6 ipv6_options_crc[31:0] 40 // 7 tcp_seq_number[31:0] 41 // 8 tcp_ack_number[31:0] 42 // 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] 43 // 10 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_10a[15:14], l3_type[31:16] 44 // 11 rule_indication_31_0[31:0] 45 // 12 rule_indication_63_32[31:0] 46 // 13 sa_idx[15:0], da_idx[31:16] 47 // 14 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26] 48 // 15 fse_metadata[31:0] 49 // 16 cce_metadata[15:0], sa_sw_peer_id[31:16] 50 // 51 // ################ END SUMMARY ################# 52 53 #define NUM_OF_DWORDS_RX_MSDU_END 17 54 55 struct rx_msdu_end { 56 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 57 sw_frame_group_id : 7, //[8:2] 58 reserved_0 : 7, //[15:9] 59 phy_ppdu_id : 16; //[31:16] 60 uint32_t ip_hdr_chksum : 16, //[15:0] 61 tcp_udp_chksum : 16; //[31:16] 62 uint32_t key_id_octet : 8, //[7:0] 63 cce_super_rule : 6, //[13:8] 64 cce_classify_not_done_truncate : 1, //[14] 65 cce_classify_not_done_cce_dis : 1, //[15] 66 ext_wapi_pn_63_48 : 16; //[31:16] 67 uint32_t ext_wapi_pn_95_64 : 32; //[31:0] 68 uint32_t ext_wapi_pn_127_96 : 32; //[31:0] 69 uint32_t reported_mpdu_length : 14, //[13:0] 70 first_msdu : 1, //[14] 71 last_msdu : 1, //[15] 72 sa_idx_timeout : 1, //[16] 73 da_idx_timeout : 1, //[17] 74 msdu_limit_error : 1, //[18] 75 flow_idx_timeout : 1, //[19] 76 flow_idx_invalid : 1, //[20] 77 wifi_parser_error : 1, //[21] 78 amsdu_parser_error : 1, //[22] 79 sa_is_valid : 1, //[23] 80 da_is_valid : 1, //[24] 81 da_is_mcbc : 1, //[25] 82 l3_header_padding : 2, //[27:26] 83 reserved_5a : 4; //[31:28] 84 uint32_t ipv6_options_crc : 32; //[31:0] 85 uint32_t tcp_seq_number : 32; //[31:0] 86 uint32_t tcp_ack_number : 32; //[31:0] 87 uint32_t tcp_flag : 9, //[8:0] 88 lro_eligible : 1, //[9] 89 reserved_9a : 6, //[15:10] 90 window_size : 16; //[31:16] 91 uint32_t da_offset : 6, //[5:0] 92 sa_offset : 6, //[11:6] 93 da_offset_valid : 1, //[12] 94 sa_offset_valid : 1, //[13] 95 reserved_10a : 2, //[15:14] 96 l3_type : 16; //[31:16] 97 uint32_t rule_indication_31_0 : 32; //[31:0] 98 uint32_t rule_indication_63_32 : 32; //[31:0] 99 uint32_t sa_idx : 16, //[15:0] 100 da_idx : 16; //[31:16] 101 uint32_t msdu_drop : 1, //[0] 102 reo_destination_indication : 5, //[5:1] 103 flow_idx : 20, //[25:6] 104 reserved_14 : 6; //[31:26] 105 uint32_t fse_metadata : 32; //[31:0] 106 uint32_t cce_metadata : 16, //[15:0] 107 sa_sw_peer_id : 16; //[31:16] 108 }; 109 110 /* 111 112 rxpcu_mpdu_filter_in_category 113 114 Field indicates what the reason was that this MPDU frame 115 was allowed to come into the receive path by RXPCU 116 117 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 118 frame filter programming of rxpcu 119 120 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 121 regular frame filter and would have been dropped, were it 122 not for the frame fitting into the 'monitor_client' 123 category. 124 125 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 126 regular frame filter and also did not pass the 127 rxpcu_monitor_client filter. It would have been dropped 128 accept that it did pass the 'monitor_other' category. 129 130 <legal 0-2> 131 132 sw_frame_group_id 133 134 SW processes frames based on certain classifications. 135 This field indicates to what sw classification this MPDU is 136 mapped. 137 138 The classification is given in priority order 139 140 141 142 <enum 0 sw_frame_group_NDP_frame> 143 144 145 146 <enum 1 sw_frame_group_Multicast_data> 147 148 <enum 2 sw_frame_group_Unicast_data> 149 150 <enum 3 sw_frame_group_Null_data > This includes mpdus 151 of type Data Null as well as QoS Data Null 152 153 154 155 <enum 4 sw_frame_group_mgmt_0000 > 156 157 <enum 5 sw_frame_group_mgmt_0001 > 158 159 <enum 6 sw_frame_group_mgmt_0010 > 160 161 <enum 7 sw_frame_group_mgmt_0011 > 162 163 <enum 8 sw_frame_group_mgmt_0100 > 164 165 <enum 9 sw_frame_group_mgmt_0101 > 166 167 <enum 10 sw_frame_group_mgmt_0110 > 168 169 <enum 11 sw_frame_group_mgmt_0111 > 170 171 <enum 12 sw_frame_group_mgmt_1000 > 172 173 <enum 13 sw_frame_group_mgmt_1001 > 174 175 <enum 14 sw_frame_group_mgmt_1010 > 176 177 <enum 15 sw_frame_group_mgmt_1011 > 178 179 <enum 16 sw_frame_group_mgmt_1100 > 180 181 <enum 17 sw_frame_group_mgmt_1101 > 182 183 <enum 18 sw_frame_group_mgmt_1110 > 184 185 <enum 19 sw_frame_group_mgmt_1111 > 186 187 188 189 <enum 20 sw_frame_group_ctrl_0000 > 190 191 <enum 21 sw_frame_group_ctrl_0001 > 192 193 <enum 22 sw_frame_group_ctrl_0010 > 194 195 <enum 23 sw_frame_group_ctrl_0011 > 196 197 <enum 24 sw_frame_group_ctrl_0100 > 198 199 <enum 25 sw_frame_group_ctrl_0101 > 200 201 <enum 26 sw_frame_group_ctrl_0110 > 202 203 <enum 27 sw_frame_group_ctrl_0111 > 204 205 <enum 28 sw_frame_group_ctrl_1000 > 206 207 <enum 29 sw_frame_group_ctrl_1001 > 208 209 <enum 30 sw_frame_group_ctrl_1010 > 210 211 <enum 31 sw_frame_group_ctrl_1011 > 212 213 <enum 32 sw_frame_group_ctrl_1100 > 214 215 <enum 33 sw_frame_group_ctrl_1101 > 216 217 <enum 34 sw_frame_group_ctrl_1110 > 218 219 <enum 35 sw_frame_group_ctrl_1111 > 220 221 222 223 <enum 36 sw_frame_group_unsupported> This covers type 3 224 and protocol version != 0 225 226 227 228 229 230 231 <legal 0-37> 232 233 reserved_0 234 235 <legal 0> 236 237 phy_ppdu_id 238 239 A ppdu counter value that PHY increments for every PPDU 240 received. The counter value wraps around 241 242 <legal all> 243 244 ip_hdr_chksum 245 246 This can include the IP header checksum or the pseudo 247 header checksum used by TCP/UDP checksum. 248 249 tcp_udp_chksum 250 251 The value of the computed TCP/UDP checksum. A mode bit 252 selects whether this checksum is the full checksum or the 253 partial checksum which does not include the pseudo header. 254 255 key_id_octet 256 257 The key ID octet from the IV. Only valid when 258 first_msdu is set. 259 260 cce_super_rule 261 262 Indicates the super filter rule 263 264 cce_classify_not_done_truncate 265 266 Classification failed due to truncated frame 267 268 cce_classify_not_done_cce_dis 269 270 Classification failed due to CCE global disable 271 272 ext_wapi_pn_63_48 273 274 Extension PN (packet number) which is only used by WAPI. 275 This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 276 The WAPI PN bits [63:0] are in the pn field of the 277 rx_mpdu_start descriptor. 278 279 ext_wapi_pn_95_64 280 281 Extension PN (packet number) which is only used by WAPI. 282 This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 283 and pn11). 284 285 ext_wapi_pn_127_96 286 287 Extension PN (packet number) which is only used by WAPI. 288 This corresponds to WAPI PN bits [127:96] (pn12, pn13, 289 pn14, pn15). 290 291 reported_mpdu_length 292 293 MPDU length before decapsulation. Only valid when 294 first_msdu is set. This field is taken directly from the 295 length field of the A-MPDU delimiter or the preamble length 296 field for non-A-MPDU frames. 297 298 first_msdu 299 300 Indicates the first MSDU of A-MSDU. If both first_msdu 301 and last_msdu are set in the MSDU then this is a 302 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 303 A-MSDU shall have both first_mpdu and last_mpdu bits set to 304 0. 305 306 last_msdu 307 308 Indicates the last MSDU of the A-MSDU. MPDU end status 309 is only valid when last_msdu is set. 310 311 sa_idx_timeout 312 313 Indicates an unsuccessful MAC source address search due 314 to the expiring of the search timer. 315 316 da_idx_timeout 317 318 Indicates an unsuccessful MAC destination address search 319 due to the expiring of the search timer. 320 321 msdu_limit_error 322 323 Indicates that the MSDU threshold was exceeded and thus 324 all the rest of the MSDUs will not be scattered and will not 325 be decapsulated but will be DMA'ed in RAW format as a single 326 MSDU buffer 327 328 flow_idx_timeout 329 330 Indicates an unsuccessful flow search due to the 331 expiring of the search timer. 332 333 <legal all> 334 335 flow_idx_invalid 336 337 flow id is not valid 338 339 <legal all> 340 341 wifi_parser_error 342 343 Indicates that the WiFi frame has one of the following 344 errors 345 346 o has less than minimum allowed bytes as per standard 347 348 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 349 350 <legal all> 351 352 amsdu_parser_error 353 354 A-MSDU could not be properly de-agregated. 355 356 <legal all> 357 358 sa_is_valid 359 360 Indicates that OLE found a valid SA entry 361 362 da_is_valid 363 364 Indicates that OLE found a valid DA entry 365 366 da_is_mcbc 367 368 Field Only valid if da_is_valid is set 369 370 371 372 Indicates the DA address was a Multicast of Broadcast 373 address. 374 375 l3_header_padding 376 377 Number of bytes padded to make sure that the L3 header 378 will always start of a Dword boundary 379 380 reserved_5a 381 382 <legal 0> 383 384 ipv6_options_crc 385 386 32 bit CRC computed out of IP v6 extension headers 387 388 tcp_seq_number 389 390 TCP sequence number 391 392 tcp_ack_number 393 394 TCP acknowledge number 395 396 tcp_flag 397 398 TCP flags 399 400 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 401 402 lro_eligible 403 404 Computed out of TCP and IP fields to indicate that this 405 MSDU is eligible for LRO 406 407 reserved_9a 408 409 NOTE: DO not assign a field... Internally used in 410 RXOLE.. 411 412 <legal 0> 413 414 window_size 415 416 TCP receive window size 417 418 da_offset 419 420 Offset into MSDU buffer for DA 421 422 sa_offset 423 424 Offset into MSDU buffer for SA 425 426 da_offset_valid 427 428 da_offset field is valid. This will be set to 0 in case 429 of a dynamic A-MSDU when DA is compressed 430 431 sa_offset_valid 432 433 sa_offset field is valid. This will be set to 0 in case 434 of a dynamic A-MSDU when SA is compressed 435 436 reserved_10a 437 438 <legal 0> 439 440 l3_type 441 442 The 16-bit type value indicating the type of L3 later 443 extracted from LLC/SNAP, set to zero if SNAP is not 444 available 445 446 rule_indication_31_0 447 448 Bitmap indicating which of rules 31-0 have matched 449 450 rule_indication_63_32 451 452 Bitmap indicating which of rules 63-32 have matched 453 454 sa_idx 455 456 The offset in the address table which matches the MAC 457 source address. 458 459 da_idx 460 461 The offset in the address table which matches the MAC 462 source address 463 464 msdu_drop 465 466 When set, REO shall drop this MSDU and not forward it to 467 any other ring... 468 469 <legal all> 470 471 reo_destination_indication 472 473 The ID of the REO exit ring where the MSDU frame shall 474 push after (MPDU level) reordering has finished. 475 476 477 478 <enum 0 reo_destination_tcl> Reo will push the frame 479 into the REO2TCL ring 480 481 <enum 1 reo_destination_sw1> Reo will push the frame 482 into the REO2SW1 ring 483 484 <enum 2 reo_destination_sw2> Reo will push the frame 485 into the REO2SW1 ring 486 487 <enum 3 reo_destination_sw3> Reo will push the frame 488 into the REO2SW1 ring 489 490 <enum 4 reo_destination_sw4> Reo will push the frame 491 into the REO2SW1 ring 492 493 <enum 5 reo_destination_release> Reo will push the frame 494 into the REO_release ring 495 496 <enum 6 reo_destination_fw> Reo will push the frame into 497 the REO2FW ring 498 499 <enum 7 reo_destination_7> REO remaps this 500 501 <enum 8 reo_destination_8> REO remaps this <enum 9 502 reo_destination_9> REO remaps this <enum 10 503 reo_destination_10> REO remaps this 504 505 <enum 11 reo_destination_11> REO remaps this 506 507 <enum 12 reo_destination_12> REO remaps this <enum 13 508 reo_destination_13> REO remaps this 509 510 <enum 14 reo_destination_14> REO remaps this 511 512 <enum 15 reo_destination_15> REO remaps this 513 514 <enum 16 reo_destination_16> REO remaps this 515 516 <enum 17 reo_destination_17> REO remaps this 517 518 <enum 18 reo_destination_18> REO remaps this 519 520 <enum 19 reo_destination_19> REO remaps this 521 522 <enum 20 reo_destination_20> REO remaps this 523 524 <enum 21 reo_destination_21> REO remaps this 525 526 <enum 22 reo_destination_22> REO remaps this 527 528 <enum 23 reo_destination_23> REO remaps this 529 530 <enum 24 reo_destination_24> REO remaps this 531 532 <enum 25 reo_destination_25> REO remaps this 533 534 <enum 26 reo_destination_26> REO remaps this 535 536 <enum 27 reo_destination_27> REO remaps this 537 538 <enum 28 reo_destination_28> REO remaps this 539 540 <enum 29 reo_destination_29> REO remaps this 541 542 <enum 30 reo_destination_30> REO remaps this 543 544 <enum 31 reo_destination_31> REO remaps this 545 546 547 548 <legal all> 549 550 flow_idx 551 552 Flow table index 553 554 <legal all> 555 556 reserved_14 557 558 <legal 0> 559 560 fse_metadata 561 562 FSE related meta data: 563 564 <legal all> 565 566 cce_metadata 567 568 CCE related meta data: 569 570 <legal all> 571 572 sa_sw_peer_id 573 574 sw_peer_id from the address search entry corresponding 575 to the source address of the MSDU 576 577 <legal 0> 578 */ 579 580 581 /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 582 583 Field indicates what the reason was that this MPDU frame 584 was allowed to come into the receive path by RXPCU 585 586 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 587 frame filter programming of rxpcu 588 589 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 590 regular frame filter and would have been dropped, were it 591 not for the frame fitting into the 'monitor_client' 592 category. 593 594 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 595 regular frame filter and also did not pass the 596 rxpcu_monitor_client filter. It would have been dropped 597 accept that it did pass the 'monitor_other' category. 598 599 <legal 0-2> 600 */ 601 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 602 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 603 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 604 605 /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID 606 607 SW processes frames based on certain classifications. 608 This field indicates to what sw classification this MPDU is 609 mapped. 610 611 The classification is given in priority order 612 613 614 615 <enum 0 sw_frame_group_NDP_frame> 616 617 618 619 <enum 1 sw_frame_group_Multicast_data> 620 621 <enum 2 sw_frame_group_Unicast_data> 622 623 <enum 3 sw_frame_group_Null_data > This includes mpdus 624 of type Data Null as well as QoS Data Null 625 626 627 628 <enum 4 sw_frame_group_mgmt_0000 > 629 630 <enum 5 sw_frame_group_mgmt_0001 > 631 632 <enum 6 sw_frame_group_mgmt_0010 > 633 634 <enum 7 sw_frame_group_mgmt_0011 > 635 636 <enum 8 sw_frame_group_mgmt_0100 > 637 638 <enum 9 sw_frame_group_mgmt_0101 > 639 640 <enum 10 sw_frame_group_mgmt_0110 > 641 642 <enum 11 sw_frame_group_mgmt_0111 > 643 644 <enum 12 sw_frame_group_mgmt_1000 > 645 646 <enum 13 sw_frame_group_mgmt_1001 > 647 648 <enum 14 sw_frame_group_mgmt_1010 > 649 650 <enum 15 sw_frame_group_mgmt_1011 > 651 652 <enum 16 sw_frame_group_mgmt_1100 > 653 654 <enum 17 sw_frame_group_mgmt_1101 > 655 656 <enum 18 sw_frame_group_mgmt_1110 > 657 658 <enum 19 sw_frame_group_mgmt_1111 > 659 660 661 662 <enum 20 sw_frame_group_ctrl_0000 > 663 664 <enum 21 sw_frame_group_ctrl_0001 > 665 666 <enum 22 sw_frame_group_ctrl_0010 > 667 668 <enum 23 sw_frame_group_ctrl_0011 > 669 670 <enum 24 sw_frame_group_ctrl_0100 > 671 672 <enum 25 sw_frame_group_ctrl_0101 > 673 674 <enum 26 sw_frame_group_ctrl_0110 > 675 676 <enum 27 sw_frame_group_ctrl_0111 > 677 678 <enum 28 sw_frame_group_ctrl_1000 > 679 680 <enum 29 sw_frame_group_ctrl_1001 > 681 682 <enum 30 sw_frame_group_ctrl_1010 > 683 684 <enum 31 sw_frame_group_ctrl_1011 > 685 686 <enum 32 sw_frame_group_ctrl_1100 > 687 688 <enum 33 sw_frame_group_ctrl_1101 > 689 690 <enum 34 sw_frame_group_ctrl_1110 > 691 692 <enum 35 sw_frame_group_ctrl_1111 > 693 694 695 696 <enum 36 sw_frame_group_unsupported> This covers type 3 697 and protocol version != 0 698 699 700 701 702 703 704 <legal 0-37> 705 */ 706 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 707 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 708 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 709 710 /* Description RX_MSDU_END_0_RESERVED_0 711 712 <legal 0> 713 */ 714 #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 715 #define RX_MSDU_END_0_RESERVED_0_LSB 9 716 #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 717 718 /* Description RX_MSDU_END_0_PHY_PPDU_ID 719 720 A ppdu counter value that PHY increments for every PPDU 721 received. The counter value wraps around 722 723 <legal all> 724 */ 725 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 726 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 727 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 728 729 /* Description RX_MSDU_END_1_IP_HDR_CHKSUM 730 731 This can include the IP header checksum or the pseudo 732 header checksum used by TCP/UDP checksum. 733 */ 734 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 735 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 736 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff 737 738 /* Description RX_MSDU_END_1_TCP_UDP_CHKSUM 739 740 The value of the computed TCP/UDP checksum. A mode bit 741 selects whether this checksum is the full checksum or the 742 partial checksum which does not include the pseudo header. 743 */ 744 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET 0x00000004 745 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB 16 746 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK 0xffff0000 747 748 /* Description RX_MSDU_END_2_KEY_ID_OCTET 749 750 The key ID octet from the IV. Only valid when 751 first_msdu is set. 752 */ 753 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 754 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 755 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff 756 757 /* Description RX_MSDU_END_2_CCE_SUPER_RULE 758 759 Indicates the super filter rule 760 */ 761 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 762 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 763 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 764 765 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE 766 767 Classification failed due to truncated frame 768 */ 769 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 770 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 771 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 772 773 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS 774 775 Classification failed due to CCE global disable 776 */ 777 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 778 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 779 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 780 781 /* Description RX_MSDU_END_2_EXT_WAPI_PN_63_48 782 783 Extension PN (packet number) which is only used by WAPI. 784 This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 785 The WAPI PN bits [63:0] are in the pn field of the 786 rx_mpdu_start descriptor. 787 */ 788 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET 0x00000008 789 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB 16 790 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK 0xffff0000 791 792 /* Description RX_MSDU_END_3_EXT_WAPI_PN_95_64 793 794 Extension PN (packet number) which is only used by WAPI. 795 This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 796 and pn11). 797 */ 798 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET 0x0000000c 799 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB 0 800 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK 0xffffffff 801 802 /* Description RX_MSDU_END_4_EXT_WAPI_PN_127_96 803 804 Extension PN (packet number) which is only used by WAPI. 805 This corresponds to WAPI PN bits [127:96] (pn12, pn13, 806 pn14, pn15). 807 */ 808 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET 0x00000010 809 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB 0 810 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK 0xffffffff 811 812 /* Description RX_MSDU_END_5_REPORTED_MPDU_LENGTH 813 814 MPDU length before decapsulation. Only valid when 815 first_msdu is set. This field is taken directly from the 816 length field of the A-MPDU delimiter or the preamble length 817 field for non-A-MPDU frames. 818 */ 819 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_OFFSET 0x00000014 820 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_LSB 0 821 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK 0x00003fff 822 823 /* Description RX_MSDU_END_5_FIRST_MSDU 824 825 Indicates the first MSDU of A-MSDU. If both first_msdu 826 and last_msdu are set in the MSDU then this is a 827 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 828 A-MSDU shall have both first_mpdu and last_mpdu bits set to 829 0. 830 */ 831 #define RX_MSDU_END_5_FIRST_MSDU_OFFSET 0x00000014 832 #define RX_MSDU_END_5_FIRST_MSDU_LSB 14 833 #define RX_MSDU_END_5_FIRST_MSDU_MASK 0x00004000 834 835 /* Description RX_MSDU_END_5_LAST_MSDU 836 837 Indicates the last MSDU of the A-MSDU. MPDU end status 838 is only valid when last_msdu is set. 839 */ 840 #define RX_MSDU_END_5_LAST_MSDU_OFFSET 0x00000014 841 #define RX_MSDU_END_5_LAST_MSDU_LSB 15 842 #define RX_MSDU_END_5_LAST_MSDU_MASK 0x00008000 843 844 /* Description RX_MSDU_END_5_SA_IDX_TIMEOUT 845 846 Indicates an unsuccessful MAC source address search due 847 to the expiring of the search timer. 848 */ 849 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_OFFSET 0x00000014 850 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_LSB 16 851 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK 0x00010000 852 853 /* Description RX_MSDU_END_5_DA_IDX_TIMEOUT 854 855 Indicates an unsuccessful MAC destination address search 856 due to the expiring of the search timer. 857 */ 858 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_OFFSET 0x00000014 859 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_LSB 17 860 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK 0x00020000 861 862 /* Description RX_MSDU_END_5_MSDU_LIMIT_ERROR 863 864 Indicates that the MSDU threshold was exceeded and thus 865 all the rest of the MSDUs will not be scattered and will not 866 be decapsulated but will be DMA'ed in RAW format as a single 867 MSDU buffer 868 */ 869 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_OFFSET 0x00000014 870 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_LSB 18 871 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK 0x00040000 872 873 /* Description RX_MSDU_END_5_FLOW_IDX_TIMEOUT 874 875 Indicates an unsuccessful flow search due to the 876 expiring of the search timer. 877 878 <legal all> 879 */ 880 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET 0x00000014 881 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB 19 882 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK 0x00080000 883 884 /* Description RX_MSDU_END_5_FLOW_IDX_INVALID 885 886 flow id is not valid 887 888 <legal all> 889 */ 890 #define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET 0x00000014 891 #define RX_MSDU_END_5_FLOW_IDX_INVALID_LSB 20 892 #define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK 0x00100000 893 894 /* Description RX_MSDU_END_5_WIFI_PARSER_ERROR 895 896 Indicates that the WiFi frame has one of the following 897 errors 898 899 o has less than minimum allowed bytes as per standard 900 901 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 902 903 <legal all> 904 */ 905 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET 0x00000014 906 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_LSB 21 907 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK 0x00200000 908 909 /* Description RX_MSDU_END_5_AMSDU_PARSER_ERROR 910 911 A-MSDU could not be properly de-agregated. 912 913 <legal all> 914 */ 915 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET 0x00000014 916 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_LSB 22 917 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK 0x00400000 918 919 /* Description RX_MSDU_END_5_SA_IS_VALID 920 921 Indicates that OLE found a valid SA entry 922 */ 923 #define RX_MSDU_END_5_SA_IS_VALID_OFFSET 0x00000014 924 #define RX_MSDU_END_5_SA_IS_VALID_LSB 23 925 #define RX_MSDU_END_5_SA_IS_VALID_MASK 0x00800000 926 927 /* Description RX_MSDU_END_5_DA_IS_VALID 928 929 Indicates that OLE found a valid DA entry 930 */ 931 #define RX_MSDU_END_5_DA_IS_VALID_OFFSET 0x00000014 932 #define RX_MSDU_END_5_DA_IS_VALID_LSB 24 933 #define RX_MSDU_END_5_DA_IS_VALID_MASK 0x01000000 934 935 /* Description RX_MSDU_END_5_DA_IS_MCBC 936 937 Field Only valid if da_is_valid is set 938 939 940 941 Indicates the DA address was a Multicast of Broadcast 942 address. 943 */ 944 #define RX_MSDU_END_5_DA_IS_MCBC_OFFSET 0x00000014 945 #define RX_MSDU_END_5_DA_IS_MCBC_LSB 25 946 #define RX_MSDU_END_5_DA_IS_MCBC_MASK 0x02000000 947 948 /* Description RX_MSDU_END_5_L3_HEADER_PADDING 949 950 Number of bytes padded to make sure that the L3 header 951 will always start of a Dword boundary 952 */ 953 #define RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET 0x00000014 954 #define RX_MSDU_END_5_L3_HEADER_PADDING_LSB 26 955 #define RX_MSDU_END_5_L3_HEADER_PADDING_MASK 0x0c000000 956 957 /* Description RX_MSDU_END_5_RESERVED_5A 958 959 <legal 0> 960 */ 961 #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 962 #define RX_MSDU_END_5_RESERVED_5A_LSB 28 963 #define RX_MSDU_END_5_RESERVED_5A_MASK 0xf0000000 964 965 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC 966 967 32 bit CRC computed out of IP v6 extension headers 968 */ 969 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 970 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 971 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff 972 973 /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER 974 975 TCP sequence number 976 */ 977 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c 978 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 979 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff 980 981 /* Description RX_MSDU_END_8_TCP_ACK_NUMBER 982 983 TCP acknowledge number 984 */ 985 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 986 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 987 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff 988 989 /* Description RX_MSDU_END_9_TCP_FLAG 990 991 TCP flags 992 993 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 994 */ 995 #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 996 #define RX_MSDU_END_9_TCP_FLAG_LSB 0 997 #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff 998 999 /* Description RX_MSDU_END_9_LRO_ELIGIBLE 1000 1001 Computed out of TCP and IP fields to indicate that this 1002 MSDU is eligible for LRO 1003 */ 1004 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 1005 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 1006 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 1007 1008 /* Description RX_MSDU_END_9_RESERVED_9A 1009 1010 NOTE: DO not assign a field... Internally used in 1011 RXOLE.. 1012 1013 <legal 0> 1014 */ 1015 #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 1016 #define RX_MSDU_END_9_RESERVED_9A_LSB 10 1017 #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 1018 1019 /* Description RX_MSDU_END_9_WINDOW_SIZE 1020 1021 TCP receive window size 1022 */ 1023 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 1024 #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 1025 #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 1026 1027 /* Description RX_MSDU_END_10_DA_OFFSET 1028 1029 Offset into MSDU buffer for DA 1030 */ 1031 #define RX_MSDU_END_10_DA_OFFSET_OFFSET 0x00000028 1032 #define RX_MSDU_END_10_DA_OFFSET_LSB 0 1033 #define RX_MSDU_END_10_DA_OFFSET_MASK 0x0000003f 1034 1035 /* Description RX_MSDU_END_10_SA_OFFSET 1036 1037 Offset into MSDU buffer for SA 1038 */ 1039 #define RX_MSDU_END_10_SA_OFFSET_OFFSET 0x00000028 1040 #define RX_MSDU_END_10_SA_OFFSET_LSB 6 1041 #define RX_MSDU_END_10_SA_OFFSET_MASK 0x00000fc0 1042 1043 /* Description RX_MSDU_END_10_DA_OFFSET_VALID 1044 1045 da_offset field is valid. This will be set to 0 in case 1046 of a dynamic A-MSDU when DA is compressed 1047 */ 1048 #define RX_MSDU_END_10_DA_OFFSET_VALID_OFFSET 0x00000028 1049 #define RX_MSDU_END_10_DA_OFFSET_VALID_LSB 12 1050 #define RX_MSDU_END_10_DA_OFFSET_VALID_MASK 0x00001000 1051 1052 /* Description RX_MSDU_END_10_SA_OFFSET_VALID 1053 1054 sa_offset field is valid. This will be set to 0 in case 1055 of a dynamic A-MSDU when SA is compressed 1056 */ 1057 #define RX_MSDU_END_10_SA_OFFSET_VALID_OFFSET 0x00000028 1058 #define RX_MSDU_END_10_SA_OFFSET_VALID_LSB 13 1059 #define RX_MSDU_END_10_SA_OFFSET_VALID_MASK 0x00002000 1060 1061 /* Description RX_MSDU_END_10_RESERVED_10A 1062 1063 <legal 0> 1064 */ 1065 #define RX_MSDU_END_10_RESERVED_10A_OFFSET 0x00000028 1066 #define RX_MSDU_END_10_RESERVED_10A_LSB 14 1067 #define RX_MSDU_END_10_RESERVED_10A_MASK 0x0000c000 1068 1069 /* Description RX_MSDU_END_10_L3_TYPE 1070 1071 The 16-bit type value indicating the type of L3 later 1072 extracted from LLC/SNAP, set to zero if SNAP is not 1073 available 1074 */ 1075 #define RX_MSDU_END_10_L3_TYPE_OFFSET 0x00000028 1076 #define RX_MSDU_END_10_L3_TYPE_LSB 16 1077 #define RX_MSDU_END_10_L3_TYPE_MASK 0xffff0000 1078 1079 /* Description RX_MSDU_END_11_RULE_INDICATION_31_0 1080 1081 Bitmap indicating which of rules 31-0 have matched 1082 */ 1083 #define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET 0x0000002c 1084 #define RX_MSDU_END_11_RULE_INDICATION_31_0_LSB 0 1085 #define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK 0xffffffff 1086 1087 /* Description RX_MSDU_END_12_RULE_INDICATION_63_32 1088 1089 Bitmap indicating which of rules 63-32 have matched 1090 */ 1091 #define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET 0x00000030 1092 #define RX_MSDU_END_12_RULE_INDICATION_63_32_LSB 0 1093 #define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK 0xffffffff 1094 1095 /* Description RX_MSDU_END_13_SA_IDX 1096 1097 The offset in the address table which matches the MAC 1098 source address. 1099 */ 1100 #define RX_MSDU_END_13_SA_IDX_OFFSET 0x00000034 1101 #define RX_MSDU_END_13_SA_IDX_LSB 0 1102 #define RX_MSDU_END_13_SA_IDX_MASK 0x0000ffff 1103 1104 /* Description RX_MSDU_END_13_DA_IDX 1105 1106 The offset in the address table which matches the MAC 1107 source address 1108 */ 1109 #define RX_MSDU_END_13_DA_IDX_OFFSET 0x00000034 1110 #define RX_MSDU_END_13_DA_IDX_LSB 16 1111 #define RX_MSDU_END_13_DA_IDX_MASK 0xffff0000 1112 1113 /* Description RX_MSDU_END_14_MSDU_DROP 1114 1115 When set, REO shall drop this MSDU and not forward it to 1116 any other ring... 1117 1118 <legal all> 1119 */ 1120 #define RX_MSDU_END_14_MSDU_DROP_OFFSET 0x00000038 1121 #define RX_MSDU_END_14_MSDU_DROP_LSB 0 1122 #define RX_MSDU_END_14_MSDU_DROP_MASK 0x00000001 1123 1124 /* Description RX_MSDU_END_14_REO_DESTINATION_INDICATION 1125 1126 The ID of the REO exit ring where the MSDU frame shall 1127 push after (MPDU level) reordering has finished. 1128 1129 1130 1131 <enum 0 reo_destination_tcl> Reo will push the frame 1132 into the REO2TCL ring 1133 1134 <enum 1 reo_destination_sw1> Reo will push the frame 1135 into the REO2SW1 ring 1136 1137 <enum 2 reo_destination_sw2> Reo will push the frame 1138 into the REO2SW1 ring 1139 1140 <enum 3 reo_destination_sw3> Reo will push the frame 1141 into the REO2SW1 ring 1142 1143 <enum 4 reo_destination_sw4> Reo will push the frame 1144 into the REO2SW1 ring 1145 1146 <enum 5 reo_destination_release> Reo will push the frame 1147 into the REO_release ring 1148 1149 <enum 6 reo_destination_fw> Reo will push the frame into 1150 the REO2FW ring 1151 1152 <enum 7 reo_destination_7> REO remaps this 1153 1154 <enum 8 reo_destination_8> REO remaps this <enum 9 1155 reo_destination_9> REO remaps this <enum 10 1156 reo_destination_10> REO remaps this 1157 1158 <enum 11 reo_destination_11> REO remaps this 1159 1160 <enum 12 reo_destination_12> REO remaps this <enum 13 1161 reo_destination_13> REO remaps this 1162 1163 <enum 14 reo_destination_14> REO remaps this 1164 1165 <enum 15 reo_destination_15> REO remaps this 1166 1167 <enum 16 reo_destination_16> REO remaps this 1168 1169 <enum 17 reo_destination_17> REO remaps this 1170 1171 <enum 18 reo_destination_18> REO remaps this 1172 1173 <enum 19 reo_destination_19> REO remaps this 1174 1175 <enum 20 reo_destination_20> REO remaps this 1176 1177 <enum 21 reo_destination_21> REO remaps this 1178 1179 <enum 22 reo_destination_22> REO remaps this 1180 1181 <enum 23 reo_destination_23> REO remaps this 1182 1183 <enum 24 reo_destination_24> REO remaps this 1184 1185 <enum 25 reo_destination_25> REO remaps this 1186 1187 <enum 26 reo_destination_26> REO remaps this 1188 1189 <enum 27 reo_destination_27> REO remaps this 1190 1191 <enum 28 reo_destination_28> REO remaps this 1192 1193 <enum 29 reo_destination_29> REO remaps this 1194 1195 <enum 30 reo_destination_30> REO remaps this 1196 1197 <enum 31 reo_destination_31> REO remaps this 1198 1199 1200 1201 <legal all> 1202 */ 1203 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET 0x00000038 1204 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_LSB 1 1205 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK 0x0000003e 1206 1207 /* Description RX_MSDU_END_14_FLOW_IDX 1208 1209 Flow table index 1210 1211 <legal all> 1212 */ 1213 #define RX_MSDU_END_14_FLOW_IDX_OFFSET 0x00000038 1214 #define RX_MSDU_END_14_FLOW_IDX_LSB 6 1215 #define RX_MSDU_END_14_FLOW_IDX_MASK 0x03ffffc0 1216 1217 /* Description RX_MSDU_END_14_RESERVED_14 1218 1219 <legal 0> 1220 */ 1221 #define RX_MSDU_END_14_RESERVED_14_OFFSET 0x00000038 1222 #define RX_MSDU_END_14_RESERVED_14_LSB 26 1223 #define RX_MSDU_END_14_RESERVED_14_MASK 0xfc000000 1224 1225 /* Description RX_MSDU_END_15_FSE_METADATA 1226 1227 FSE related meta data: 1228 1229 <legal all> 1230 */ 1231 #define RX_MSDU_END_15_FSE_METADATA_OFFSET 0x0000003c 1232 #define RX_MSDU_END_15_FSE_METADATA_LSB 0 1233 #define RX_MSDU_END_15_FSE_METADATA_MASK 0xffffffff 1234 1235 /* Description RX_MSDU_END_16_CCE_METADATA 1236 1237 CCE related meta data: 1238 1239 <legal all> 1240 */ 1241 #define RX_MSDU_END_16_CCE_METADATA_OFFSET 0x00000040 1242 #define RX_MSDU_END_16_CCE_METADATA_LSB 0 1243 #define RX_MSDU_END_16_CCE_METADATA_MASK 0x0000ffff 1244 1245 /* Description RX_MSDU_END_16_SA_SW_PEER_ID 1246 1247 sw_peer_id from the address search entry corresponding 1248 to the source address of the MSDU 1249 1250 <legal 0> 1251 */ 1252 #define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET 0x00000040 1253 #define RX_MSDU_END_16_SA_SW_PEER_ID_LSB 16 1254 #define RX_MSDU_END_16_SA_SW_PEER_ID_MASK 0xffff0000 1255 1256 1257 #endif // _RX_MSDU_END_H_ 1258