1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _TCL_GSE_CMD_H_ 25 #define _TCL_GSE_CMD_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 control_buffer_addr_31_0[31:0] 34 // 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], reserved_1a[31:15] 35 // 2 cmd_meta_data_31_0[31:0] 36 // 3 cmd_meta_data_63_32[31:0] 37 // 4 reserved_4a[31:0] 38 // 5 reserved_5a[31:0] 39 // 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] 40 // 41 // ################ END SUMMARY ################# 42 43 #define NUM_OF_DWORDS_TCL_GSE_CMD 7 44 45 struct tcl_gse_cmd { 46 uint32_t control_buffer_addr_31_0 : 32; //[31:0] 47 uint32_t control_buffer_addr_39_32 : 8, //[7:0] 48 gse_ctrl : 4, //[11:8] 49 gse_sel : 1, //[12] 50 status_destination_ring_id : 1, //[13] 51 swap : 1, //[14] 52 reserved_1a : 17; //[31:15] 53 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 54 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 55 uint32_t reserved_4a : 32; //[31:0] 56 uint32_t reserved_5a : 32; //[31:0] 57 uint32_t reserved_6a : 20, //[19:0] 58 ring_id : 8, //[27:20] 59 looping_count : 4; //[31:28] 60 }; 61 62 /* 63 64 control_buffer_addr_31_0 65 66 Address (lower 32 bits) of a control buffer containing 67 additional info needed for this command execution. 68 69 <legal all> 70 71 control_buffer_addr_39_32 72 73 Address (upper 8 bits) of a control buffer containing 74 additional info needed for this command execution. 75 76 <legal all> 77 78 gse_ctrl 79 80 GSE control operations. This includes cache operations 81 and table entry statistics read/clear operation. 82 83 <enum 0 rd_stat> Report or Read statistics 84 85 <enum 1 srch_dis> Search disable. Report only Hash 86 87 <enum 2 Wr_bk_single> Write Back single entry 88 89 <enum 3 wr_bk_all> Write Back entire cache entry 90 91 <enum 4 inval_single> Invalidate single cache entry 92 93 <enum 5 inval_all> Invalidate entire cache 94 95 <enum 6 wr_bk_inval_single> Write back and Invalidate 96 single entry in cache 97 98 <enum 7 wr_bk_inval_all> write back and invalidate 99 entire cache 100 101 <enum 8 clr_stat_single> Clear statistics for single 102 entry 103 104 <legal 0-8> 105 106 Rest of the values reserved. 107 108 For all single entry control operations (write back, 109 Invalidate or both)Statistics will be reported 110 111 gse_sel 112 113 Bit to select the ASE or FSE to do the operation mention 114 by GSE_ctrl bit 115 116 0: FSE select 117 118 1: ASE select 119 120 status_destination_ring_id 121 122 The TCL status ring to which the GSE status needs to be 123 send. 124 125 126 127 <enum 0 tcl_status_0_ring> 128 129 <enum 1 tcl_status_1_ring> 130 131 132 133 <legal all> 134 135 swap 136 137 Bit to enable byte swapping of contents of buffer 138 139 <enum 0 Byte_swap_disable > 140 141 <enum 1 byte_swap_enable > 142 143 <legal all> 144 145 reserved_1a 146 147 <legal 0> 148 149 cmd_meta_data_31_0 150 151 Meta data to be returned in the status descriptor 152 153 <legal all> 154 155 cmd_meta_data_63_32 156 157 Meta data to be returned in the status descriptor 158 159 <legal all> 160 161 reserved_4a 162 163 <legal 0> 164 165 reserved_5a 166 167 <legal 0> 168 169 reserved_6a 170 171 <legal 0> 172 173 ring_id 174 175 Helps with debugging when dumping ring contents. 176 177 <legal all> 178 179 looping_count 180 181 A count value that indicates the number of times the 182 producer of entries into the Ring has looped around the 183 ring. 184 185 At initialization time, this value is set to 0. On the 186 first loop, this value is set to 1. After the max value is 187 reached allowed by the number of bits for this field, the 188 count value continues with 0 again. 189 190 191 192 In case SW is the consumer of the ring entries, it can 193 use this field to figure out up to where the producer of 194 entries has created new entries. This eliminates the need to 195 check where the head pointer' of the ring is located once 196 the SW starts processing an interrupt indicating that new 197 entries have been put into this ring... 198 199 200 201 Also note that SW if it wants only needs to look at the 202 LSB bit of this count value. 203 204 <legal all> 205 */ 206 207 208 /* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 209 210 Address (lower 32 bits) of a control buffer containing 211 additional info needed for this command execution. 212 213 <legal all> 214 */ 215 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 216 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 217 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 218 219 /* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 220 221 Address (upper 8 bits) of a control buffer containing 222 additional info needed for this command execution. 223 224 <legal all> 225 */ 226 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 227 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 228 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 229 230 /* Description TCL_GSE_CMD_1_GSE_CTRL 231 232 GSE control operations. This includes cache operations 233 and table entry statistics read/clear operation. 234 235 <enum 0 rd_stat> Report or Read statistics 236 237 <enum 1 srch_dis> Search disable. Report only Hash 238 239 <enum 2 Wr_bk_single> Write Back single entry 240 241 <enum 3 wr_bk_all> Write Back entire cache entry 242 243 <enum 4 inval_single> Invalidate single cache entry 244 245 <enum 5 inval_all> Invalidate entire cache 246 247 <enum 6 wr_bk_inval_single> Write back and Invalidate 248 single entry in cache 249 250 <enum 7 wr_bk_inval_all> write back and invalidate 251 entire cache 252 253 <enum 8 clr_stat_single> Clear statistics for single 254 entry 255 256 <legal 0-8> 257 258 Rest of the values reserved. 259 260 For all single entry control operations (write back, 261 Invalidate or both)Statistics will be reported 262 */ 263 #define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 264 #define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 265 #define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 266 267 /* Description TCL_GSE_CMD_1_GSE_SEL 268 269 Bit to select the ASE or FSE to do the operation mention 270 by GSE_ctrl bit 271 272 0: FSE select 273 274 1: ASE select 275 */ 276 #define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 277 #define TCL_GSE_CMD_1_GSE_SEL_LSB 12 278 #define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 279 280 /* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID 281 282 The TCL status ring to which the GSE status needs to be 283 send. 284 285 286 287 <enum 0 tcl_status_0_ring> 288 289 <enum 1 tcl_status_1_ring> 290 291 292 293 <legal all> 294 */ 295 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 296 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 297 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 298 299 /* Description TCL_GSE_CMD_1_SWAP 300 301 Bit to enable byte swapping of contents of buffer 302 303 <enum 0 Byte_swap_disable > 304 305 <enum 1 byte_swap_enable > 306 307 <legal all> 308 */ 309 #define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 310 #define TCL_GSE_CMD_1_SWAP_LSB 14 311 #define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 312 313 /* Description TCL_GSE_CMD_1_RESERVED_1A 314 315 <legal 0> 316 */ 317 #define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 318 #define TCL_GSE_CMD_1_RESERVED_1A_LSB 15 319 #define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xffff8000 320 321 /* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 322 323 Meta data to be returned in the status descriptor 324 325 <legal all> 326 */ 327 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 328 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 329 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff 330 331 /* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 332 333 Meta data to be returned in the status descriptor 334 335 <legal all> 336 */ 337 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c 338 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 339 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff 340 341 /* Description TCL_GSE_CMD_4_RESERVED_4A 342 343 <legal 0> 344 */ 345 #define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 346 #define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 347 #define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff 348 349 /* Description TCL_GSE_CMD_5_RESERVED_5A 350 351 <legal 0> 352 */ 353 #define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 354 #define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 355 #define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff 356 357 /* Description TCL_GSE_CMD_6_RESERVED_6A 358 359 <legal 0> 360 */ 361 #define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 362 #define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 363 #define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff 364 365 /* Description TCL_GSE_CMD_6_RING_ID 366 367 Helps with debugging when dumping ring contents. 368 369 <legal all> 370 */ 371 #define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 372 #define TCL_GSE_CMD_6_RING_ID_LSB 20 373 #define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 374 375 /* Description TCL_GSE_CMD_6_LOOPING_COUNT 376 377 A count value that indicates the number of times the 378 producer of entries into the Ring has looped around the 379 ring. 380 381 At initialization time, this value is set to 0. On the 382 first loop, this value is set to 1. After the max value is 383 reached allowed by the number of bits for this field, the 384 count value continues with 0 again. 385 386 387 388 In case SW is the consumer of the ring entries, it can 389 use this field to figure out up to where the producer of 390 entries has created new entries. This eliminates the need to 391 check where the head pointer' of the ring is located once 392 the SW starts processing an interrupt indicating that new 393 entries have been put into this ring... 394 395 396 397 Also note that SW if it wants only needs to look at the 398 LSB bit of this count value. 399 400 <legal all> 401 */ 402 #define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 403 #define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 404 #define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 405 406 407 #endif // _TCL_GSE_CMD_H_ 408