1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __MAC_TCL_REG_SEQ_REG_H__ 20 #define __MAC_TCL_REG_SEQ_REG_H__ 21 22 #include "seq_hwio.h" 23 #include "mac_tcl_reg_seq_hwiobase.h" 24 #ifdef SCALE_INCLUDES 25 #include "HALhwio.h" 26 #else 27 #include "msmhwio.h" 28 #endif 29 30 31 /////////////////////////////////////////////////////////////////////////////////////////////// 32 // Register Data for Block MAC_TCL_REG 33 /////////////////////////////////////////////////////////////////////////////////////////////// 34 35 //// Register TCL_R0_SW2TCL1_RING_CTRL //// 36 37 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) 38 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) 39 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 40 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 41 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ 42 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) 43 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ 44 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 45 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ 46 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) 47 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 48 do {\ 49 HWIO_INTLOCK(); \ 50 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ 51 HWIO_INTFREE();\ 52 } while (0) 53 54 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 55 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 56 57 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 58 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 59 60 //// Register TCL_R0_SW2TCL2_RING_CTRL //// 61 62 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) 63 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) 64 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 65 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 66 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ 67 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) 68 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ 69 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 70 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ 71 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) 72 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ 73 do {\ 74 HWIO_INTLOCK(); \ 75 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ 76 HWIO_INTFREE();\ 77 } while (0) 78 79 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 80 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 81 82 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 83 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 84 85 //// Register TCL_R0_SW2TCL3_RING_CTRL //// 86 87 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) 88 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) 89 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 90 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 91 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ 92 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) 93 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ 94 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 95 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ 96 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) 97 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ 98 do {\ 99 HWIO_INTLOCK(); \ 100 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ 101 HWIO_INTFREE();\ 102 } while (0) 103 104 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 105 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 106 107 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 108 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 109 110 //// Register TCL_R0_FW2TCL1_RING_CTRL //// 111 112 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) 113 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) 114 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 115 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 116 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ 117 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) 118 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ 119 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 120 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ 121 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) 122 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 123 do {\ 124 HWIO_INTLOCK(); \ 125 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ 126 HWIO_INTFREE();\ 127 } while (0) 128 129 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 130 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 131 132 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 133 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 134 135 //// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// 136 137 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) 138 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) 139 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0003ffe0 140 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 5 141 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ 142 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) 143 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ 144 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) 145 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val) \ 146 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val) 147 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val) \ 148 do {\ 149 HWIO_INTLOCK(); \ 150 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \ 151 HWIO_INTFREE();\ 152 } while (0) 153 154 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 155 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 156 157 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 158 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 159 160 //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// 161 162 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) 163 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) 164 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x000fffff 165 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 166 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ 167 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) 168 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ 169 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 170 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ 171 out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) 172 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ 173 do {\ 174 HWIO_INTLOCK(); \ 175 out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ 176 HWIO_INTFREE();\ 177 } while (0) 178 179 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x00080000 180 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 0x13 181 182 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_BMSK 0x00040000 183 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_SHFT 0x12 184 185 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x00020000 186 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 0x11 187 188 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x0001c000 189 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 0xe 190 191 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x00002000 192 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 0xd 193 194 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_BMSK 0x00001000 195 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_SHFT 0xc 196 197 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 198 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb 199 200 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 201 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa 202 203 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 204 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 205 206 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 207 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 208 209 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_BMSK 0x00000080 210 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_SHFT 0x7 211 212 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 213 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 214 215 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 216 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 217 218 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 219 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 220 221 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 222 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 223 224 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 225 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 226 227 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 228 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 229 230 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 231 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 232 233 //// Register TCL_R0_TCL2TQM_RING_CTRL //// 234 235 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) 236 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) 237 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x00003fff 238 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 239 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ 240 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) 241 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ 242 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 243 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ 244 out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) 245 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ 246 do {\ 247 HWIO_INTLOCK(); \ 248 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ 249 HWIO_INTFREE();\ 250 } while (0) 251 252 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x00002000 253 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 0xd 254 255 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x00001000 256 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 0xc 257 258 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 259 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 260 261 //// Register TCL_R0_TCL2FW_RING_CTRL //// 262 263 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) 264 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) 265 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff 266 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 267 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ 268 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) 269 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ 270 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 271 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ 272 out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) 273 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ 274 do {\ 275 HWIO_INTLOCK(); \ 276 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ 277 HWIO_INTFREE();\ 278 } while (0) 279 280 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 281 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 282 283 //// Register TCL_R0_TCL_STATUS1_RING_CTRL //// 284 285 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) 286 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) 287 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff 288 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 289 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ 290 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) 291 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ 292 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 293 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ 294 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) 295 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ 296 do {\ 297 HWIO_INTLOCK(); \ 298 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ 299 HWIO_INTFREE();\ 300 } while (0) 301 302 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 303 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 304 305 //// Register TCL_R0_TCL_STATUS2_RING_CTRL //// 306 307 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) 308 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) 309 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff 310 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 311 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ 312 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) 313 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ 314 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 315 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ 316 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) 317 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ 318 do {\ 319 HWIO_INTLOCK(); \ 320 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ 321 HWIO_INTFREE();\ 322 } while (0) 323 324 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 325 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 326 327 //// Register TCL_R0_GEN_CTRL //// 328 329 #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) 330 #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) 331 #define HWIO_TCL_R0_GEN_CTRL_RMSK 0xfffff1fb 332 #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 333 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ 334 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) 335 #define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ 336 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 337 #define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ 338 out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) 339 #define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ 340 do {\ 341 HWIO_INTLOCK(); \ 342 out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ 343 HWIO_INTFREE();\ 344 } while (0) 345 346 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 347 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 348 349 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x00008000 350 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 0xf 351 352 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 353 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe 354 355 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 356 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd 357 358 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 359 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc 360 361 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 362 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 363 364 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 365 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 366 367 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 368 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 369 370 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 371 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 372 373 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 374 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 375 376 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 377 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 378 379 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x00000002 380 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 0x1 381 382 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 383 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 384 385 //// Register TCL_R0_DSCP_TID_MAP_n //// 386 387 #define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n) (base+0x2C+0x4*n) 388 #define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base, n) (base+0x2C+0x4*n) 389 #define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff 390 #define HWIO_TCL_R0_DSCP_TID_MAP_n_SHFT 0 391 #define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 287 392 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n) \ 393 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) 394 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base, n, mask) \ 395 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask) 396 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base, n, val) \ 397 out_dword( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), val) 398 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base, n, mask, val) \ 399 do {\ 400 HWIO_INTLOCK(); \ 401 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask, val, HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n)); \ 402 HWIO_INTFREE();\ 403 } while (0) 404 405 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff 406 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0x0 407 408 //// Register TCL_R0_PCP_TID_MAP //// 409 410 #define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x000004ac) 411 #define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x000004ac) 412 #define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff 413 #define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 414 #define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ 415 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) 416 #define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ 417 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 418 #define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ 419 out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) 420 #define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ 421 do {\ 422 HWIO_INTLOCK(); \ 423 out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ 424 HWIO_INTFREE();\ 425 } while (0) 426 427 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 428 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 429 430 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 431 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 432 433 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 434 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf 435 436 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 437 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc 438 439 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 440 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 441 442 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 443 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 444 445 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 446 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 447 448 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 449 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 450 451 //// Register TCL_R0_ASE_HASH_KEY_31_0 //// 452 453 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x000004b0) 454 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x000004b0) 455 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff 456 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 457 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ 458 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) 459 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ 460 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 461 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ 462 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) 463 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ 464 do {\ 465 HWIO_INTLOCK(); \ 466 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ 467 HWIO_INTFREE();\ 468 } while (0) 469 470 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 471 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 472 473 //// Register TCL_R0_ASE_HASH_KEY_63_32 //// 474 475 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x000004b4) 476 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x000004b4) 477 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff 478 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 479 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ 480 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) 481 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ 482 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 483 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ 484 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) 485 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ 486 do {\ 487 HWIO_INTLOCK(); \ 488 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ 489 HWIO_INTFREE();\ 490 } while (0) 491 492 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 493 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 494 495 //// Register TCL_R0_ASE_HASH_KEY_64 //// 496 497 #define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x000004b8) 498 #define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x000004b8) 499 #define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 500 #define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 501 #define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ 502 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) 503 #define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ 504 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 505 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ 506 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) 507 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ 508 do {\ 509 HWIO_INTLOCK(); \ 510 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ 511 HWIO_INTFREE();\ 512 } while (0) 513 514 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 515 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 516 517 //// Register TCL_R0_CONFIG_SEARCH_QUEUE //// 518 519 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x000004bc) 520 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x000004bc) 521 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00fffdfc 522 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 523 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ 524 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) 525 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ 526 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 527 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ 528 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) 529 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ 530 do {\ 531 HWIO_INTLOCK(); \ 532 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ 533 HWIO_INTFREE();\ 534 } while (0) 535 536 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_BMSK 0x00800000 537 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_SHFT 0x17 538 539 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x00700000 540 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 0x14 541 542 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0x000e0000 543 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 0x11 544 545 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x0001c000 546 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 0xe 547 548 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 549 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd 550 551 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 552 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc 553 554 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 555 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb 556 557 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 558 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa 559 560 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 561 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 562 563 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 564 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 565 566 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c 567 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 568 569 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// 570 571 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c0) 572 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c0) 573 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 574 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 575 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ 576 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) 577 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 578 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 579 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 580 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 581 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 582 do {\ 583 HWIO_INTLOCK(); \ 584 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 585 HWIO_INTFREE();\ 586 } while (0) 587 588 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 589 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 590 591 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// 592 593 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004c4) 594 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004c4) 595 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 596 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 597 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 598 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) 599 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 600 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 601 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 602 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 603 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 604 do {\ 605 HWIO_INTLOCK(); \ 606 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 607 HWIO_INTFREE();\ 608 } while (0) 609 610 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 611 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 612 613 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// 614 615 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c8) 616 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c8) 617 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 618 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 619 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ 620 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) 621 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 622 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 623 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 624 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 625 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 626 do {\ 627 HWIO_INTLOCK(); \ 628 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 629 HWIO_INTFREE();\ 630 } while (0) 631 632 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 633 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 634 635 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// 636 637 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004cc) 638 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004cc) 639 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 640 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 641 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 642 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) 643 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 644 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 645 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 646 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 647 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 648 do {\ 649 HWIO_INTLOCK(); \ 650 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 651 HWIO_INTFREE();\ 652 } while (0) 653 654 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 655 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 656 657 //// Register TCL_R0_CONFIG_SEARCH_METADATA //// 658 659 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000004d0) 660 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000004d0) 661 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff 662 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 663 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ 664 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) 665 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ 666 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 667 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ 668 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) 669 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ 670 do {\ 671 HWIO_INTLOCK(); \ 672 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ 673 HWIO_INTFREE();\ 674 } while (0) 675 676 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 677 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 678 679 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff 680 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 681 682 //// Register TCL_R0_TID_MAP_PRTY //// 683 684 #define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000004d4) 685 #define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000004d4) 686 #define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef 687 #define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 688 #define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ 689 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) 690 #define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ 691 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 692 #define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ 693 out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) 694 #define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ 695 do {\ 696 HWIO_INTLOCK(); \ 697 out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ 698 HWIO_INTFREE();\ 699 } while (0) 700 701 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 702 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 703 704 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f 705 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 706 707 //// Register TCL_R0_INVALID_APB_ACC_ADDR //// 708 709 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000004d8) 710 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000004d8) 711 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff 712 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 713 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ 714 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) 715 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ 716 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 717 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ 718 out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) 719 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ 720 do {\ 721 HWIO_INTLOCK(); \ 722 out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ 723 HWIO_INTFREE();\ 724 } while (0) 725 726 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff 727 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 728 729 //// Register TCL_R0_WATCHDOG //// 730 731 #define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000004dc) 732 #define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000004dc) 733 #define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff 734 #define HWIO_TCL_R0_WATCHDOG_SHFT 0 735 #define HWIO_TCL_R0_WATCHDOG_IN(x) \ 736 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) 737 #define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ 738 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 739 #define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ 740 out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) 741 #define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ 742 do {\ 743 HWIO_INTLOCK(); \ 744 out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ 745 HWIO_INTFREE();\ 746 } while (0) 747 748 #define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 749 #define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 750 751 #define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff 752 #define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 753 754 //// Register TCL_R0_LCE_RULE_n //// 755 756 #define HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n) (base+0x4E0+0x4*n) 757 #define HWIO_TCL_R0_LCE_RULE_n_PHYS(base, n) (base+0x4E0+0x4*n) 758 #define HWIO_TCL_R0_LCE_RULE_n_RMSK 0x007fffff 759 #define HWIO_TCL_R0_LCE_RULE_n_SHFT 0 760 #define HWIO_TCL_R0_LCE_RULE_n_MAXn 25 761 #define HWIO_TCL_R0_LCE_RULE_n_INI(base, n) \ 762 in_dword_masked ( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), HWIO_TCL_R0_LCE_RULE_n_RMSK) 763 #define HWIO_TCL_R0_LCE_RULE_n_INMI(base, n, mask) \ 764 in_dword_masked ( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), mask) 765 #define HWIO_TCL_R0_LCE_RULE_n_OUTI(base, n, val) \ 766 out_dword( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), val) 767 #define HWIO_TCL_R0_LCE_RULE_n_OUTMI(base, n, mask, val) \ 768 do {\ 769 HWIO_INTLOCK(); \ 770 out_dword_masked_ns(HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_RULE_n_INI(base, n)); \ 771 HWIO_INTFREE();\ 772 } while (0) 773 774 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_BMSK 0x00400000 775 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_SHFT 0x16 776 777 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_BMSK 0x00200000 778 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_SHFT 0x15 779 780 #define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_BMSK 0x00180000 781 #define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_SHFT 0x13 782 783 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_BMSK 0x00040000 784 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_SHFT 0x12 785 786 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_BMSK 0x00020000 787 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_SHFT 0x11 788 789 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_BMSK 0x00010000 790 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_SHFT 0x10 791 792 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_BMSK 0x0000ffff 793 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_SHFT 0x0 794 795 //// Register TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n //// 796 797 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n) (base+0x548+0x4*n) 798 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_PHYS(base, n) (base+0x548+0x4*n) 799 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK 0xffffffff 800 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_SHFT 0 801 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_MAXn 25 802 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base, n) \ 803 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK) 804 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INMI(base, n, mask) \ 805 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), mask) 806 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTI(base, n, val) \ 807 out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), val) 808 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTMI(base, n, mask, val) \ 809 do {\ 810 HWIO_INTLOCK(); \ 811 out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base, n)); \ 812 HWIO_INTFREE();\ 813 } while (0) 814 815 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_BMSK 0xffffffff 816 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_SHFT 0x0 817 818 //// Register TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n //// 819 820 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n) (base+0x5B0+0x4*n) 821 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_PHYS(base, n) (base+0x5B0+0x4*n) 822 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK 0x000000ff 823 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_SHFT 0 824 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_MAXn 25 825 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base, n) \ 826 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK) 827 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INMI(base, n, mask) \ 828 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), mask) 829 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTI(base, n, val) \ 830 out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), val) 831 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTMI(base, n, mask, val) \ 832 do {\ 833 HWIO_INTLOCK(); \ 834 out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base, n)); \ 835 HWIO_INTFREE();\ 836 } while (0) 837 838 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_BMSK 0x000000ff 839 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_SHFT 0x0 840 841 //// Register TCL_R0_LCE_CLFY_INFO_HANDLER_n //// 842 843 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n) (base+0x618+0x4*n) 844 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_PHYS(base, n) (base+0x618+0x4*n) 845 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK 0x003fffff 846 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_SHFT 0 847 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MAXn 25 848 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base, n) \ 849 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK) 850 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INMI(base, n, mask) \ 851 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), mask) 852 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTI(base, n, val) \ 853 out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), val) 854 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTMI(base, n, mask, val) \ 855 do {\ 856 HWIO_INTLOCK(); \ 857 out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base, n)); \ 858 HWIO_INTFREE();\ 859 } while (0) 860 861 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_BMSK 0x00200000 862 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_SHFT 0x15 863 864 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_BMSK 0x001fffe0 865 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_SHFT 0x5 866 867 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_BMSK 0x00000010 868 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_SHFT 0x4 869 870 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_BMSK 0x00000008 871 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_SHFT 0x3 872 873 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_BMSK 0x00000004 874 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_SHFT 0x2 875 876 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_BMSK 0x00000003 877 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_SHFT 0x0 878 879 //// Register TCL_R0_CLKGATE_DISABLE //// 880 881 #define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x00000680) 882 #define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x00000680) 883 #define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff 884 #define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 885 #define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ 886 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) 887 #define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ 888 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 889 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ 890 out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) 891 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ 892 do {\ 893 HWIO_INTLOCK(); \ 894 out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ 895 HWIO_INTFREE();\ 896 } while (0) 897 898 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 899 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_SHFT 0x1f 900 901 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 902 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 903 904 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_BMSK 0x20000000 905 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_SHFT 0x1d 906 907 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_BMSK 0x10000000 908 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_SHFT 0x1c 909 910 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_BMSK 0x08000000 911 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_SHFT 0x1b 912 913 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_BMSK 0x04000000 914 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_SHFT 0x1a 915 916 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_BMSK 0x02000000 917 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_SHFT 0x19 918 919 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_BMSK 0x01000000 920 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_SHFT 0x18 921 922 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_BMSK 0x00800000 923 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_SHFT 0x17 924 925 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_BMSK 0x00400000 926 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_SHFT 0x16 927 928 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_BMSK 0x00200000 929 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_SHFT 0x15 930 931 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_BMSK 0x00100000 932 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_SHFT 0x14 933 934 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_BMSK 0x00080000 935 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_SHFT 0x13 936 937 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_BMSK 0x00040000 938 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_SHFT 0x12 939 940 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_BMSK 0x00020000 941 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_SHFT 0x11 942 943 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_BMSK 0x00010000 944 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_SHFT 0x10 945 946 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_BMSK 0x00008000 947 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_SHFT 0xf 948 949 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_BMSK 0x00004000 950 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_SHFT 0xe 951 952 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_BMSK 0x00002000 953 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_SHFT 0xd 954 955 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_BMSK 0x00001000 956 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_SHFT 0xc 957 958 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_BMSK 0x00000800 959 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_SHFT 0xb 960 961 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_BMSK 0x00000400 962 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_SHFT 0xa 963 964 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_BMSK 0x00000200 965 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_SHFT 0x9 966 967 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_BMSK 0x00000100 968 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_SHFT 0x8 969 970 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_BMSK 0x00000080 971 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_SHFT 0x7 972 973 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_BMSK 0x00000040 974 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_SHFT 0x6 975 976 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_BMSK 0x00000020 977 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_SHFT 0x5 978 979 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_BMSK 0x00000010 980 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_SHFT 0x4 981 982 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_BMSK 0x00000008 983 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_SHFT 0x3 984 985 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_BMSK 0x00000004 986 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_SHFT 0x2 987 988 #define HWIO_TCL_R0_CLKGATE_DISABLE_LCE_BMSK 0x00000002 989 #define HWIO_TCL_R0_CLKGATE_DISABLE_LCE_SHFT 0x1 990 991 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_BMSK 0x00000001 992 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_SHFT 0x0 993 994 //// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// 995 996 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000684) 997 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000684) 998 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 999 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 1000 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ 1001 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) 1002 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ 1003 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 1004 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ 1005 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) 1006 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 1007 do {\ 1008 HWIO_INTLOCK(); \ 1009 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ 1010 HWIO_INTFREE();\ 1011 } while (0) 1012 1013 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1014 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1015 1016 //// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// 1017 1018 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000688) 1019 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000688) 1020 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x0fffffff 1021 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 1022 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ 1023 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) 1024 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ 1025 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 1026 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ 1027 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) 1028 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 1029 do {\ 1030 HWIO_INTLOCK(); \ 1031 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ 1032 HWIO_INTFREE();\ 1033 } while (0) 1034 1035 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1036 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1037 1038 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1039 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1040 1041 //// Register TCL_R0_SW2TCL1_RING_ID //// 1042 1043 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x0000068c) 1044 #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x0000068c) 1045 #define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff 1046 #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 1047 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ 1048 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) 1049 #define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ 1050 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 1051 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ 1052 out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) 1053 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ 1054 do {\ 1055 HWIO_INTLOCK(); \ 1056 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ 1057 HWIO_INTFREE();\ 1058 } while (0) 1059 1060 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1061 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 1062 1063 //// Register TCL_R0_SW2TCL1_RING_STATUS //// 1064 1065 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x00000690) 1066 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x00000690) 1067 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff 1068 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 1069 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ 1070 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) 1071 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ 1072 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 1073 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ 1074 out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) 1075 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 1076 do {\ 1077 HWIO_INTLOCK(); \ 1078 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ 1079 HWIO_INTFREE();\ 1080 } while (0) 1081 1082 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1083 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1084 1085 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1086 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1087 1088 //// Register TCL_R0_SW2TCL1_RING_MISC //// 1089 1090 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x00000694) 1091 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x00000694) 1092 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff 1093 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 1094 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ 1095 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) 1096 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ 1097 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 1098 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ 1099 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) 1100 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ 1101 do {\ 1102 HWIO_INTLOCK(); \ 1103 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ 1104 HWIO_INTFREE();\ 1105 } while (0) 1106 1107 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1108 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 1109 1110 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1111 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1112 1113 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1114 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1115 1116 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1117 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1118 1119 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1120 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 1121 1122 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1123 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1124 1125 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1126 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1127 1128 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1129 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1130 1131 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1132 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 1133 1134 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1135 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1136 1137 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1138 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1139 1140 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// 1141 1142 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000006a0) 1143 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000006a0) 1144 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1145 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 1146 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 1147 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) 1148 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 1149 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 1150 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 1151 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 1152 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1153 do {\ 1154 HWIO_INTLOCK(); \ 1155 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 1156 HWIO_INTFREE();\ 1157 } while (0) 1158 1159 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1160 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1161 1162 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// 1163 1164 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000006a4) 1165 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000006a4) 1166 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1167 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 1168 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 1169 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) 1170 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 1171 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 1172 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 1173 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 1174 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1175 do {\ 1176 HWIO_INTLOCK(); \ 1177 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 1178 HWIO_INTFREE();\ 1179 } while (0) 1180 1181 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1182 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1183 1184 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 1185 1186 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000006b4) 1187 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000006b4) 1188 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1189 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1190 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1191 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1192 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1193 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1194 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1195 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1196 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1197 do {\ 1198 HWIO_INTLOCK(); \ 1199 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1200 HWIO_INTFREE();\ 1201 } while (0) 1202 1203 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1204 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1205 1206 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1207 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1208 1209 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1210 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1211 1212 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 1213 1214 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000006b8) 1215 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000006b8) 1216 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1217 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1218 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1219 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1220 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1221 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1222 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1223 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1224 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1225 do {\ 1226 HWIO_INTLOCK(); \ 1227 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1228 HWIO_INTFREE();\ 1229 } while (0) 1230 1231 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1232 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1233 1234 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// 1235 1236 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000006bc) 1237 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000006bc) 1238 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1239 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 1240 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 1241 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 1242 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1243 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1244 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1245 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1246 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1247 do {\ 1248 HWIO_INTLOCK(); \ 1249 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1250 HWIO_INTFREE();\ 1251 } while (0) 1252 1253 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1254 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1255 1256 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1257 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1258 1259 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1260 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1261 1262 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 1263 1264 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000006c0) 1265 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000006c0) 1266 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1267 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1268 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1269 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1270 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1271 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1272 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1273 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1274 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1275 do {\ 1276 HWIO_INTLOCK(); \ 1277 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1278 HWIO_INTFREE();\ 1279 } while (0) 1280 1281 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1282 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1283 1284 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 1285 1286 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000006c4) 1287 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000006c4) 1288 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1289 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1290 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1291 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1292 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1293 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1294 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1295 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1296 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1297 do {\ 1298 HWIO_INTLOCK(); \ 1299 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1300 HWIO_INTFREE();\ 1301 } while (0) 1302 1303 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1304 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1305 1306 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 1307 1308 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000006c8) 1309 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000006c8) 1310 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 1311 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1312 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1313 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1314 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1315 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1316 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1317 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1318 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1319 do {\ 1320 HWIO_INTLOCK(); \ 1321 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1322 HWIO_INTFREE();\ 1323 } while (0) 1324 1325 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 1326 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 1327 1328 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 1329 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1330 1331 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// 1332 1333 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006cc) 1334 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006cc) 1335 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1336 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 1337 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 1338 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) 1339 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1340 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1341 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1342 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 1343 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1344 do {\ 1345 HWIO_INTLOCK(); \ 1346 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 1347 HWIO_INTFREE();\ 1348 } while (0) 1349 1350 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1351 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1352 1353 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// 1354 1355 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006d0) 1356 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006d0) 1357 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1358 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 1359 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 1360 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) 1361 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1362 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1363 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1364 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 1365 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1366 do {\ 1367 HWIO_INTLOCK(); \ 1368 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 1369 HWIO_INTFREE();\ 1370 } while (0) 1371 1372 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1373 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1374 1375 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1376 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1377 1378 //// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// 1379 1380 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006d4) 1381 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006d4) 1382 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 1383 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 1384 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ 1385 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) 1386 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 1387 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 1388 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 1389 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) 1390 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1391 do {\ 1392 HWIO_INTLOCK(); \ 1393 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ 1394 HWIO_INTFREE();\ 1395 } while (0) 1396 1397 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1398 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 1399 1400 //// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// 1401 1402 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006d8) 1403 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006d8) 1404 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1405 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 1406 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 1407 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 1408 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1409 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1410 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1411 out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1412 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1413 do {\ 1414 HWIO_INTLOCK(); \ 1415 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 1416 HWIO_INTFREE();\ 1417 } while (0) 1418 1419 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1420 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1421 1422 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// 1423 1424 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x000006dc) 1425 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x000006dc) 1426 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff 1427 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 1428 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ 1429 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) 1430 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ 1431 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 1432 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ 1433 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) 1434 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ 1435 do {\ 1436 HWIO_INTLOCK(); \ 1437 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ 1438 HWIO_INTFREE();\ 1439 } while (0) 1440 1441 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1442 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1443 1444 //// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// 1445 1446 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x000006e0) 1447 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x000006e0) 1448 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x0fffffff 1449 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 1450 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ 1451 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) 1452 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ 1453 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 1454 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ 1455 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) 1456 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ 1457 do {\ 1458 HWIO_INTLOCK(); \ 1459 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ 1460 HWIO_INTFREE();\ 1461 } while (0) 1462 1463 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1464 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1465 1466 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1467 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1468 1469 //// Register TCL_R0_SW2TCL2_RING_ID //// 1470 1471 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x000006e4) 1472 #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x000006e4) 1473 #define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff 1474 #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 1475 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ 1476 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) 1477 #define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ 1478 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 1479 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ 1480 out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) 1481 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ 1482 do {\ 1483 HWIO_INTLOCK(); \ 1484 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ 1485 HWIO_INTFREE();\ 1486 } while (0) 1487 1488 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1489 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 1490 1491 //// Register TCL_R0_SW2TCL2_RING_STATUS //// 1492 1493 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x000006e8) 1494 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x000006e8) 1495 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff 1496 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 1497 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ 1498 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) 1499 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ 1500 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 1501 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ 1502 out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) 1503 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ 1504 do {\ 1505 HWIO_INTLOCK(); \ 1506 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ 1507 HWIO_INTFREE();\ 1508 } while (0) 1509 1510 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1511 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1512 1513 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1514 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1515 1516 //// Register TCL_R0_SW2TCL2_RING_MISC //// 1517 1518 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x000006ec) 1519 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x000006ec) 1520 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff 1521 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 1522 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ 1523 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) 1524 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ 1525 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 1526 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ 1527 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) 1528 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ 1529 do {\ 1530 HWIO_INTLOCK(); \ 1531 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ 1532 HWIO_INTFREE();\ 1533 } while (0) 1534 1535 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1536 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 0xe 1537 1538 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1539 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1540 1541 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1542 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1543 1544 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1545 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1546 1547 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1548 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 0x6 1549 1550 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1551 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1552 1553 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1554 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1555 1556 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1557 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1558 1559 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1560 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 1561 1562 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1563 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1564 1565 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1566 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1567 1568 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// 1569 1570 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x000006f8) 1571 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x000006f8) 1572 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff 1573 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 1574 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ 1575 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) 1576 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ 1577 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 1578 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ 1579 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) 1580 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1581 do {\ 1582 HWIO_INTLOCK(); \ 1583 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ 1584 HWIO_INTFREE();\ 1585 } while (0) 1586 1587 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1588 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1589 1590 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// 1591 1592 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x000006fc) 1593 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x000006fc) 1594 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff 1595 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 1596 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ 1597 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) 1598 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ 1599 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 1600 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ 1601 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) 1602 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1603 do {\ 1604 HWIO_INTLOCK(); \ 1605 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ 1606 HWIO_INTFREE();\ 1607 } while (0) 1608 1609 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1610 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1611 1612 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// 1613 1614 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000070c) 1615 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000070c) 1616 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1617 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1618 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1619 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1620 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1621 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1622 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1623 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1624 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1625 do {\ 1626 HWIO_INTLOCK(); \ 1627 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1628 HWIO_INTFREE();\ 1629 } while (0) 1630 1631 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1632 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1633 1634 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1635 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1636 1637 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1638 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1639 1640 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// 1641 1642 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000710) 1643 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000710) 1644 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1645 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1646 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1647 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1648 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1649 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1650 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1651 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1652 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1653 do {\ 1654 HWIO_INTLOCK(); \ 1655 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1656 HWIO_INTFREE();\ 1657 } while (0) 1658 1659 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1660 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1661 1662 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// 1663 1664 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000714) 1665 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000714) 1666 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1667 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 1668 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ 1669 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) 1670 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1671 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1672 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1673 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1674 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1675 do {\ 1676 HWIO_INTLOCK(); \ 1677 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ 1678 HWIO_INTFREE();\ 1679 } while (0) 1680 1681 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1682 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1683 1684 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1685 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1686 1687 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1688 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1689 1690 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// 1691 1692 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000718) 1693 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000718) 1694 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1695 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1696 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1697 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1698 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1699 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1700 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1701 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1702 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1703 do {\ 1704 HWIO_INTLOCK(); \ 1705 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1706 HWIO_INTFREE();\ 1707 } while (0) 1708 1709 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1710 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1711 1712 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// 1713 1714 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000071c) 1715 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000071c) 1716 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1717 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1718 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1719 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1720 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1721 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1722 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1723 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1724 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1725 do {\ 1726 HWIO_INTLOCK(); \ 1727 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1728 HWIO_INTFREE();\ 1729 } while (0) 1730 1731 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1732 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1733 1734 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// 1735 1736 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000720) 1737 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000720) 1738 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 1739 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1740 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1741 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1742 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1743 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1744 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1745 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1746 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1747 do {\ 1748 HWIO_INTLOCK(); \ 1749 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1750 HWIO_INTFREE();\ 1751 } while (0) 1752 1753 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 1754 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 1755 1756 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 1757 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1758 1759 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// 1760 1761 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000724) 1762 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000724) 1763 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1764 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 1765 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ 1766 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) 1767 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ 1768 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 1769 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ 1770 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) 1771 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1772 do {\ 1773 HWIO_INTLOCK(); \ 1774 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ 1775 HWIO_INTFREE();\ 1776 } while (0) 1777 1778 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1779 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1780 1781 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// 1782 1783 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000728) 1784 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000728) 1785 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1786 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 1787 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ 1788 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) 1789 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ 1790 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 1791 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ 1792 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) 1793 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1794 do {\ 1795 HWIO_INTLOCK(); \ 1796 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ 1797 HWIO_INTFREE();\ 1798 } while (0) 1799 1800 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1801 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1802 1803 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1804 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1805 1806 //// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// 1807 1808 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x0000072c) 1809 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x0000072c) 1810 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff 1811 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 1812 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ 1813 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) 1814 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ 1815 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 1816 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ 1817 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) 1818 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ 1819 do {\ 1820 HWIO_INTLOCK(); \ 1821 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ 1822 HWIO_INTFREE();\ 1823 } while (0) 1824 1825 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1826 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 1827 1828 //// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// 1829 1830 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000730) 1831 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000730) 1832 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1833 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 1834 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ 1835 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) 1836 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1837 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1838 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1839 out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1840 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1841 do {\ 1842 HWIO_INTLOCK(); \ 1843 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ 1844 HWIO_INTFREE();\ 1845 } while (0) 1846 1847 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1848 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1849 1850 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// 1851 1852 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000734) 1853 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000734) 1854 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff 1855 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 1856 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ 1857 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) 1858 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ 1859 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 1860 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ 1861 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) 1862 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ 1863 do {\ 1864 HWIO_INTLOCK(); \ 1865 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ 1866 HWIO_INTFREE();\ 1867 } while (0) 1868 1869 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1870 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1871 1872 //// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// 1873 1874 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000738) 1875 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000738) 1876 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x0fffffff 1877 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 1878 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ 1879 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) 1880 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ 1881 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 1882 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ 1883 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) 1884 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ 1885 do {\ 1886 HWIO_INTLOCK(); \ 1887 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ 1888 HWIO_INTFREE();\ 1889 } while (0) 1890 1891 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1892 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1893 1894 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1895 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1896 1897 //// Register TCL_R0_SW2TCL3_RING_ID //// 1898 1899 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000073c) 1900 #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000073c) 1901 #define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff 1902 #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 1903 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ 1904 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) 1905 #define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ 1906 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 1907 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ 1908 out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) 1909 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ 1910 do {\ 1911 HWIO_INTLOCK(); \ 1912 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ 1913 HWIO_INTFREE();\ 1914 } while (0) 1915 1916 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1917 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 1918 1919 //// Register TCL_R0_SW2TCL3_RING_STATUS //// 1920 1921 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x00000740) 1922 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x00000740) 1923 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff 1924 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 1925 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ 1926 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) 1927 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ 1928 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 1929 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ 1930 out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) 1931 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ 1932 do {\ 1933 HWIO_INTLOCK(); \ 1934 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ 1935 HWIO_INTFREE();\ 1936 } while (0) 1937 1938 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1939 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1940 1941 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1942 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1943 1944 //// Register TCL_R0_SW2TCL3_RING_MISC //// 1945 1946 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000744) 1947 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000744) 1948 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff 1949 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 1950 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ 1951 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) 1952 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ 1953 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 1954 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ 1955 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) 1956 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ 1957 do {\ 1958 HWIO_INTLOCK(); \ 1959 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ 1960 HWIO_INTFREE();\ 1961 } while (0) 1962 1963 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1964 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 0xe 1965 1966 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1967 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1968 1969 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1970 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1971 1972 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1973 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1974 1975 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1976 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 0x6 1977 1978 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1979 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1980 1981 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1982 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1983 1984 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1985 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1986 1987 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1988 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 1989 1990 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1991 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1992 1993 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1994 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1995 1996 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// 1997 1998 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000750) 1999 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000750) 2000 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff 2001 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 2002 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ 2003 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) 2004 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ 2005 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 2006 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ 2007 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) 2008 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2009 do {\ 2010 HWIO_INTLOCK(); \ 2011 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ 2012 HWIO_INTFREE();\ 2013 } while (0) 2014 2015 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2016 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2017 2018 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// 2019 2020 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000754) 2021 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000754) 2022 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff 2023 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 2024 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ 2025 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) 2026 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ 2027 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 2028 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ 2029 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) 2030 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2031 do {\ 2032 HWIO_INTLOCK(); \ 2033 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ 2034 HWIO_INTFREE();\ 2035 } while (0) 2036 2037 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2038 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2039 2040 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// 2041 2042 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000764) 2043 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000764) 2044 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2045 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2046 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2047 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2048 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2049 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2050 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2051 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2052 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2053 do {\ 2054 HWIO_INTLOCK(); \ 2055 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2056 HWIO_INTFREE();\ 2057 } while (0) 2058 2059 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2060 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2061 2062 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2063 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2064 2065 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2066 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2067 2068 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// 2069 2070 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000768) 2071 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000768) 2072 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2073 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2074 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2075 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2076 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2077 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2078 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2079 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2080 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2081 do {\ 2082 HWIO_INTLOCK(); \ 2083 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2084 HWIO_INTFREE();\ 2085 } while (0) 2086 2087 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2088 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2089 2090 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// 2091 2092 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000076c) 2093 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000076c) 2094 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2095 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 2096 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ 2097 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) 2098 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2099 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2100 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2101 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2102 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2103 do {\ 2104 HWIO_INTLOCK(); \ 2105 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ 2106 HWIO_INTFREE();\ 2107 } while (0) 2108 2109 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2110 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2111 2112 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2113 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2114 2115 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2116 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2117 2118 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// 2119 2120 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000770) 2121 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000770) 2122 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2123 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2124 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2125 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2126 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2127 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2128 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2129 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2130 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2131 do {\ 2132 HWIO_INTLOCK(); \ 2133 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2134 HWIO_INTFREE();\ 2135 } while (0) 2136 2137 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2138 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2139 2140 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// 2141 2142 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000774) 2143 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000774) 2144 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2145 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2146 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2147 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2148 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2149 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2150 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2151 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2152 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2153 do {\ 2154 HWIO_INTLOCK(); \ 2155 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2156 HWIO_INTFREE();\ 2157 } while (0) 2158 2159 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2160 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2161 2162 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// 2163 2164 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000778) 2165 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000778) 2166 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 2167 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2168 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2169 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2170 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2171 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2172 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2173 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2174 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2175 do {\ 2176 HWIO_INTLOCK(); \ 2177 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2178 HWIO_INTFREE();\ 2179 } while (0) 2180 2181 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 2182 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 2183 2184 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 2185 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2186 2187 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// 2188 2189 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000077c) 2190 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000077c) 2191 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2192 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 2193 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ 2194 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) 2195 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ 2196 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 2197 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ 2198 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) 2199 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2200 do {\ 2201 HWIO_INTLOCK(); \ 2202 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ 2203 HWIO_INTFREE();\ 2204 } while (0) 2205 2206 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2207 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2208 2209 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// 2210 2211 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000780) 2212 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000780) 2213 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2214 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 2215 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ 2216 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) 2217 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ 2218 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 2219 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ 2220 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) 2221 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2222 do {\ 2223 HWIO_INTLOCK(); \ 2224 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ 2225 HWIO_INTFREE();\ 2226 } while (0) 2227 2228 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2229 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2230 2231 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2232 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2233 2234 //// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// 2235 2236 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x00000784) 2237 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x00000784) 2238 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff 2239 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 2240 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ 2241 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) 2242 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ 2243 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 2244 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ 2245 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) 2246 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ 2247 do {\ 2248 HWIO_INTLOCK(); \ 2249 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ 2250 HWIO_INTFREE();\ 2251 } while (0) 2252 2253 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2254 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 2255 2256 //// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// 2257 2258 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000788) 2259 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000788) 2260 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2261 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 2262 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ 2263 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) 2264 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2265 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2266 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2267 out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2268 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2269 do {\ 2270 HWIO_INTLOCK(); \ 2271 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ 2272 HWIO_INTFREE();\ 2273 } while (0) 2274 2275 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2276 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2277 2278 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// 2279 2280 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x) (x+0x0000078c) 2281 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x) (x+0x0000078c) 2282 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK 0xffffffff 2283 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT 0 2284 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x) \ 2285 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK) 2286 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask) \ 2287 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) 2288 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val) \ 2289 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val) 2290 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 2291 do {\ 2292 HWIO_INTLOCK(); \ 2293 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \ 2294 HWIO_INTFREE();\ 2295 } while (0) 2296 2297 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2298 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2299 2300 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB //// 2301 2302 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x) (x+0x00000790) 2303 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x) (x+0x00000790) 2304 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK 0x0fffffff 2305 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT 0 2306 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x) \ 2307 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK) 2308 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask) \ 2309 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) 2310 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val) \ 2311 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val) 2312 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 2313 do {\ 2314 HWIO_INTLOCK(); \ 2315 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \ 2316 HWIO_INTFREE();\ 2317 } while (0) 2318 2319 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2320 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2321 2322 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2323 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2324 2325 //// Register TCL_R0_SW2TCL_CMD_RING_ID //// 2326 2327 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x00000794) 2328 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x00000794) 2329 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x000000ff 2330 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 2331 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ 2332 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) 2333 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask) \ 2334 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) 2335 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val) \ 2336 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val) 2337 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val) \ 2338 do {\ 2339 HWIO_INTLOCK(); \ 2340 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \ 2341 HWIO_INTFREE();\ 2342 } while (0) 2343 2344 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2345 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 2346 2347 //// Register TCL_R0_SW2TCL_CMD_RING_STATUS //// 2348 2349 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x) (x+0x00000798) 2350 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x) (x+0x00000798) 2351 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK 0xffffffff 2352 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT 0 2353 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x) \ 2354 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK) 2355 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask) \ 2356 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) 2357 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val) \ 2358 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val) 2359 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val) \ 2360 do {\ 2361 HWIO_INTLOCK(); \ 2362 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \ 2363 HWIO_INTFREE();\ 2364 } while (0) 2365 2366 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2367 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2368 2369 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2370 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2371 2372 //// Register TCL_R0_SW2TCL_CMD_RING_MISC //// 2373 2374 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x) (x+0x0000079c) 2375 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x) (x+0x0000079c) 2376 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK 0x003fffff 2377 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT 0 2378 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x) \ 2379 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK) 2380 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask) \ 2381 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) 2382 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val) \ 2383 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val) 2384 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val) \ 2385 do {\ 2386 HWIO_INTLOCK(); \ 2387 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \ 2388 HWIO_INTFREE();\ 2389 } while (0) 2390 2391 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2392 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 2393 2394 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2395 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2396 2397 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2398 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2399 2400 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2401 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2402 2403 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2404 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 2405 2406 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2407 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2408 2409 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2410 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2411 2412 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2413 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2414 2415 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2416 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 2417 2418 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2419 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2420 2421 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2422 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2423 2424 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB //// 2425 2426 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000007a8) 2427 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000007a8) 2428 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 2429 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT 0 2430 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x) \ 2431 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK) 2432 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 2433 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 2434 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 2435 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 2436 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2437 do {\ 2438 HWIO_INTLOCK(); \ 2439 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \ 2440 HWIO_INTFREE();\ 2441 } while (0) 2442 2443 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2444 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2445 2446 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB //// 2447 2448 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000007ac) 2449 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000007ac) 2450 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 2451 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT 0 2452 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x) \ 2453 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK) 2454 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 2455 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 2456 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 2457 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 2458 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2459 do {\ 2460 HWIO_INTLOCK(); \ 2461 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \ 2462 HWIO_INTFREE();\ 2463 } while (0) 2464 2465 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2466 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2467 2468 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 2469 2470 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000007bc) 2471 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000007bc) 2472 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2473 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2474 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2475 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2476 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2477 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2478 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2479 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2480 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2481 do {\ 2482 HWIO_INTLOCK(); \ 2483 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2484 HWIO_INTFREE();\ 2485 } while (0) 2486 2487 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2488 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2489 2490 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2491 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2492 2493 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2494 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2495 2496 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 2497 2498 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000007c0) 2499 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000007c0) 2500 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2501 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2502 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2503 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2504 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2505 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2506 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2507 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2508 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2509 do {\ 2510 HWIO_INTLOCK(); \ 2511 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2512 HWIO_INTFREE();\ 2513 } while (0) 2514 2515 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2516 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2517 2518 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS //// 2519 2520 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000007c4) 2521 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000007c4) 2522 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2523 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 2524 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 2525 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK) 2526 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2527 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2528 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2529 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2530 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2531 do {\ 2532 HWIO_INTLOCK(); \ 2533 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 2534 HWIO_INTFREE();\ 2535 } while (0) 2536 2537 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2538 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2539 2540 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2541 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2542 2543 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2544 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2545 2546 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER //// 2547 2548 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000007c8) 2549 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000007c8) 2550 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2551 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2552 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2553 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2554 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2555 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2556 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2557 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2558 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2559 do {\ 2560 HWIO_INTLOCK(); \ 2561 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2562 HWIO_INTFREE();\ 2563 } while (0) 2564 2565 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2566 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2567 2568 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// 2569 2570 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000007cc) 2571 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000007cc) 2572 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2573 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2574 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2575 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2576 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2577 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2578 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2579 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2580 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2581 do {\ 2582 HWIO_INTLOCK(); \ 2583 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2584 HWIO_INTFREE();\ 2585 } while (0) 2586 2587 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2588 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2589 2590 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS //// 2591 2592 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000007d0) 2593 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000007d0) 2594 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 2595 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2596 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2597 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2598 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2599 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2600 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2601 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2602 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2603 do {\ 2604 HWIO_INTLOCK(); \ 2605 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2606 HWIO_INTFREE();\ 2607 } while (0) 2608 2609 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 2610 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 2611 2612 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 2613 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2614 2615 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB //// 2616 2617 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007d4) 2618 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007d4) 2619 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2620 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT 0 2621 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x) \ 2622 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK) 2623 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 2624 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 2625 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 2626 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 2627 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2628 do {\ 2629 HWIO_INTLOCK(); \ 2630 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 2631 HWIO_INTFREE();\ 2632 } while (0) 2633 2634 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2635 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2636 2637 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB //// 2638 2639 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007d8) 2640 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007d8) 2641 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2642 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT 0 2643 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x) \ 2644 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK) 2645 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 2646 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 2647 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 2648 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 2649 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2650 do {\ 2651 HWIO_INTLOCK(); \ 2652 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 2653 HWIO_INTFREE();\ 2654 } while (0) 2655 2656 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2657 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2658 2659 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2660 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2661 2662 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA //// 2663 2664 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x) (x+0x000007dc) 2665 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x) (x+0x000007dc) 2666 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK 0xffffffff 2667 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT 0 2668 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x) \ 2669 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK) 2670 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask) \ 2671 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) 2672 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val) \ 2673 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val) 2674 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 2675 do {\ 2676 HWIO_INTLOCK(); \ 2677 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \ 2678 HWIO_INTFREE();\ 2679 } while (0) 2680 2681 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2682 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 2683 2684 //// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET //// 2685 2686 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007e0) 2687 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007e0) 2688 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2689 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 2690 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 2691 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) 2692 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2693 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2694 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2695 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2696 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2697 do {\ 2698 HWIO_INTLOCK(); \ 2699 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 2700 HWIO_INTFREE();\ 2701 } while (0) 2702 2703 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2704 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2705 2706 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// 2707 2708 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000007e4) 2709 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000007e4) 2710 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 2711 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 2712 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ 2713 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) 2714 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ 2715 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 2716 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ 2717 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) 2718 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 2719 do {\ 2720 HWIO_INTLOCK(); \ 2721 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ 2722 HWIO_INTFREE();\ 2723 } while (0) 2724 2725 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2726 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2727 2728 //// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// 2729 2730 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000007e8) 2731 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000007e8) 2732 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 2733 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 2734 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ 2735 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) 2736 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ 2737 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 2738 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ 2739 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) 2740 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 2741 do {\ 2742 HWIO_INTLOCK(); \ 2743 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ 2744 HWIO_INTFREE();\ 2745 } while (0) 2746 2747 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2748 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2749 2750 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2751 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2752 2753 //// Register TCL_R0_FW2TCL1_RING_ID //// 2754 2755 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x000007ec) 2756 #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x000007ec) 2757 #define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff 2758 #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 2759 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ 2760 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) 2761 #define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ 2762 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 2763 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ 2764 out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) 2765 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ 2766 do {\ 2767 HWIO_INTLOCK(); \ 2768 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ 2769 HWIO_INTFREE();\ 2770 } while (0) 2771 2772 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2773 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 2774 2775 //// Register TCL_R0_FW2TCL1_RING_STATUS //// 2776 2777 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x000007f0) 2778 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x000007f0) 2779 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff 2780 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 2781 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ 2782 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) 2783 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ 2784 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 2785 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ 2786 out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) 2787 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 2788 do {\ 2789 HWIO_INTLOCK(); \ 2790 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ 2791 HWIO_INTFREE();\ 2792 } while (0) 2793 2794 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2795 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2796 2797 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2798 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2799 2800 //// Register TCL_R0_FW2TCL1_RING_MISC //// 2801 2802 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x000007f4) 2803 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x000007f4) 2804 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff 2805 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 2806 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ 2807 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) 2808 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ 2809 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 2810 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ 2811 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) 2812 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ 2813 do {\ 2814 HWIO_INTLOCK(); \ 2815 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ 2816 HWIO_INTFREE();\ 2817 } while (0) 2818 2819 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2820 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2821 2822 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2823 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2824 2825 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2826 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2827 2828 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2829 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2830 2831 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2832 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2833 2834 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2835 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2836 2837 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2838 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2839 2840 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2841 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2842 2843 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2844 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 2845 2846 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2847 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2848 2849 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2850 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2851 2852 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// 2853 2854 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000800) 2855 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000800) 2856 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 2857 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 2858 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 2859 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) 2860 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 2861 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 2862 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 2863 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 2864 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2865 do {\ 2866 HWIO_INTLOCK(); \ 2867 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 2868 HWIO_INTFREE();\ 2869 } while (0) 2870 2871 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2872 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2873 2874 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// 2875 2876 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000804) 2877 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000804) 2878 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 2879 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 2880 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 2881 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) 2882 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 2883 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 2884 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 2885 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 2886 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2887 do {\ 2888 HWIO_INTLOCK(); \ 2889 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 2890 HWIO_INTFREE();\ 2891 } while (0) 2892 2893 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2894 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2895 2896 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 2897 2898 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000814) 2899 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000814) 2900 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2901 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2902 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2903 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2904 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2905 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2906 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2907 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2908 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2909 do {\ 2910 HWIO_INTLOCK(); \ 2911 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2912 HWIO_INTFREE();\ 2913 } while (0) 2914 2915 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2916 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2917 2918 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2919 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2920 2921 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2922 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2923 2924 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 2925 2926 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000818) 2927 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000818) 2928 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2929 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2930 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2931 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2932 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2933 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2934 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2935 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2936 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2937 do {\ 2938 HWIO_INTLOCK(); \ 2939 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2940 HWIO_INTFREE();\ 2941 } while (0) 2942 2943 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2944 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2945 2946 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// 2947 2948 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000081c) 2949 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000081c) 2950 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2951 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 2952 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 2953 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 2954 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2955 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2956 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2957 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2958 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2959 do {\ 2960 HWIO_INTLOCK(); \ 2961 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 2962 HWIO_INTFREE();\ 2963 } while (0) 2964 2965 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2966 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2967 2968 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2969 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2970 2971 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2972 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2973 2974 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 2975 2976 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000820) 2977 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000820) 2978 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2979 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2980 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2981 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2982 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2983 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2984 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2985 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2986 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2987 do {\ 2988 HWIO_INTLOCK(); \ 2989 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2990 HWIO_INTFREE();\ 2991 } while (0) 2992 2993 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2994 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2995 2996 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 2997 2998 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000824) 2999 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000824) 3000 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3001 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3002 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3003 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3004 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3005 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3006 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3007 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3008 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3009 do {\ 3010 HWIO_INTLOCK(); \ 3011 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3012 HWIO_INTFREE();\ 3013 } while (0) 3014 3015 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3016 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3017 3018 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 3019 3020 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000828) 3021 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000828) 3022 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3023 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3024 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3025 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3026 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3027 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3028 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3029 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3030 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3031 do {\ 3032 HWIO_INTLOCK(); \ 3033 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3034 HWIO_INTFREE();\ 3035 } while (0) 3036 3037 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3038 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3039 3040 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3041 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3042 3043 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// 3044 3045 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000082c) 3046 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000082c) 3047 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3048 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 3049 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 3050 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) 3051 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3052 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3053 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3054 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 3055 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3056 do {\ 3057 HWIO_INTLOCK(); \ 3058 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 3059 HWIO_INTFREE();\ 3060 } while (0) 3061 3062 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3063 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3064 3065 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// 3066 3067 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000830) 3068 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000830) 3069 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3070 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 3071 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 3072 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) 3073 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3074 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3075 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3076 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 3077 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3078 do {\ 3079 HWIO_INTLOCK(); \ 3080 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 3081 HWIO_INTFREE();\ 3082 } while (0) 3083 3084 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3085 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3086 3087 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3088 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3089 3090 //// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// 3091 3092 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000834) 3093 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000834) 3094 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 3095 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 3096 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ 3097 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) 3098 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 3099 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 3100 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 3101 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) 3102 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3103 do {\ 3104 HWIO_INTLOCK(); \ 3105 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ 3106 HWIO_INTFREE();\ 3107 } while (0) 3108 3109 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3110 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 3111 3112 //// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// 3113 3114 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000838) 3115 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000838) 3116 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3117 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 3118 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 3119 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 3120 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3121 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3122 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3123 out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3124 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3125 do {\ 3126 HWIO_INTLOCK(); \ 3127 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3128 HWIO_INTFREE();\ 3129 } while (0) 3130 3131 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3132 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3133 3134 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// 3135 3136 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x0000083c) 3137 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x0000083c) 3138 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff 3139 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 3140 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ 3141 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) 3142 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ 3143 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 3144 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ 3145 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) 3146 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ 3147 do {\ 3148 HWIO_INTLOCK(); \ 3149 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ 3150 HWIO_INTFREE();\ 3151 } while (0) 3152 3153 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3154 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3155 3156 //// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// 3157 3158 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x00000840) 3159 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x00000840) 3160 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff 3161 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 3162 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ 3163 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) 3164 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ 3165 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 3166 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ 3167 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) 3168 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ 3169 do {\ 3170 HWIO_INTLOCK(); \ 3171 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ 3172 HWIO_INTFREE();\ 3173 } while (0) 3174 3175 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3176 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3177 3178 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3179 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3180 3181 //// Register TCL_R0_TCL2TQM_RING_ID //// 3182 3183 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000844) 3184 #define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000844) 3185 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff 3186 #define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 3187 #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ 3188 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) 3189 #define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ 3190 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 3191 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ 3192 out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) 3193 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ 3194 do {\ 3195 HWIO_INTLOCK(); \ 3196 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ 3197 HWIO_INTFREE();\ 3198 } while (0) 3199 3200 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 3201 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 3202 3203 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3204 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 3205 3206 //// Register TCL_R0_TCL2TQM_RING_STATUS //// 3207 3208 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000848) 3209 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000848) 3210 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff 3211 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 3212 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ 3213 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) 3214 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ 3215 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 3216 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ 3217 out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) 3218 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ 3219 do {\ 3220 HWIO_INTLOCK(); \ 3221 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ 3222 HWIO_INTFREE();\ 3223 } while (0) 3224 3225 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3226 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3227 3228 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3229 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3230 3231 //// Register TCL_R0_TCL2TQM_RING_MISC //// 3232 3233 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x0000084c) 3234 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x0000084c) 3235 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff 3236 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 3237 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ 3238 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) 3239 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ 3240 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 3241 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ 3242 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) 3243 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ 3244 do {\ 3245 HWIO_INTLOCK(); \ 3246 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ 3247 HWIO_INTFREE();\ 3248 } while (0) 3249 3250 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3251 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 0x16 3252 3253 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3254 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 0xe 3255 3256 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3257 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3258 3259 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3260 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3261 3262 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3263 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3264 3265 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3266 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 0x6 3267 3268 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3269 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3270 3271 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3272 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3273 3274 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3275 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3276 3277 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3278 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 3279 3280 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3281 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3282 3283 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3284 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3285 3286 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// 3287 3288 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000850) 3289 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000850) 3290 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff 3291 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 3292 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ 3293 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) 3294 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ 3295 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 3296 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ 3297 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) 3298 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3299 do {\ 3300 HWIO_INTLOCK(); \ 3301 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ 3302 HWIO_INTFREE();\ 3303 } while (0) 3304 3305 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3306 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3307 3308 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// 3309 3310 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000854) 3311 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000854) 3312 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff 3313 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 3314 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ 3315 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) 3316 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ 3317 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 3318 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ 3319 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) 3320 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3321 do {\ 3322 HWIO_INTLOCK(); \ 3323 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ 3324 HWIO_INTFREE();\ 3325 } while (0) 3326 3327 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3328 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3329 3330 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// 3331 3332 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000860) 3333 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000860) 3334 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3335 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 3336 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ 3337 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) 3338 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3339 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3340 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3341 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3342 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3343 do {\ 3344 HWIO_INTLOCK(); \ 3345 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ 3346 HWIO_INTFREE();\ 3347 } while (0) 3348 3349 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3350 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3351 3352 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3353 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3354 3355 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3356 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3357 3358 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// 3359 3360 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000864) 3361 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000864) 3362 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3363 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 3364 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ 3365 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) 3366 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3367 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3368 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3369 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3370 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3371 do {\ 3372 HWIO_INTLOCK(); \ 3373 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ 3374 HWIO_INTFREE();\ 3375 } while (0) 3376 3377 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3378 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3379 3380 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3381 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3382 3383 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3384 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3385 3386 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// 3387 3388 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000868) 3389 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000868) 3390 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3391 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 3392 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3393 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) 3394 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3395 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3396 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3397 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3398 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3399 do {\ 3400 HWIO_INTLOCK(); \ 3401 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3402 HWIO_INTFREE();\ 3403 } while (0) 3404 3405 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3406 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3407 3408 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// 3409 3410 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000890) 3411 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000890) 3412 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3413 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 3414 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ 3415 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) 3416 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3417 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3418 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3419 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3420 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3421 do {\ 3422 HWIO_INTLOCK(); \ 3423 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ 3424 HWIO_INTFREE();\ 3425 } while (0) 3426 3427 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3428 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3429 3430 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// 3431 3432 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x00000894) 3433 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x00000894) 3434 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff 3435 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 3436 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ 3437 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) 3438 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ 3439 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 3440 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ 3441 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) 3442 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ 3443 do {\ 3444 HWIO_INTLOCK(); \ 3445 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ 3446 HWIO_INTFREE();\ 3447 } while (0) 3448 3449 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3450 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3451 3452 //// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// 3453 3454 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x00000898) 3455 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x00000898) 3456 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff 3457 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 3458 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ 3459 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) 3460 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ 3461 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 3462 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ 3463 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) 3464 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ 3465 do {\ 3466 HWIO_INTLOCK(); \ 3467 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ 3468 HWIO_INTFREE();\ 3469 } while (0) 3470 3471 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3472 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3473 3474 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3475 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3476 3477 //// Register TCL_R0_TCL_STATUS1_RING_ID //// 3478 3479 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x0000089c) 3480 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x0000089c) 3481 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff 3482 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 3483 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ 3484 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) 3485 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ 3486 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 3487 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ 3488 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) 3489 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ 3490 do {\ 3491 HWIO_INTLOCK(); \ 3492 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ 3493 HWIO_INTFREE();\ 3494 } while (0) 3495 3496 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 3497 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 3498 3499 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3500 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 3501 3502 //// Register TCL_R0_TCL_STATUS1_RING_STATUS //// 3503 3504 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000008a0) 3505 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000008a0) 3506 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff 3507 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 3508 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ 3509 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) 3510 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ 3511 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 3512 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ 3513 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) 3514 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ 3515 do {\ 3516 HWIO_INTLOCK(); \ 3517 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ 3518 HWIO_INTFREE();\ 3519 } while (0) 3520 3521 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3522 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3523 3524 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3525 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3526 3527 //// Register TCL_R0_TCL_STATUS1_RING_MISC //// 3528 3529 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000008a4) 3530 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000008a4) 3531 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff 3532 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 3533 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ 3534 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) 3535 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ 3536 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 3537 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ 3538 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) 3539 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ 3540 do {\ 3541 HWIO_INTLOCK(); \ 3542 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ 3543 HWIO_INTFREE();\ 3544 } while (0) 3545 3546 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3547 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 0x16 3548 3549 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3550 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3551 3552 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3553 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3554 3555 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3556 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3557 3558 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3559 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3560 3561 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3562 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3563 3564 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3565 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3566 3567 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3568 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3569 3570 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3571 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3572 3573 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3574 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 3575 3576 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3577 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3578 3579 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3580 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3581 3582 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// 3583 3584 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008a8) 3585 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008a8) 3586 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff 3587 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 3588 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ 3589 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) 3590 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ 3591 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 3592 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ 3593 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) 3594 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3595 do {\ 3596 HWIO_INTLOCK(); \ 3597 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ 3598 HWIO_INTFREE();\ 3599 } while (0) 3600 3601 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3602 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3603 3604 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// 3605 3606 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008ac) 3607 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008ac) 3608 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff 3609 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 3610 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ 3611 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) 3612 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ 3613 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 3614 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ 3615 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) 3616 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3617 do {\ 3618 HWIO_INTLOCK(); \ 3619 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ 3620 HWIO_INTFREE();\ 3621 } while (0) 3622 3623 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3624 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3625 3626 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// 3627 3628 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008b8) 3629 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008b8) 3630 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3631 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 3632 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ 3633 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) 3634 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3635 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3636 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3637 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3638 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3639 do {\ 3640 HWIO_INTLOCK(); \ 3641 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ 3642 HWIO_INTFREE();\ 3643 } while (0) 3644 3645 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3646 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3647 3648 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3649 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3650 3651 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3652 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3653 3654 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// 3655 3656 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008bc) 3657 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008bc) 3658 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3659 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 3660 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ 3661 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) 3662 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3663 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3664 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3665 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3666 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3667 do {\ 3668 HWIO_INTLOCK(); \ 3669 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ 3670 HWIO_INTFREE();\ 3671 } while (0) 3672 3673 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3674 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3675 3676 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3677 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3678 3679 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3680 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3681 3682 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// 3683 3684 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008c0) 3685 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008c0) 3686 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3687 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3688 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3689 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) 3690 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3691 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3692 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3693 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3694 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3695 do {\ 3696 HWIO_INTLOCK(); \ 3697 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3698 HWIO_INTFREE();\ 3699 } while (0) 3700 3701 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3702 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3703 3704 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// 3705 3706 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008dc) 3707 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008dc) 3708 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3709 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 3710 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ 3711 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) 3712 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3713 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3714 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3715 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) 3716 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3717 do {\ 3718 HWIO_INTLOCK(); \ 3719 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ 3720 HWIO_INTFREE();\ 3721 } while (0) 3722 3723 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3724 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3725 3726 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// 3727 3728 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008e0) 3729 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008e0) 3730 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3731 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 3732 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ 3733 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) 3734 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3735 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3736 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3737 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) 3738 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3739 do {\ 3740 HWIO_INTLOCK(); \ 3741 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ 3742 HWIO_INTFREE();\ 3743 } while (0) 3744 3745 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3746 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3747 3748 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3749 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3750 3751 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// 3752 3753 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x000008e4) 3754 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x000008e4) 3755 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff 3756 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 3757 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ 3758 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) 3759 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ 3760 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 3761 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ 3762 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) 3763 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3764 do {\ 3765 HWIO_INTLOCK(); \ 3766 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ 3767 HWIO_INTFREE();\ 3768 } while (0) 3769 3770 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3771 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 3772 3773 //// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// 3774 3775 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008e8) 3776 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008e8) 3777 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3778 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 3779 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ 3780 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) 3781 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3782 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3783 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3784 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3785 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3786 do {\ 3787 HWIO_INTLOCK(); \ 3788 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3789 HWIO_INTFREE();\ 3790 } while (0) 3791 3792 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3793 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3794 3795 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// 3796 3797 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x000008ec) 3798 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x000008ec) 3799 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff 3800 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 3801 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ 3802 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) 3803 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ 3804 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 3805 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ 3806 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) 3807 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ 3808 do {\ 3809 HWIO_INTLOCK(); \ 3810 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ 3811 HWIO_INTFREE();\ 3812 } while (0) 3813 3814 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3815 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3816 3817 //// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// 3818 3819 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x000008f0) 3820 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x000008f0) 3821 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff 3822 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 3823 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ 3824 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) 3825 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ 3826 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 3827 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ 3828 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) 3829 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ 3830 do {\ 3831 HWIO_INTLOCK(); \ 3832 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ 3833 HWIO_INTFREE();\ 3834 } while (0) 3835 3836 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3837 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3838 3839 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3840 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3841 3842 //// Register TCL_R0_TCL_STATUS2_RING_ID //// 3843 3844 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x000008f4) 3845 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x000008f4) 3846 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff 3847 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 3848 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ 3849 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) 3850 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ 3851 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 3852 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ 3853 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) 3854 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ 3855 do {\ 3856 HWIO_INTLOCK(); \ 3857 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ 3858 HWIO_INTFREE();\ 3859 } while (0) 3860 3861 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 3862 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 3863 3864 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3865 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 3866 3867 //// Register TCL_R0_TCL_STATUS2_RING_STATUS //// 3868 3869 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x000008f8) 3870 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x000008f8) 3871 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff 3872 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 3873 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ 3874 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) 3875 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ 3876 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 3877 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ 3878 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) 3879 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ 3880 do {\ 3881 HWIO_INTLOCK(); \ 3882 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ 3883 HWIO_INTFREE();\ 3884 } while (0) 3885 3886 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3887 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3888 3889 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3890 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3891 3892 //// Register TCL_R0_TCL_STATUS2_RING_MISC //// 3893 3894 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x000008fc) 3895 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x000008fc) 3896 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff 3897 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 3898 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ 3899 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) 3900 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ 3901 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 3902 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ 3903 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) 3904 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ 3905 do {\ 3906 HWIO_INTLOCK(); \ 3907 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ 3908 HWIO_INTFREE();\ 3909 } while (0) 3910 3911 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3912 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_SHFT 0x16 3913 3914 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3915 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_SHFT 0xe 3916 3917 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3918 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3919 3920 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3921 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3922 3923 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3924 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3925 3926 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3927 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_SHFT 0x6 3928 3929 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3930 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3931 3932 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3933 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3934 3935 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3936 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3937 3938 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3939 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 3940 3941 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3942 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3943 3944 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3945 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3946 3947 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// 3948 3949 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000900) 3950 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000900) 3951 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff 3952 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 3953 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ 3954 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) 3955 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ 3956 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 3957 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ 3958 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) 3959 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3960 do {\ 3961 HWIO_INTLOCK(); \ 3962 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ 3963 HWIO_INTFREE();\ 3964 } while (0) 3965 3966 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3967 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3968 3969 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// 3970 3971 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000904) 3972 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000904) 3973 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff 3974 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 3975 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ 3976 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) 3977 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ 3978 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 3979 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ 3980 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) 3981 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3982 do {\ 3983 HWIO_INTLOCK(); \ 3984 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ 3985 HWIO_INTFREE();\ 3986 } while (0) 3987 3988 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3989 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3990 3991 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// 3992 3993 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000910) 3994 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000910) 3995 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3996 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 3997 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ 3998 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) 3999 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4000 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4001 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4002 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4003 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4004 do {\ 4005 HWIO_INTLOCK(); \ 4006 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ 4007 HWIO_INTFREE();\ 4008 } while (0) 4009 4010 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4011 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4012 4013 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4014 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4015 4016 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4017 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4018 4019 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// 4020 4021 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000914) 4022 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000914) 4023 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4024 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 4025 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ 4026 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) 4027 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4028 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4029 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4030 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4031 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4032 do {\ 4033 HWIO_INTLOCK(); \ 4034 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ 4035 HWIO_INTFREE();\ 4036 } while (0) 4037 4038 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4039 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4040 4041 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4042 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4043 4044 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4045 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4046 4047 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// 4048 4049 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000918) 4050 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000918) 4051 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4052 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 4053 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4054 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) 4055 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4056 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4057 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4058 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4059 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4060 do {\ 4061 HWIO_INTLOCK(); \ 4062 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4063 HWIO_INTFREE();\ 4064 } while (0) 4065 4066 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4067 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4068 4069 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// 4070 4071 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000934) 4072 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000934) 4073 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4074 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 4075 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ 4076 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) 4077 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ 4078 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 4079 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ 4080 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) 4081 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4082 do {\ 4083 HWIO_INTLOCK(); \ 4084 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ 4085 HWIO_INTFREE();\ 4086 } while (0) 4087 4088 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4089 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4090 4091 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// 4092 4093 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000938) 4094 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000938) 4095 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4096 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 4097 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ 4098 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) 4099 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ 4100 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 4101 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ 4102 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) 4103 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4104 do {\ 4105 HWIO_INTLOCK(); \ 4106 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ 4107 HWIO_INTFREE();\ 4108 } while (0) 4109 4110 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4111 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4112 4113 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4114 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4115 4116 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// 4117 4118 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x0000093c) 4119 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x0000093c) 4120 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff 4121 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 4122 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ 4123 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) 4124 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ 4125 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 4126 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ 4127 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) 4128 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ 4129 do {\ 4130 HWIO_INTLOCK(); \ 4131 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ 4132 HWIO_INTFREE();\ 4133 } while (0) 4134 4135 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4136 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 4137 4138 //// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// 4139 4140 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000940) 4141 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000940) 4142 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4143 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 4144 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ 4145 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) 4146 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4147 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4148 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4149 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4150 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4151 do {\ 4152 HWIO_INTLOCK(); \ 4153 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ 4154 HWIO_INTFREE();\ 4155 } while (0) 4156 4157 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4158 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4159 4160 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// 4161 4162 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000944) 4163 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000944) 4164 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff 4165 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 4166 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ 4167 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) 4168 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ 4169 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 4170 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ 4171 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) 4172 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4173 do {\ 4174 HWIO_INTLOCK(); \ 4175 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ 4176 HWIO_INTFREE();\ 4177 } while (0) 4178 4179 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4180 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4181 4182 //// Register TCL_R0_TCL2FW_RING_BASE_MSB //// 4183 4184 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000948) 4185 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000948) 4186 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff 4187 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 4188 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ 4189 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) 4190 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ 4191 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 4192 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ 4193 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) 4194 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4195 do {\ 4196 HWIO_INTLOCK(); \ 4197 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ 4198 HWIO_INTFREE();\ 4199 } while (0) 4200 4201 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4202 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4203 4204 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4205 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4206 4207 //// Register TCL_R0_TCL2FW_RING_ID //// 4208 4209 #define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x0000094c) 4210 #define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x0000094c) 4211 #define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff 4212 #define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 4213 #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ 4214 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) 4215 #define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ 4216 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 4217 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ 4218 out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) 4219 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ 4220 do {\ 4221 HWIO_INTLOCK(); \ 4222 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ 4223 HWIO_INTFREE();\ 4224 } while (0) 4225 4226 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4227 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 4228 4229 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4230 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4231 4232 //// Register TCL_R0_TCL2FW_RING_STATUS //// 4233 4234 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x00000950) 4235 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x00000950) 4236 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff 4237 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 4238 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ 4239 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) 4240 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ 4241 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 4242 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ 4243 out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) 4244 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ 4245 do {\ 4246 HWIO_INTLOCK(); \ 4247 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ 4248 HWIO_INTFREE();\ 4249 } while (0) 4250 4251 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4252 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4253 4254 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4255 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4256 4257 //// Register TCL_R0_TCL2FW_RING_MISC //// 4258 4259 #define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000954) 4260 #define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000954) 4261 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff 4262 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 4263 #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ 4264 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) 4265 #define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ 4266 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 4267 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ 4268 out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) 4269 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ 4270 do {\ 4271 HWIO_INTLOCK(); \ 4272 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ 4273 HWIO_INTFREE();\ 4274 } while (0) 4275 4276 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4277 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 0x16 4278 4279 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4280 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 4281 4282 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4283 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4284 4285 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4286 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4287 4288 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4289 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4290 4291 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4292 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 4293 4294 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4295 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4296 4297 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4298 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4299 4300 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4301 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4302 4303 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4304 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4305 4306 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4307 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4308 4309 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4310 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4311 4312 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// 4313 4314 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000958) 4315 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000958) 4316 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4317 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 4318 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ 4319 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) 4320 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4321 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4322 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4323 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4324 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4325 do {\ 4326 HWIO_INTLOCK(); \ 4327 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ 4328 HWIO_INTFREE();\ 4329 } while (0) 4330 4331 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4332 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4333 4334 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// 4335 4336 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000095c) 4337 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000095c) 4338 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4339 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 4340 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ 4341 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) 4342 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4343 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4344 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4345 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4346 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4347 do {\ 4348 HWIO_INTLOCK(); \ 4349 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ 4350 HWIO_INTFREE();\ 4351 } while (0) 4352 4353 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4354 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4355 4356 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// 4357 4358 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000968) 4359 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000968) 4360 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4361 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4362 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4363 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) 4364 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4365 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4366 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4367 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4368 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4369 do {\ 4370 HWIO_INTLOCK(); \ 4371 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4372 HWIO_INTFREE();\ 4373 } while (0) 4374 4375 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4376 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4377 4378 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4379 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4380 4381 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4382 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4383 4384 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// 4385 4386 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000096c) 4387 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000096c) 4388 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4389 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4390 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4391 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) 4392 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4393 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4394 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4395 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4396 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4397 do {\ 4398 HWIO_INTLOCK(); \ 4399 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4400 HWIO_INTFREE();\ 4401 } while (0) 4402 4403 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4404 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4405 4406 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4407 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4408 4409 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4410 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4411 4412 //// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// 4413 4414 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000970) 4415 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000970) 4416 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4417 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4418 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4419 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4420 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4421 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4422 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4423 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4424 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4425 do {\ 4426 HWIO_INTLOCK(); \ 4427 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4428 HWIO_INTFREE();\ 4429 } while (0) 4430 4431 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4432 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4433 4434 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// 4435 4436 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000998) 4437 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000998) 4438 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4439 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 4440 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 4441 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) 4442 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4443 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4444 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4445 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4446 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4447 do {\ 4448 HWIO_INTLOCK(); \ 4449 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 4450 HWIO_INTFREE();\ 4451 } while (0) 4452 4453 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4454 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4455 4456 //// Register TCL_R0_GXI_TESTBUS_LOWER //// 4457 4458 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x0000099c) 4459 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x0000099c) 4460 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 4461 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 4462 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ 4463 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) 4464 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 4465 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 4466 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 4467 out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 4468 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 4469 do {\ 4470 HWIO_INTLOCK(); \ 4471 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ 4472 HWIO_INTFREE();\ 4473 } while (0) 4474 4475 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 4476 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 4477 4478 //// Register TCL_R0_GXI_TESTBUS_UPPER //// 4479 4480 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000009a0) 4481 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000009a0) 4482 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 4483 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 4484 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ 4485 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) 4486 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 4487 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 4488 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 4489 out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 4490 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 4491 do {\ 4492 HWIO_INTLOCK(); \ 4493 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ 4494 HWIO_INTFREE();\ 4495 } while (0) 4496 4497 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 4498 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 4499 4500 //// Register TCL_R0_GXI_SM_STATES_IX_0 //// 4501 4502 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000009a4) 4503 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000009a4) 4504 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 4505 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 4506 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ 4507 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) 4508 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 4509 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 4510 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 4511 out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 4512 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 4513 do {\ 4514 HWIO_INTLOCK(); \ 4515 out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ 4516 HWIO_INTFREE();\ 4517 } while (0) 4518 4519 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 4520 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 4521 4522 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 4523 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 4524 4525 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 4526 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 4527 4528 //// Register TCL_R0_GXI_END_OF_TEST_CHECK //// 4529 4530 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000009a8) 4531 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000009a8) 4532 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 4533 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 4534 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 4535 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) 4536 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 4537 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 4538 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 4539 out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 4540 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 4541 do {\ 4542 HWIO_INTLOCK(); \ 4543 out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 4544 HWIO_INTFREE();\ 4545 } while (0) 4546 4547 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 4548 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 4549 4550 //// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// 4551 4552 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000009ac) 4553 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000009ac) 4554 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 4555 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 4556 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 4557 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 4558 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 4559 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 4560 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 4561 out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 4562 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 4563 do {\ 4564 HWIO_INTLOCK(); \ 4565 out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 4566 HWIO_INTFREE();\ 4567 } while (0) 4568 4569 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 4570 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 4571 4572 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 4573 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 4574 4575 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 4576 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 4577 4578 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 4579 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 4580 4581 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 4582 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 4583 4584 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 4585 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 4586 4587 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 4588 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 4589 4590 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 4591 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 4592 4593 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 4594 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 4595 4596 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 4597 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 4598 4599 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 4600 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 4601 4602 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 4603 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 4604 4605 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 4606 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 4607 4608 //// Register TCL_R0_GXI_GXI_ERR_INTS //// 4609 4610 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000009b0) 4611 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000009b0) 4612 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 4613 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 4614 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ 4615 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) 4616 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 4617 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 4618 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 4619 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 4620 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 4621 do {\ 4622 HWIO_INTLOCK(); \ 4623 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ 4624 HWIO_INTFREE();\ 4625 } while (0) 4626 4627 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 4628 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 4629 4630 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 4631 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 4632 4633 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 4634 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 4635 4636 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 4637 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 4638 4639 //// Register TCL_R0_GXI_GXI_ERR_STATS //// 4640 4641 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000009b4) 4642 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000009b4) 4643 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 4644 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 4645 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ 4646 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) 4647 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 4648 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 4649 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 4650 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 4651 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 4652 do {\ 4653 HWIO_INTLOCK(); \ 4654 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ 4655 HWIO_INTFREE();\ 4656 } while (0) 4657 4658 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 4659 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 4660 4661 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 4662 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 4663 4664 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 4665 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 4666 4667 //// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// 4668 4669 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000009b8) 4670 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000009b8) 4671 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 4672 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 4673 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 4674 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 4675 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 4676 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 4677 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 4678 out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 4679 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 4680 do {\ 4681 HWIO_INTLOCK(); \ 4682 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 4683 HWIO_INTFREE();\ 4684 } while (0) 4685 4686 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 4687 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 4688 4689 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4690 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 4691 4692 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 4693 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 4694 4695 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 4696 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 4697 4698 //// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// 4699 4700 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000009bc) 4701 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000009bc) 4702 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 4703 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 4704 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 4705 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 4706 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 4707 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 4708 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 4709 out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 4710 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 4711 do {\ 4712 HWIO_INTLOCK(); \ 4713 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 4714 HWIO_INTFREE();\ 4715 } while (0) 4716 4717 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 4718 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 4719 4720 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4721 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 4722 4723 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 4724 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 4725 4726 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 4727 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 4728 4729 //// Register TCL_R0_GXI_GXI_MISC_CONTROL //// 4730 4731 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000009c0) 4732 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000009c0) 4733 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 4734 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 4735 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 4736 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) 4737 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 4738 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 4739 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 4740 out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 4741 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 4742 do {\ 4743 HWIO_INTLOCK(); \ 4744 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 4745 HWIO_INTFREE();\ 4746 } while (0) 4747 4748 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 4749 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 4750 4751 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 4752 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 4753 4754 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 4755 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 4756 4757 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 4758 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 4759 4760 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 4761 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 4762 4763 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 4764 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 4765 4766 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 4767 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 4768 4769 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 4770 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 4771 4772 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 4773 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 4774 4775 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 4776 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 4777 4778 //// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// 4779 4780 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000009c4) 4781 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000009c4) 4782 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 4783 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 4784 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 4785 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) 4786 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 4787 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 4788 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 4789 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 4790 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 4791 do {\ 4792 HWIO_INTLOCK(); \ 4793 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 4794 HWIO_INTFREE();\ 4795 } while (0) 4796 4797 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 4798 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 4799 4800 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 4801 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 4802 4803 //// Register TCL_R0_GXI_GXI_WDOG_STATUS //// 4804 4805 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000009c8) 4806 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000009c8) 4807 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 4808 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 4809 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 4810 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) 4811 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 4812 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 4813 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 4814 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 4815 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 4816 do {\ 4817 HWIO_INTLOCK(); \ 4818 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 4819 HWIO_INTFREE();\ 4820 } while (0) 4821 4822 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 4823 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 4824 4825 //// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// 4826 4827 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000009cc) 4828 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000009cc) 4829 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 4830 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 4831 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 4832 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 4833 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 4834 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 4835 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 4836 out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 4837 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 4838 do {\ 4839 HWIO_INTLOCK(); \ 4840 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 4841 HWIO_INTFREE();\ 4842 } while (0) 4843 4844 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 4845 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 4846 4847 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 4848 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 4849 4850 //// Register TCL_R0_GXI_GXI_RD_LATENCY_CTRL //// 4851 4852 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x000009d0) 4853 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x000009d0) 4854 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 4855 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 4856 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ 4857 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) 4858 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 4859 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 4860 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 4861 out_dword( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) 4862 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 4863 do {\ 4864 HWIO_INTLOCK(); \ 4865 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ 4866 HWIO_INTFREE();\ 4867 } while (0) 4868 4869 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 4870 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 4871 4872 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 4873 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 4874 4875 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 4876 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 4877 4878 //// Register TCL_R0_GXI_GXI_WR_LATENCY_CTRL //// 4879 4880 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x000009d4) 4881 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x000009d4) 4882 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 4883 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 4884 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ 4885 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) 4886 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 4887 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 4888 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 4889 out_dword( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) 4890 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 4891 do {\ 4892 HWIO_INTLOCK(); \ 4893 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ 4894 HWIO_INTFREE();\ 4895 } while (0) 4896 4897 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 4898 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 4899 4900 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 4901 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 4902 4903 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 4904 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 4905 4906 //// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// 4907 4908 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x000009d8) 4909 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x000009d8) 4910 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 4911 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 4912 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ 4913 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) 4914 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ 4915 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 4916 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ 4917 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) 4918 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 4919 do {\ 4920 HWIO_INTLOCK(); \ 4921 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ 4922 HWIO_INTFREE();\ 4923 } while (0) 4924 4925 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 4926 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 4927 4928 //// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// 4929 4930 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x000009dc) 4931 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x000009dc) 4932 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 4933 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 4934 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ 4935 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) 4936 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 4937 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 4938 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 4939 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) 4940 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 4941 do {\ 4942 HWIO_INTLOCK(); \ 4943 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ 4944 HWIO_INTFREE();\ 4945 } while (0) 4946 4947 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 4948 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 4949 4950 //// Register TCL_R0_ASE_GST_SIZE //// 4951 4952 #define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x000009e0) 4953 #define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x000009e0) 4954 #define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff 4955 #define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 4956 #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ 4957 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) 4958 #define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ 4959 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 4960 #define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ 4961 out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) 4962 #define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ 4963 do {\ 4964 HWIO_INTLOCK(); \ 4965 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ 4966 HWIO_INTFREE();\ 4967 } while (0) 4968 4969 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff 4970 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 4971 4972 //// Register TCL_R0_ASE_SEARCH_CTRL //// 4973 4974 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x000009e4) 4975 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x000009e4) 4976 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff07ff 4977 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 4978 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ 4979 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) 4980 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ 4981 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 4982 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ 4983 out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) 4984 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ 4985 do {\ 4986 HWIO_INTLOCK(); \ 4987 out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ 4988 HWIO_INTFREE();\ 4989 } while (0) 4990 4991 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 4992 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 4993 4994 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400 4995 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa 4996 4997 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 4998 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 4999 5000 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5001 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5002 5003 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5004 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5005 5006 //// Register TCL_R0_ASE_WATCHDOG //// 5007 5008 #define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x000009e8) 5009 #define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x000009e8) 5010 #define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff 5011 #define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 5012 #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ 5013 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) 5014 #define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ 5015 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 5016 #define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ 5017 out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) 5018 #define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ 5019 do {\ 5020 HWIO_INTLOCK(); \ 5021 out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ 5022 HWIO_INTFREE();\ 5023 } while (0) 5024 5025 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 5026 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 5027 5028 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5029 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 5030 5031 //// Register TCL_R0_ASE_CLKGATE_DISABLE //// 5032 5033 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x000009ec) 5034 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x000009ec) 5035 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xfffff87f 5036 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 5037 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ 5038 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) 5039 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ 5040 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 5041 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ 5042 out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) 5043 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5044 do {\ 5045 HWIO_INTLOCK(); \ 5046 out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ 5047 HWIO_INTFREE();\ 5048 } while (0) 5049 5050 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5051 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5052 5053 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5054 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5055 5056 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffff800 5057 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0xb 5058 5059 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000040 5060 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 0x6 5061 5062 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x00000020 5063 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 0x5 5064 5065 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000010 5066 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x4 5067 5068 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000008 5069 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x3 5070 5071 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000004 5072 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x2 5073 5074 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5075 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5076 5077 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5078 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5079 5080 //// Register TCL_R0_ASE_WRITE_BACK_PENDING //// 5081 5082 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x000009f0) 5083 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x000009f0) 5084 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 5085 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 5086 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ 5087 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) 5088 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ 5089 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 5090 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ 5091 out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) 5092 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5093 do {\ 5094 HWIO_INTLOCK(); \ 5095 out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ 5096 HWIO_INTFREE();\ 5097 } while (0) 5098 5099 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5100 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5101 5102 //// Register TCL_R1_CACHE_FLUSH //// 5103 5104 #define HWIO_TCL_R1_CACHE_FLUSH_ADDR(x) (x+0x00001000) 5105 #define HWIO_TCL_R1_CACHE_FLUSH_PHYS(x) (x+0x00001000) 5106 #define HWIO_TCL_R1_CACHE_FLUSH_RMSK 0x00000003 5107 #define HWIO_TCL_R1_CACHE_FLUSH_SHFT 0 5108 #define HWIO_TCL_R1_CACHE_FLUSH_IN(x) \ 5109 in_dword_masked ( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), HWIO_TCL_R1_CACHE_FLUSH_RMSK) 5110 #define HWIO_TCL_R1_CACHE_FLUSH_INM(x, mask) \ 5111 in_dword_masked ( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), mask) 5112 #define HWIO_TCL_R1_CACHE_FLUSH_OUT(x, val) \ 5113 out_dword( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), val) 5114 #define HWIO_TCL_R1_CACHE_FLUSH_OUTM(x, mask, val) \ 5115 do {\ 5116 HWIO_INTLOCK(); \ 5117 out_dword_masked_ns(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), mask, val, HWIO_TCL_R1_CACHE_FLUSH_IN(x)); \ 5118 HWIO_INTFREE();\ 5119 } while (0) 5120 5121 #define HWIO_TCL_R1_CACHE_FLUSH_STATUS_BMSK 0x00000002 5122 #define HWIO_TCL_R1_CACHE_FLUSH_STATUS_SHFT 0x1 5123 5124 #define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_BMSK 0x00000001 5125 #define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_SHFT 0x0 5126 5127 //// Register TCL_R1_SM_STATES_IX_0 //// 5128 5129 #define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001004) 5130 #define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001004) 5131 #define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff 5132 #define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 5133 #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ 5134 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) 5135 #define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ 5136 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 5137 #define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ 5138 out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) 5139 #define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 5140 do {\ 5141 HWIO_INTLOCK(); \ 5142 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ 5143 HWIO_INTFREE();\ 5144 } while (0) 5145 5146 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 5147 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 5148 5149 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 5150 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 5151 5152 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 5153 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 5154 5155 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 5156 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf 5157 5158 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK 0x00007000 5159 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT 0xc 5160 5161 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 5162 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 5163 5164 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 5165 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 5166 5167 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 5168 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 5169 5170 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 5171 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 5172 5173 //// Register TCL_R1_SM_STATES_IX_1 //// 5174 5175 #define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001008) 5176 #define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001008) 5177 #define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x0003ffff 5178 #define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 5179 #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ 5180 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) 5181 #define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ 5182 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 5183 #define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ 5184 out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) 5185 #define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 5186 do {\ 5187 HWIO_INTLOCK(); \ 5188 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ 5189 HWIO_INTFREE();\ 5190 } while (0) 5191 5192 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x00038000 5193 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 0xf 5194 5195 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 5196 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc 5197 5198 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 5199 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 5200 5201 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 5202 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 5203 5204 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 5205 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 5206 5207 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 5208 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 5209 5210 //// Register TCL_R1_TESTBUS_CTRL_0 //// 5211 5212 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x0000100c) 5213 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x0000100c) 5214 #define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x3fffffff 5215 #define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 5216 #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ 5217 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) 5218 #define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ 5219 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 5220 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ 5221 out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) 5222 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ 5223 do {\ 5224 HWIO_INTLOCK(); \ 5225 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ 5226 HWIO_INTFREE();\ 5227 } while (0) 5228 5229 #define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x20000000 5230 #define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x1d 5231 5232 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 5233 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 5234 5235 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 5236 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 5237 5238 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 5239 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe 5240 5241 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 5242 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa 5243 5244 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 5245 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 5246 5247 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f 5248 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 5249 5250 //// Register TCL_R1_TESTBUS_LOW //// 5251 5252 #define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x00001010) 5253 #define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x00001010) 5254 #define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff 5255 #define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 5256 #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ 5257 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) 5258 #define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ 5259 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 5260 #define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ 5261 out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) 5262 #define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 5263 do {\ 5264 HWIO_INTLOCK(); \ 5265 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ 5266 HWIO_INTFREE();\ 5267 } while (0) 5268 5269 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 5270 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 5271 5272 //// Register TCL_R1_TESTBUS_HIGH //// 5273 5274 #define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001014) 5275 #define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001014) 5276 #define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff 5277 #define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 5278 #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ 5279 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) 5280 #define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ 5281 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 5282 #define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ 5283 out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) 5284 #define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 5285 do {\ 5286 HWIO_INTLOCK(); \ 5287 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ 5288 HWIO_INTFREE();\ 5289 } while (0) 5290 5291 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 5292 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 5293 5294 //// Register TCL_R1_EVENTMASK_IX_0 //// 5295 5296 #define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001018) 5297 #define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001018) 5298 #define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff 5299 #define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 5300 #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ 5301 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) 5302 #define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ 5303 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 5304 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ 5305 out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) 5306 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 5307 do {\ 5308 HWIO_INTLOCK(); \ 5309 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ 5310 HWIO_INTFREE();\ 5311 } while (0) 5312 5313 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff 5314 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 5315 5316 //// Register TCL_R1_EVENTMASK_IX_1 //// 5317 5318 #define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x0000101c) 5319 #define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x0000101c) 5320 #define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff 5321 #define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 5322 #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ 5323 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) 5324 #define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ 5325 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 5326 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ 5327 out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) 5328 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 5329 do {\ 5330 HWIO_INTLOCK(); \ 5331 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ 5332 HWIO_INTFREE();\ 5333 } while (0) 5334 5335 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff 5336 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 5337 5338 //// Register TCL_R1_EVENTMASK_IX_2 //// 5339 5340 #define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00001020) 5341 #define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00001020) 5342 #define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff 5343 #define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 5344 #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ 5345 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) 5346 #define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ 5347 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 5348 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ 5349 out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) 5350 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ 5351 do {\ 5352 HWIO_INTLOCK(); \ 5353 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ 5354 HWIO_INTFREE();\ 5355 } while (0) 5356 5357 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff 5358 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 5359 5360 //// Register TCL_R1_EVENTMASK_IX_3 //// 5361 5362 #define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001024) 5363 #define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001024) 5364 #define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff 5365 #define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 5366 #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ 5367 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) 5368 #define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ 5369 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 5370 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ 5371 out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) 5372 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ 5373 do {\ 5374 HWIO_INTLOCK(); \ 5375 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ 5376 HWIO_INTFREE();\ 5377 } while (0) 5378 5379 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff 5380 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 5381 5382 //// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// 5383 5384 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001028) 5385 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001028) 5386 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 5387 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 5388 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 5389 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 5390 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 5391 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 5392 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 5393 out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 5394 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 5395 do {\ 5396 HWIO_INTLOCK(); \ 5397 out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 5398 HWIO_INTFREE();\ 5399 } while (0) 5400 5401 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 5402 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 5403 5404 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 5405 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 5406 5407 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 5408 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 5409 5410 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 5411 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 5412 5413 //// Register TCL_R1_END_OF_TEST_CHECK //// 5414 5415 #define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x0000102c) 5416 #define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x0000102c) 5417 #define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 5418 #define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 5419 #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ 5420 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) 5421 #define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ 5422 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 5423 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ 5424 out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) 5425 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5426 do {\ 5427 HWIO_INTLOCK(); \ 5428 out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ 5429 HWIO_INTFREE();\ 5430 } while (0) 5431 5432 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5433 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5434 5435 //// Register TCL_R1_ASE_END_OF_TEST_CHECK //// 5436 5437 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x00001030) 5438 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x00001030) 5439 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 5440 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 5441 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ 5442 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) 5443 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ 5444 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 5445 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ 5446 out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) 5447 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5448 do {\ 5449 HWIO_INTLOCK(); \ 5450 out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ 5451 HWIO_INTFREE();\ 5452 } while (0) 5453 5454 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5455 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5456 5457 //// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// 5458 5459 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001034) 5460 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001034) 5461 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 5462 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 5463 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ 5464 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) 5465 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 5466 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 5467 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 5468 out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 5469 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 5470 do {\ 5471 HWIO_INTLOCK(); \ 5472 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 5473 HWIO_INTFREE();\ 5474 } while (0) 5475 5476 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 5477 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 5478 5479 //// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// 5480 5481 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001038) 5482 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001038) 5483 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 5484 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 5485 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 5486 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 5487 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 5488 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 5489 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 5490 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 5491 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 5492 do {\ 5493 HWIO_INTLOCK(); \ 5494 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 5495 HWIO_INTFREE();\ 5496 } while (0) 5497 5498 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 5499 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 5500 5501 //// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// 5502 5503 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x0000103c) 5504 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x0000103c) 5505 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 5506 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 5507 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 5508 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 5509 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 5510 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 5511 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 5512 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 5513 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 5514 do {\ 5515 HWIO_INTLOCK(); \ 5516 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 5517 HWIO_INTFREE();\ 5518 } while (0) 5519 5520 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 5521 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 5522 5523 //// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 5524 5525 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x00001040) 5526 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x00001040) 5527 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 5528 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 5529 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 5530 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 5531 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 5532 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 5533 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 5534 out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 5535 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 5536 do {\ 5537 HWIO_INTLOCK(); \ 5538 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 5539 HWIO_INTFREE();\ 5540 } while (0) 5541 5542 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 5543 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 5544 5545 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 5546 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 5547 5548 //// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// 5549 5550 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001044) 5551 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001044) 5552 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 5553 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 5554 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 5555 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 5556 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 5557 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 5558 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 5559 out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 5560 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 5561 do {\ 5562 HWIO_INTLOCK(); \ 5563 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 5564 HWIO_INTFREE();\ 5565 } while (0) 5566 5567 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 5568 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 5569 5570 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 5571 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 5572 5573 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 5574 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 5575 5576 //// Register TCL_R1_ASE_SM_STATES //// 5577 5578 #define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001048) 5579 #define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001048) 5580 #define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x00001fff 5581 #define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 5582 #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ 5583 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) 5584 #define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ 5585 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 5586 #define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ 5587 out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) 5588 #define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ 5589 do {\ 5590 HWIO_INTLOCK(); \ 5591 out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ 5592 HWIO_INTFREE();\ 5593 } while (0) 5594 5595 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00001800 5596 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0xb 5597 5598 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x00000600 5599 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x9 5600 5601 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00000180 5602 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x7 5603 5604 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00000070 5605 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0x4 5606 5607 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 5608 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 5609 5610 //// Register TCL_R1_ASE_CACHE_DEBUG //// 5611 5612 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x0000104c) 5613 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x0000104c) 5614 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff 5615 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 5616 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ 5617 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) 5618 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ 5619 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 5620 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ 5621 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) 5622 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ 5623 do {\ 5624 HWIO_INTLOCK(); \ 5625 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ 5626 HWIO_INTFREE();\ 5627 } while (0) 5628 5629 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 5630 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 5631 5632 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// 5633 5634 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x00001050) 5635 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x00001050) 5636 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 5637 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 5638 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 5639 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) 5640 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 5641 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 5642 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 5643 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 5644 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 5645 do {\ 5646 HWIO_INTLOCK(); \ 5647 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 5648 HWIO_INTFREE();\ 5649 } while (0) 5650 5651 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 5652 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 5653 5654 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 5655 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 5656 5657 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 5658 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 5659 5660 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 5661 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 5662 5663 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// 5664 5665 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1054+0x4*n) 5666 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1054+0x4*n) 5667 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 5668 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 5669 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 5670 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 5671 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) 5672 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 5673 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 5674 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 5675 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 5676 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 5677 do {\ 5678 HWIO_INTLOCK(); \ 5679 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 5680 HWIO_INTFREE();\ 5681 } while (0) 5682 5683 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 5684 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 5685 5686 //// Register TCL_R2_SW2TCL1_RING_HP //// 5687 5688 #define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) 5689 #define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) 5690 #define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x000fffff 5691 #define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 5692 #define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ 5693 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) 5694 #define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ 5695 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 5696 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ 5697 out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) 5698 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ 5699 do {\ 5700 HWIO_INTLOCK(); \ 5701 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ 5702 HWIO_INTFREE();\ 5703 } while (0) 5704 5705 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x000fffff 5706 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 5707 5708 //// Register TCL_R2_SW2TCL1_RING_TP //// 5709 5710 #define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) 5711 #define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) 5712 #define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x000fffff 5713 #define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 5714 #define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ 5715 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) 5716 #define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ 5717 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 5718 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ 5719 out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) 5720 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ 5721 do {\ 5722 HWIO_INTLOCK(); \ 5723 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ 5724 HWIO_INTFREE();\ 5725 } while (0) 5726 5727 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x000fffff 5728 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 5729 5730 //// Register TCL_R2_SW2TCL2_RING_HP //// 5731 5732 #define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) 5733 #define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) 5734 #define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x000fffff 5735 #define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 5736 #define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ 5737 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) 5738 #define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ 5739 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 5740 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ 5741 out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) 5742 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ 5743 do {\ 5744 HWIO_INTLOCK(); \ 5745 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ 5746 HWIO_INTFREE();\ 5747 } while (0) 5748 5749 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x000fffff 5750 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 5751 5752 //// Register TCL_R2_SW2TCL2_RING_TP //// 5753 5754 #define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) 5755 #define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) 5756 #define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x000fffff 5757 #define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 5758 #define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ 5759 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) 5760 #define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ 5761 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 5762 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ 5763 out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) 5764 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ 5765 do {\ 5766 HWIO_INTLOCK(); \ 5767 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ 5768 HWIO_INTFREE();\ 5769 } while (0) 5770 5771 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x000fffff 5772 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 5773 5774 //// Register TCL_R2_SW2TCL3_RING_HP //// 5775 5776 #define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) 5777 #define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) 5778 #define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x000fffff 5779 #define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 5780 #define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ 5781 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) 5782 #define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ 5783 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 5784 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ 5785 out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) 5786 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ 5787 do {\ 5788 HWIO_INTLOCK(); \ 5789 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ 5790 HWIO_INTFREE();\ 5791 } while (0) 5792 5793 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x000fffff 5794 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 5795 5796 //// Register TCL_R2_SW2TCL3_RING_TP //// 5797 5798 #define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) 5799 #define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) 5800 #define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x000fffff 5801 #define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 5802 #define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ 5803 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) 5804 #define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ 5805 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 5806 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ 5807 out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) 5808 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ 5809 do {\ 5810 HWIO_INTLOCK(); \ 5811 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ 5812 HWIO_INTFREE();\ 5813 } while (0) 5814 5815 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x000fffff 5816 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 5817 5818 //// Register TCL_R2_SW2TCL_CMD_RING_HP //// 5819 5820 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x) (x+0x00002018) 5821 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x) (x+0x00002018) 5822 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK 0x000fffff 5823 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT 0 5824 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x) \ 5825 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK) 5826 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask) \ 5827 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) 5828 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val) \ 5829 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val) 5830 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val) \ 5831 do {\ 5832 HWIO_INTLOCK(); \ 5833 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \ 5834 HWIO_INTFREE();\ 5835 } while (0) 5836 5837 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK 0x000fffff 5838 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT 0x0 5839 5840 //// Register TCL_R2_SW2TCL_CMD_RING_TP //// 5841 5842 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x) (x+0x0000201c) 5843 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x) (x+0x0000201c) 5844 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK 0x000fffff 5845 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT 0 5846 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x) \ 5847 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK) 5848 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask) \ 5849 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) 5850 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val) \ 5851 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val) 5852 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val) \ 5853 do {\ 5854 HWIO_INTLOCK(); \ 5855 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \ 5856 HWIO_INTFREE();\ 5857 } while (0) 5858 5859 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK 0x000fffff 5860 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT 0x0 5861 5862 //// Register TCL_R2_FW2TCL1_RING_HP //// 5863 5864 #define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) 5865 #define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) 5866 #define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff 5867 #define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 5868 #define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ 5869 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) 5870 #define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ 5871 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 5872 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ 5873 out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) 5874 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ 5875 do {\ 5876 HWIO_INTLOCK(); \ 5877 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ 5878 HWIO_INTFREE();\ 5879 } while (0) 5880 5881 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 5882 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 5883 5884 //// Register TCL_R2_FW2TCL1_RING_TP //// 5885 5886 #define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) 5887 #define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) 5888 #define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff 5889 #define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 5890 #define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ 5891 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) 5892 #define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ 5893 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 5894 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ 5895 out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) 5896 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ 5897 do {\ 5898 HWIO_INTLOCK(); \ 5899 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ 5900 HWIO_INTFREE();\ 5901 } while (0) 5902 5903 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 5904 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 5905 5906 //// Register TCL_R2_TCL2TQM_RING_HP //// 5907 5908 #define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) 5909 #define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) 5910 #define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff 5911 #define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 5912 #define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ 5913 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) 5914 #define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ 5915 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 5916 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ 5917 out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) 5918 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ 5919 do {\ 5920 HWIO_INTLOCK(); \ 5921 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ 5922 HWIO_INTFREE();\ 5923 } while (0) 5924 5925 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff 5926 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 5927 5928 //// Register TCL_R2_TCL2TQM_RING_TP //// 5929 5930 #define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) 5931 #define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) 5932 #define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff 5933 #define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 5934 #define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ 5935 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) 5936 #define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ 5937 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 5938 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ 5939 out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) 5940 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ 5941 do {\ 5942 HWIO_INTLOCK(); \ 5943 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ 5944 HWIO_INTFREE();\ 5945 } while (0) 5946 5947 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff 5948 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 5949 5950 //// Register TCL_R2_TCL_STATUS1_RING_HP //// 5951 5952 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) 5953 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) 5954 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff 5955 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 5956 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ 5957 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) 5958 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ 5959 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 5960 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ 5961 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) 5962 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ 5963 do {\ 5964 HWIO_INTLOCK(); \ 5965 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ 5966 HWIO_INTFREE();\ 5967 } while (0) 5968 5969 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 5970 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 5971 5972 //// Register TCL_R2_TCL_STATUS1_RING_TP //// 5973 5974 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) 5975 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) 5976 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff 5977 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 5978 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ 5979 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) 5980 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ 5981 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 5982 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ 5983 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) 5984 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ 5985 do {\ 5986 HWIO_INTLOCK(); \ 5987 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ 5988 HWIO_INTFREE();\ 5989 } while (0) 5990 5991 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 5992 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 5993 5994 //// Register TCL_R2_TCL_STATUS2_RING_HP //// 5995 5996 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) 5997 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) 5998 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff 5999 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 6000 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ 6001 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) 6002 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ 6003 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 6004 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ 6005 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) 6006 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ 6007 do {\ 6008 HWIO_INTLOCK(); \ 6009 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ 6010 HWIO_INTFREE();\ 6011 } while (0) 6012 6013 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6014 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 6015 6016 //// Register TCL_R2_TCL_STATUS2_RING_TP //// 6017 6018 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) 6019 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) 6020 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff 6021 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 6022 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ 6023 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) 6024 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ 6025 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 6026 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ 6027 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) 6028 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ 6029 do {\ 6030 HWIO_INTLOCK(); \ 6031 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ 6032 HWIO_INTFREE();\ 6033 } while (0) 6034 6035 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6036 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 6037 6038 //// Register TCL_R2_TCL2FW_RING_HP //// 6039 6040 #define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) 6041 #define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) 6042 #define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff 6043 #define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 6044 #define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ 6045 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) 6046 #define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ 6047 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 6048 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ 6049 out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) 6050 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ 6051 do {\ 6052 HWIO_INTLOCK(); \ 6053 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ 6054 HWIO_INTFREE();\ 6055 } while (0) 6056 6057 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6058 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 6059 6060 //// Register TCL_R2_TCL2FW_RING_TP //// 6061 6062 #define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) 6063 #define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) 6064 #define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff 6065 #define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 6066 #define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ 6067 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) 6068 #define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ 6069 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 6070 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ 6071 out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) 6072 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ 6073 do {\ 6074 HWIO_INTLOCK(); \ 6075 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ 6076 HWIO_INTFREE();\ 6077 } while (0) 6078 6079 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6080 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 6081 6082 6083 #endif 6084 6085