1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _PHYRX_PKT_END_INFO_H_ 20 #define _PHYRX_PKT_END_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "rx_location_info.h" 25 #include "rx_timing_offset_info.h" 26 #include "receive_rssi_info.h" 27 28 // ################ START SUMMARY ################# 29 // 30 // Dword Fields 31 // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27] 32 // 1 phy_timestamp_1_lower_32[31:0] 33 // 2 phy_timestamp_1_upper_32[31:0] 34 // 3 phy_timestamp_2_lower_32[31:0] 35 // 4 phy_timestamp_2_upper_32[31:0] 36 // 5-13 struct rx_location_info rx_location_info_details; 37 // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 38 // 15-30 struct receive_rssi_info post_rssi_info_details; 39 // 31 phy_sw_status_31_0[31:0] 40 // 32 phy_sw_status_63_32[31:0] 41 // 42 // ################ END SUMMARY ################# 43 44 #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 45 46 struct phyrx_pkt_end_info { 47 uint32_t phy_internal_nap : 1, //[0] 48 location_info_valid : 1, //[1] 49 timing_info_valid : 1, //[2] 50 rssi_info_valid : 1, //[3] 51 rx_frame_correction_needed : 1, //[4] 52 frameless_frame_received : 1, //[5] 53 reserved_0a : 6, //[11:6] 54 dl_ofdma_info_valid : 1, //[12] 55 dl_ofdma_ru_start_index : 7, //[19:13] 56 dl_ofdma_ru_width : 7, //[26:20] 57 reserved_0b : 5; //[31:27] 58 uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 59 uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 60 uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 61 uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 62 struct rx_location_info rx_location_info_details; 63 struct rx_timing_offset_info rx_timing_offset_info_details; 64 struct receive_rssi_info post_rssi_info_details; 65 uint32_t phy_sw_status_31_0 : 32; //[31:0] 66 uint32_t phy_sw_status_63_32 : 32; //[31:0] 67 }; 68 69 /* 70 71 phy_internal_nap 72 73 When set, PHY RX entered an internal NAP state, as PHY 74 determined that this reception was not destined to this 75 device 76 77 location_info_valid 78 79 Indicates that the RX_LOCATION_INFO structure later on 80 in the TLV contains valid info 81 82 timing_info_valid 83 84 Indicates that the RX_TIMING_OFFSET_INFO structure later 85 on in the TLV contains valid info 86 87 rssi_info_valid 88 89 Indicates that the RECEIVE_RSSI_INFO structure later on 90 in the TLV contains valid info 91 92 rx_frame_correction_needed 93 94 When clear, no action is needed in the MAC. 95 96 97 98 When set, the falling edge of the rx_frame happened 4us 99 too late. MAC will need to compensate for this delay in 100 order to maintain proper SIFS timing and/or not to get 101 de-slotted. 102 103 104 105 PHY uses this for very short 11a frames. 106 107 108 109 When set, PHY will have passed this TLV to the MAC up to 110 8 us into the 'real SIFS' time, and thus within 4us from the 111 falling edge of the rx_frame. 112 113 114 115 <legal all> 116 117 frameless_frame_received 118 119 When set, PHY has received the 'frameless frame' . Can 120 be used in the 'MU-RTS -CTS exchange where CTS reception can 121 be problematic. 122 123 <legal all> 124 125 reserved_0a 126 127 <legal 0> 128 129 dl_ofdma_info_valid 130 131 When set, the following DL_ofdma_... fields are valid. 132 133 It provides the MAC insight into which RU was allocated 134 to this device. 135 136 <legal all> 137 138 dl_ofdma_ru_start_index 139 140 RU index number to which User is assigned 141 142 RU numbering is over the entire BW, starting from 0 143 144 <legal 0-73> 145 146 dl_ofdma_ru_width 147 148 The size of the RU for this user. 149 150 In units of 1 (26 tone) RU 151 152 <legal 1-74> 153 154 reserved_0b 155 156 <legal 0> 157 158 phy_timestamp_1_lower_32 159 160 TODO PHY: cleanup descriptionThe PHY timestamp in the 161 AMPI of the first rising edge of rx_clear_pri after 162 TX_PHY_DESC. . This field should set to 0 by the PHY and 163 should be updated by the AMPI before being forwarded to the 164 rest of the MAC. This field indicates the lower 32 bits of 165 the timestamp 166 167 phy_timestamp_1_upper_32 168 169 TODO PHY: cleanup description 170 171 The PHY timestamp in the AMPI of the first rising edge 172 of rx_clear_pri after TX_PHY_DESC. This field should set to 173 0 by the PHY and should be updated by the AMPI before being 174 forwarded to the rest of the MAC. This field indicates the 175 upper 32 bits of the timestamp 176 177 phy_timestamp_2_lower_32 178 179 TODO PHY: cleanup description 180 181 The PHY timestamp in the AMPI of the rising edge of 182 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 183 0 by the PHY and should be updated by the AMPI before being 184 forwarded to the rest of the MAC. This field indicates the 185 lower 32 bits of the timestamp 186 187 phy_timestamp_2_upper_32 188 189 TODO PHY: cleanup description 190 191 The PHY timestamp in the AMPI of the rising edge of 192 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 193 0 by the PHY and should be updated by the AMPI before being 194 forwarded to the rest of the MAC. This field indicates the 195 upper 32 bits of the timestamp 196 197 struct rx_location_info rx_location_info_details 198 199 Overview of location related info 200 201 struct rx_timing_offset_info rx_timing_offset_info_details 202 203 Overview of timing offset related info 204 205 struct receive_rssi_info post_rssi_info_details 206 207 Overview of the post-RSSI values. 208 209 phy_sw_status_31_0 210 211 Some PHY micro code status that can be put in here. 212 Details of definition within SW specification 213 214 This field can be used for debugging, FW - SW message 215 exchange, etc. 216 217 It could for example be a pointer to a DDR memory 218 location where PHY FW put some debug info. 219 220 <legal all> 221 222 phy_sw_status_63_32 223 224 Some PHY micro code status that can be put in here. 225 Details of definition within SW specification 226 227 This field can be used for debugging, FW - SW message 228 exchange, etc. 229 230 It could for example be a pointer to a DDR memory 231 location where PHY FW put some debug info. 232 233 <legal all> 234 */ 235 236 237 /* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP 238 239 When set, PHY RX entered an internal NAP state, as PHY 240 determined that this reception was not destined to this 241 device 242 */ 243 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 244 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 245 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 246 247 /* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID 248 249 Indicates that the RX_LOCATION_INFO structure later on 250 in the TLV contains valid info 251 */ 252 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 253 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 254 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 255 256 /* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID 257 258 Indicates that the RX_TIMING_OFFSET_INFO structure later 259 on in the TLV contains valid info 260 */ 261 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 262 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 263 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 264 265 /* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID 266 267 Indicates that the RECEIVE_RSSI_INFO structure later on 268 in the TLV contains valid info 269 */ 270 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 271 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 272 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 273 274 /* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED 275 276 When clear, no action is needed in the MAC. 277 278 279 280 When set, the falling edge of the rx_frame happened 4us 281 too late. MAC will need to compensate for this delay in 282 order to maintain proper SIFS timing and/or not to get 283 de-slotted. 284 285 286 287 PHY uses this for very short 11a frames. 288 289 290 291 When set, PHY will have passed this TLV to the MAC up to 292 8 us into the 'real SIFS' time, and thus within 4us from the 293 falling edge of the rx_frame. 294 295 296 297 <legal all> 298 */ 299 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 300 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 301 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 302 303 /* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED 304 305 When set, PHY has received the 'frameless frame' . Can 306 be used in the 'MU-RTS -CTS exchange where CTS reception can 307 be problematic. 308 309 <legal all> 310 */ 311 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 312 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 313 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 314 315 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0A 316 317 <legal 0> 318 */ 319 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 320 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 321 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 322 323 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID 324 325 When set, the following DL_ofdma_... fields are valid. 326 327 It provides the MAC insight into which RU was allocated 328 to this device. 329 330 <legal all> 331 */ 332 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 333 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 334 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 335 336 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX 337 338 RU index number to which User is assigned 339 340 RU numbering is over the entire BW, starting from 0 341 342 <legal 0-73> 343 */ 344 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 345 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 346 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 347 348 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH 349 350 The size of the RU for this user. 351 352 In units of 1 (26 tone) RU 353 354 <legal 1-74> 355 */ 356 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 357 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 358 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 359 360 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0B 361 362 <legal 0> 363 */ 364 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 365 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 366 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 367 368 /* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 369 370 TODO PHY: cleanup descriptionThe PHY timestamp in the 371 AMPI of the first rising edge of rx_clear_pri after 372 TX_PHY_DESC. . This field should set to 0 by the PHY and 373 should be updated by the AMPI before being forwarded to the 374 rest of the MAC. This field indicates the lower 32 bits of 375 the timestamp 376 */ 377 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 378 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 379 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 380 381 /* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 382 383 TODO PHY: cleanup description 384 385 The PHY timestamp in the AMPI of the first rising edge 386 of rx_clear_pri after TX_PHY_DESC. This field should set to 387 0 by the PHY and should be updated by the AMPI before being 388 forwarded to the rest of the MAC. This field indicates the 389 upper 32 bits of the timestamp 390 */ 391 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 392 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 393 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 394 395 /* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 396 397 TODO PHY: cleanup description 398 399 The PHY timestamp in the AMPI of the rising edge of 400 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 401 0 by the PHY and should be updated by the AMPI before being 402 forwarded to the rest of the MAC. This field indicates the 403 lower 32 bits of the timestamp 404 */ 405 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 406 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 407 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 408 409 /* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 410 411 TODO PHY: cleanup description 412 413 The PHY timestamp in the AMPI of the rising edge of 414 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 415 0 by the PHY and should be updated by the AMPI before being 416 forwarded to the rest of the MAC. This field indicates the 417 upper 32 bits of the timestamp 418 */ 419 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 420 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 421 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 422 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000014 423 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 424 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 425 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000018 426 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 427 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 428 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000001c 429 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 430 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 431 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000020 432 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 433 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 434 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000024 435 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 436 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 437 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000028 438 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 439 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 440 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000002c 441 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 442 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 443 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000030 444 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 445 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 446 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000034 447 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 448 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 449 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_OFFSET 0x00000038 450 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_LSB 0 451 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_MASK 0xffffffff 452 #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000003c 453 #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 454 #define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 455 #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000040 456 #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 457 #define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 458 #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000044 459 #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 460 #define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 461 #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000048 462 #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 463 #define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 464 #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000004c 465 #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 466 #define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 467 #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000050 468 #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 469 #define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 470 #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000054 471 #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 472 #define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 473 #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000058 474 #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 475 #define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 476 #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000005c 477 #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 478 #define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 479 #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000060 480 #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 481 #define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 482 #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000064 483 #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 484 #define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 485 #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000068 486 #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 487 #define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 488 #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000006c 489 #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 490 #define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 491 #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000070 492 #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 493 #define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 494 #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000074 495 #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 496 #define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 497 #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000078 498 #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 499 #define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 500 501 /* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 502 503 Some PHY micro code status that can be put in here. 504 Details of definition within SW specification 505 506 This field can be used for debugging, FW - SW message 507 exchange, etc. 508 509 It could for example be a pointer to a DDR memory 510 location where PHY FW put some debug info. 511 512 <legal all> 513 */ 514 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 515 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 516 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 517 518 /* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 519 520 Some PHY micro code status that can be put in here. 521 Details of definition within SW specification 522 523 This field can be used for debugging, FW - SW message 524 exchange, etc. 525 526 It could for example be a pointer to a DDR memory 527 location where PHY FW put some debug info. 528 529 <legal all> 530 */ 531 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 532 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 533 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 534 535 536 #endif // _PHYRX_PKT_END_INFO_H_ 537