1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REO_FLUSH_CACHE_H_ 20 #define _REO_FLUSH_CACHE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_cmd_header.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0 struct uniform_reo_cmd_header cmd_header; 30 // 1 flush_addr_31_0[31:0] 31 // 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15] 32 // 3 reserved_3a[31:0] 33 // 4 reserved_4a[31:0] 34 // 5 reserved_5a[31:0] 35 // 6 reserved_6a[31:0] 36 // 7 reserved_7a[31:0] 37 // 8 reserved_8a[31:0] 38 // 39 // ################ END SUMMARY ################# 40 41 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 42 43 struct reo_flush_cache { 44 struct uniform_reo_cmd_header cmd_header; 45 uint32_t flush_addr_31_0 : 32; //[31:0] 46 uint32_t flush_addr_39_32 : 8, //[7:0] 47 forward_all_mpdus_in_queue : 1, //[8] 48 release_cache_block_index : 1, //[9] 49 cache_block_resource_index : 2, //[11:10] 50 flush_without_invalidate : 1, //[12] 51 block_cache_usage_after_flush : 1, //[13] 52 flush_entire_cache : 1, //[14] 53 reserved_2b : 17; //[31:15] 54 uint32_t reserved_3a : 32; //[31:0] 55 uint32_t reserved_4a : 32; //[31:0] 56 uint32_t reserved_5a : 32; //[31:0] 57 uint32_t reserved_6a : 32; //[31:0] 58 uint32_t reserved_7a : 32; //[31:0] 59 uint32_t reserved_8a : 32; //[31:0] 60 }; 61 62 /* 63 64 struct uniform_reo_cmd_header cmd_header 65 66 Consumer: REO 67 68 Producer: SW 69 70 71 72 Details for command execution tracking purposes. 73 74 flush_addr_31_0 75 76 Consumer: REO 77 78 Producer: SW 79 80 81 82 Address (lower 32 bits) of the descriptor to flush 83 84 <legal all> 85 86 flush_addr_39_32 87 88 Consumer: REO 89 90 Producer: SW 91 92 93 94 Address (upper 8 bits) of the descriptor to flush 95 96 <legal all> 97 98 forward_all_mpdus_in_queue 99 100 Is only allowed to be set when the flush address 101 corresponds with a REO descriptor. 102 103 104 105 When set, REO shall first forward all the MPDUs held in 106 the indicated re-order queue, before flushing the descriptor 107 from the cache. 108 109 <legal all> 110 111 release_cache_block_index 112 113 Field not valid when Flush_entire_cache is set. 114 115 116 117 If SW has previously used a blocking resource that it 118 now wants to re-use for this command, this bit shall be set. 119 It prevents SW from having to send a separate 120 REO_UNBLOCK_CACHE command. 121 122 123 124 When set, HW will first release the blocking resource 125 (indicated in field 'Cache_block_resouce_index') before this 126 command gets executed. 127 128 If that resource was already unblocked, this will be 129 considered an error. This command will not be executed, and 130 an error shall be returned. 131 132 <legal all> 133 134 cache_block_resource_index 135 136 Field not valid when Flush_entire_cache is set. 137 138 139 140 Indicates which of the four blocking resources in REO 141 will be assigned for managing the blocking of this 142 (descriptor) address 143 144 <legal all> 145 146 flush_without_invalidate 147 148 Field not valid when Flush_entire_cache is set. 149 150 151 152 When set, REO shall flush the cache line contents from 153 the cache, but there is NO need to invalidate the cache line 154 entry... The contents in the cache can be maintained. This 155 feature can be used by SW (and DV) to get a current snapshot 156 of the contents in the cache 157 158 159 160 <legal all> 161 162 block_cache_usage_after_flush 163 164 Field not valid when Flush_entire_cache is set. 165 166 167 168 When set, REO shall block any cache accesses to this 169 address till explicitly unblocked. 170 171 172 173 Whenever SW sets this bit, SW shall also set bit 174 'Forward_all_mpdus_in_queue' to ensure all packets are 175 flushed out in order to make sure this queue desc is not in 176 one of the aging link lists. In case SW does not want to 177 flush the MPDUs in the queue, see the recipe description 178 below this TLV definition. 179 180 181 182 The 'blocking' index to be used for this is indicated in 183 field 'cache_block_resource_index'. If SW had previously 184 used this blocking resource and was not freed up yet, SW 185 shall first unblock that index (by setting bit 186 Release_cache_block_index) or use an unblock command. 187 188 189 190 If the resource indicated here was already blocked (and 191 did not get unblocked in this command), it is considered an 192 error scenario... 193 194 No flush shall happen. The status for this command shall 195 indicate error. 196 197 198 199 <legal all> 200 201 flush_entire_cache 202 203 When set, the entire cache shall be flushed. The entire 204 cache will also remain blocked, till the 205 'REO_UNBLOCK_COMMAND' is received with bit unblock type set 206 to unblock_cache. All other fields in this command are to be 207 ignored. 208 209 210 211 Note that flushing the entire cache has no changes to 212 the current settings of the blocking resource settings 213 214 215 216 <legal all> 217 218 reserved_2b 219 220 <legal 0> 221 222 reserved_3a 223 224 <legal 0> 225 226 reserved_4a 227 228 <legal 0> 229 230 reserved_5a 231 232 <legal 0> 233 234 reserved_6a 235 236 <legal 0> 237 238 reserved_7a 239 240 <legal 0> 241 242 reserved_8a 243 244 <legal 0> 245 */ 246 247 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000 248 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0 249 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff 250 251 /* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0 252 253 Consumer: REO 254 255 Producer: SW 256 257 258 259 Address (lower 32 bits) of the descriptor to flush 260 261 <legal all> 262 */ 263 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 264 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 265 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff 266 267 /* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32 268 269 Consumer: REO 270 271 Producer: SW 272 273 274 275 Address (upper 8 bits) of the descriptor to flush 276 277 <legal all> 278 */ 279 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 280 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 281 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff 282 283 /* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE 284 285 Is only allowed to be set when the flush address 286 corresponds with a REO descriptor. 287 288 289 290 When set, REO shall first forward all the MPDUs held in 291 the indicated re-order queue, before flushing the descriptor 292 from the cache. 293 294 <legal all> 295 */ 296 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 297 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 298 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 299 300 /* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX 301 302 Field not valid when Flush_entire_cache is set. 303 304 305 306 If SW has previously used a blocking resource that it 307 now wants to re-use for this command, this bit shall be set. 308 It prevents SW from having to send a separate 309 REO_UNBLOCK_CACHE command. 310 311 312 313 When set, HW will first release the blocking resource 314 (indicated in field 'Cache_block_resouce_index') before this 315 command gets executed. 316 317 If that resource was already unblocked, this will be 318 considered an error. This command will not be executed, and 319 an error shall be returned. 320 321 <legal all> 322 */ 323 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 324 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 325 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 326 327 /* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX 328 329 Field not valid when Flush_entire_cache is set. 330 331 332 333 Indicates which of the four blocking resources in REO 334 will be assigned for managing the blocking of this 335 (descriptor) address 336 337 <legal all> 338 */ 339 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 340 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 341 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 342 343 /* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE 344 345 Field not valid when Flush_entire_cache is set. 346 347 348 349 When set, REO shall flush the cache line contents from 350 the cache, but there is NO need to invalidate the cache line 351 entry... The contents in the cache can be maintained. This 352 feature can be used by SW (and DV) to get a current snapshot 353 of the contents in the cache 354 355 356 357 <legal all> 358 */ 359 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 360 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 361 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 362 363 /* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH 364 365 Field not valid when Flush_entire_cache is set. 366 367 368 369 When set, REO shall block any cache accesses to this 370 address till explicitly unblocked. 371 372 373 374 Whenever SW sets this bit, SW shall also set bit 375 'Forward_all_mpdus_in_queue' to ensure all packets are 376 flushed out in order to make sure this queue desc is not in 377 one of the aging link lists. In case SW does not want to 378 flush the MPDUs in the queue, see the recipe description 379 below this TLV definition. 380 381 382 383 The 'blocking' index to be used for this is indicated in 384 field 'cache_block_resource_index'. If SW had previously 385 used this blocking resource and was not freed up yet, SW 386 shall first unblock that index (by setting bit 387 Release_cache_block_index) or use an unblock command. 388 389 390 391 If the resource indicated here was already blocked (and 392 did not get unblocked in this command), it is considered an 393 error scenario... 394 395 No flush shall happen. The status for this command shall 396 indicate error. 397 398 399 400 <legal all> 401 */ 402 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 403 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 404 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 405 406 /* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE 407 408 When set, the entire cache shall be flushed. The entire 409 cache will also remain blocked, till the 410 'REO_UNBLOCK_COMMAND' is received with bit unblock type set 411 to unblock_cache. All other fields in this command are to be 412 ignored. 413 414 415 416 Note that flushing the entire cache has no changes to 417 the current settings of the blocking resource settings 418 419 420 421 <legal all> 422 */ 423 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 424 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 425 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 426 427 /* Description REO_FLUSH_CACHE_2_RESERVED_2B 428 429 <legal 0> 430 */ 431 #define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 432 #define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 433 #define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 434 435 /* Description REO_FLUSH_CACHE_3_RESERVED_3A 436 437 <legal 0> 438 */ 439 #define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c 440 #define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 441 #define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff 442 443 /* Description REO_FLUSH_CACHE_4_RESERVED_4A 444 445 <legal 0> 446 */ 447 #define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 448 #define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 449 #define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff 450 451 /* Description REO_FLUSH_CACHE_5_RESERVED_5A 452 453 <legal 0> 454 */ 455 #define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 456 #define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 457 #define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff 458 459 /* Description REO_FLUSH_CACHE_6_RESERVED_6A 460 461 <legal 0> 462 */ 463 #define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 464 #define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 465 #define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff 466 467 /* Description REO_FLUSH_CACHE_7_RESERVED_7A 468 469 <legal 0> 470 */ 471 #define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c 472 #define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 473 #define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff 474 475 /* Description REO_FLUSH_CACHE_8_RESERVED_8A 476 477 <legal 0> 478 */ 479 #define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 480 #define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 481 #define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff 482 483 484 #endif // _REO_FLUSH_CACHE_H_ 485