1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _RX_MSDU_END_H_ 20 #define _RX_MSDU_END_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 29 // 1 ip_hdr_chksum[15:0], tcp_udp_chksum[31:16] 30 // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16] 31 // 3 ext_wapi_pn_95_64[31:0] 32 // 4 ext_wapi_pn_127_96[31:0] 33 // 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], reserved_5a[31:28] 34 // 6 ipv6_options_crc[31:0] 35 // 7 tcp_seq_number[31:0] 36 // 8 tcp_ack_number[31:0] 37 // 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] 38 // 10 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_10a[15:14], l3_type[31:16] 39 // 11 rule_indication_31_0[31:0] 40 // 12 rule_indication_63_32[31:0] 41 // 13 sa_idx[15:0], da_idx_or_sw_peer_id[31:16] 42 // 14 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26] 43 // 15 fse_metadata[31:0] 44 // 16 cce_metadata[15:0], sa_sw_peer_id[31:16] 45 // 46 // ################ END SUMMARY ################# 47 48 #define NUM_OF_DWORDS_RX_MSDU_END 17 49 50 struct rx_msdu_end { 51 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 52 sw_frame_group_id : 7, //[8:2] 53 reserved_0 : 7, //[15:9] 54 phy_ppdu_id : 16; //[31:16] 55 uint32_t ip_hdr_chksum : 16, //[15:0] 56 tcp_udp_chksum : 16; //[31:16] 57 uint32_t key_id_octet : 8, //[7:0] 58 cce_super_rule : 6, //[13:8] 59 cce_classify_not_done_truncate : 1, //[14] 60 cce_classify_not_done_cce_dis : 1, //[15] 61 ext_wapi_pn_63_48 : 16; //[31:16] 62 uint32_t ext_wapi_pn_95_64 : 32; //[31:0] 63 uint32_t ext_wapi_pn_127_96 : 32; //[31:0] 64 uint32_t reported_mpdu_length : 14, //[13:0] 65 first_msdu : 1, //[14] 66 last_msdu : 1, //[15] 67 sa_idx_timeout : 1, //[16] 68 da_idx_timeout : 1, //[17] 69 msdu_limit_error : 1, //[18] 70 flow_idx_timeout : 1, //[19] 71 flow_idx_invalid : 1, //[20] 72 wifi_parser_error : 1, //[21] 73 amsdu_parser_error : 1, //[22] 74 sa_is_valid : 1, //[23] 75 da_is_valid : 1, //[24] 76 da_is_mcbc : 1, //[25] 77 l3_header_padding : 2, //[27:26] 78 reserved_5a : 4; //[31:28] 79 uint32_t ipv6_options_crc : 32; //[31:0] 80 uint32_t tcp_seq_number : 32; //[31:0] 81 uint32_t tcp_ack_number : 32; //[31:0] 82 uint32_t tcp_flag : 9, //[8:0] 83 lro_eligible : 1, //[9] 84 reserved_9a : 6, //[15:10] 85 window_size : 16; //[31:16] 86 uint32_t da_offset : 6, //[5:0] 87 sa_offset : 6, //[11:6] 88 da_offset_valid : 1, //[12] 89 sa_offset_valid : 1, //[13] 90 reserved_10a : 2, //[15:14] 91 l3_type : 16; //[31:16] 92 uint32_t rule_indication_31_0 : 32; //[31:0] 93 uint32_t rule_indication_63_32 : 32; //[31:0] 94 uint32_t sa_idx : 16, //[15:0] 95 da_idx_or_sw_peer_id : 16; //[31:16] 96 uint32_t msdu_drop : 1, //[0] 97 reo_destination_indication : 5, //[5:1] 98 flow_idx : 20, //[25:6] 99 reserved_14 : 6; //[31:26] 100 uint32_t fse_metadata : 32; //[31:0] 101 uint32_t cce_metadata : 16, //[15:0] 102 sa_sw_peer_id : 16; //[31:16] 103 }; 104 105 /* 106 107 rxpcu_mpdu_filter_in_category 108 109 Field indicates what the reason was that this MPDU frame 110 was allowed to come into the receive path by RXPCU 111 112 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 113 frame filter programming of rxpcu 114 115 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 116 regular frame filter and would have been dropped, were it 117 not for the frame fitting into the 'monitor_client' 118 category. 119 120 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 121 regular frame filter and also did not pass the 122 rxpcu_monitor_client filter. It would have been dropped 123 accept that it did pass the 'monitor_other' category. 124 125 <legal 0-2> 126 127 sw_frame_group_id 128 129 SW processes frames based on certain classifications. 130 This field indicates to what sw classification this MPDU is 131 mapped. 132 133 The classification is given in priority order 134 135 136 137 <enum 0 sw_frame_group_NDP_frame> 138 139 140 141 <enum 1 sw_frame_group_Multicast_data> 142 143 <enum 2 sw_frame_group_Unicast_data> 144 145 <enum 3 sw_frame_group_Null_data > This includes mpdus 146 of type Data Null as well as QoS Data Null 147 148 149 150 <enum 4 sw_frame_group_mgmt_0000 > 151 152 <enum 5 sw_frame_group_mgmt_0001 > 153 154 <enum 6 sw_frame_group_mgmt_0010 > 155 156 <enum 7 sw_frame_group_mgmt_0011 > 157 158 <enum 8 sw_frame_group_mgmt_0100 > 159 160 <enum 9 sw_frame_group_mgmt_0101 > 161 162 <enum 10 sw_frame_group_mgmt_0110 > 163 164 <enum 11 sw_frame_group_mgmt_0111 > 165 166 <enum 12 sw_frame_group_mgmt_1000 > 167 168 <enum 13 sw_frame_group_mgmt_1001 > 169 170 <enum 14 sw_frame_group_mgmt_1010 > 171 172 <enum 15 sw_frame_group_mgmt_1011 > 173 174 <enum 16 sw_frame_group_mgmt_1100 > 175 176 <enum 17 sw_frame_group_mgmt_1101 > 177 178 <enum 18 sw_frame_group_mgmt_1110 > 179 180 <enum 19 sw_frame_group_mgmt_1111 > 181 182 183 184 <enum 20 sw_frame_group_ctrl_0000 > 185 186 <enum 21 sw_frame_group_ctrl_0001 > 187 188 <enum 22 sw_frame_group_ctrl_0010 > 189 190 <enum 23 sw_frame_group_ctrl_0011 > 191 192 <enum 24 sw_frame_group_ctrl_0100 > 193 194 <enum 25 sw_frame_group_ctrl_0101 > 195 196 <enum 26 sw_frame_group_ctrl_0110 > 197 198 <enum 27 sw_frame_group_ctrl_0111 > 199 200 <enum 28 sw_frame_group_ctrl_1000 > 201 202 <enum 29 sw_frame_group_ctrl_1001 > 203 204 <enum 30 sw_frame_group_ctrl_1010 > 205 206 <enum 31 sw_frame_group_ctrl_1011 > 207 208 <enum 32 sw_frame_group_ctrl_1100 > 209 210 <enum 33 sw_frame_group_ctrl_1101 > 211 212 <enum 34 sw_frame_group_ctrl_1110 > 213 214 <enum 35 sw_frame_group_ctrl_1111 > 215 216 217 218 <enum 36 sw_frame_group_unsupported> This covers type 3 219 and protocol version != 0 220 221 222 223 224 225 226 <legal 0-37> 227 228 reserved_0 229 230 <legal 0> 231 232 phy_ppdu_id 233 234 A ppdu counter value that PHY increments for every PPDU 235 received. The counter value wraps around 236 237 <legal all> 238 239 ip_hdr_chksum 240 241 This can include the IP header checksum or the pseudo 242 header checksum used by TCP/UDP checksum. 243 244 (with the first byte in the MSB and the second byte in 245 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 246 w.r.t. the byte order in a packet) 247 248 tcp_udp_chksum 249 250 The value of the computed TCP/UDP checksum. A mode bit 251 selects whether this checksum is the full checksum or the 252 partial checksum which does not include the pseudo header. 253 (with the first byte in the MSB and the second byte in the 254 LSB, i.e. requiring a byte-swap for little-endian FW/SW 255 w.r.t. the byte order in a packet) 256 257 key_id_octet 258 259 The key ID octet from the IV. Only valid when 260 first_msdu is set. 261 262 cce_super_rule 263 264 Indicates the super filter rule 265 266 cce_classify_not_done_truncate 267 268 Classification failed due to truncated frame 269 270 cce_classify_not_done_cce_dis 271 272 Classification failed due to CCE global disable 273 274 ext_wapi_pn_63_48 275 276 Extension PN (packet number) which is only used by WAPI. 277 This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 278 The WAPI PN bits [63:0] are in the pn field of the 279 rx_mpdu_start descriptor. 280 281 ext_wapi_pn_95_64 282 283 Extension PN (packet number) which is only used by WAPI. 284 This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 285 and pn11). 286 287 ext_wapi_pn_127_96 288 289 Extension PN (packet number) which is only used by WAPI. 290 This corresponds to WAPI PN bits [127:96] (pn12, pn13, 291 pn14, pn15). 292 293 reported_mpdu_length 294 295 MPDU length before decapsulation. Only valid when 296 first_msdu is set. This field is taken directly from the 297 length field of the A-MPDU delimiter or the preamble length 298 field for non-A-MPDU frames. 299 300 first_msdu 301 302 Indicates the first MSDU of A-MSDU. If both first_msdu 303 and last_msdu are set in the MSDU then this is a 304 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 305 A-MSDU shall have both first_mpdu and last_mpdu bits set to 306 0. 307 308 last_msdu 309 310 Indicates the last MSDU of the A-MSDU. MPDU end status 311 is only valid when last_msdu is set. 312 313 sa_idx_timeout 314 315 Indicates an unsuccessful MAC source address search due 316 to the expiring of the search timer. 317 318 da_idx_timeout 319 320 Indicates an unsuccessful MAC destination address search 321 due to the expiring of the search timer. 322 323 msdu_limit_error 324 325 Indicates that the MSDU threshold was exceeded and thus 326 all the rest of the MSDUs will not be scattered and will not 327 be decapsulated but will be DMA'ed in RAW format as a single 328 MSDU buffer 329 330 flow_idx_timeout 331 332 Indicates an unsuccessful flow search due to the 333 expiring of the search timer. 334 335 <legal all> 336 337 flow_idx_invalid 338 339 flow id is not valid 340 341 <legal all> 342 343 wifi_parser_error 344 345 Indicates that the WiFi frame has one of the following 346 errors 347 348 o has less than minimum allowed bytes as per standard 349 350 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 351 352 <legal all> 353 354 amsdu_parser_error 355 356 A-MSDU could not be properly de-agregated. 357 358 <legal all> 359 360 sa_is_valid 361 362 Indicates that OLE found a valid SA entry 363 364 da_is_valid 365 366 Indicates that OLE found a valid DA entry 367 368 da_is_mcbc 369 370 Field Only valid if da_is_valid is set 371 372 373 374 Indicates the DA address was a Multicast of Broadcast 375 address. 376 377 l3_header_padding 378 379 Number of bytes padded to make sure that the L3 header 380 will always start of a Dword boundary 381 382 reserved_5a 383 384 <legal 0> 385 386 ipv6_options_crc 387 388 32 bit CRC computed out of IP v6 extension headers 389 390 tcp_seq_number 391 392 TCP sequence number (as a number assembled from a TCP 393 packet in big-endian order, i.e. requiring a byte-swap for 394 little-endian FW/SW w.r.t. the byte order in a packet) 395 396 tcp_ack_number 397 398 TCP acknowledge number (as a number assembled from a TCP 399 packet in big-endian order, i.e. requiring a byte-swap for 400 little-endian FW/SW w.r.t. the byte order in a packet) 401 402 tcp_flag 403 404 TCP flags 405 406 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 407 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 408 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 409 the byte order in a packet) 410 411 lro_eligible 412 413 Computed out of TCP and IP fields to indicate that this 414 MSDU is eligible for LRO 415 416 reserved_9a 417 418 NOTE: DO not assign a field... Internally used in 419 RXOLE.. 420 421 <legal 0> 422 423 window_size 424 425 TCP receive window size (as a number assembled from a 426 TCP packet in big-endian order, i.e. requiring a byte-swap 427 for little-endian FW/SW w.r.t. the byte order in a packet) 428 429 da_offset 430 431 Offset into MSDU buffer for DA 432 433 sa_offset 434 435 Offset into MSDU buffer for SA 436 437 da_offset_valid 438 439 da_offset field is valid. This will be set to 0 in case 440 of a dynamic A-MSDU when DA is compressed 441 442 sa_offset_valid 443 444 sa_offset field is valid. This will be set to 0 in case 445 of a dynamic A-MSDU when SA is compressed 446 447 reserved_10a 448 449 <legal 0> 450 451 l3_type 452 453 The 16-bit type value indicating the type of L3 later 454 extracted from LLC/SNAP, set to zero if SNAP is not 455 available 456 457 rule_indication_31_0 458 459 Bitmap indicating which of rules 31-0 have matched 460 461 rule_indication_63_32 462 463 Bitmap indicating which of rules 63-32 have matched 464 465 sa_idx 466 467 The offset in the address table which matches the MAC 468 source address. 469 470 da_idx_or_sw_peer_id 471 472 Based on a register configuration in RXOLE, this field 473 will contain: 474 475 The offset in the address table which matches the MAC 476 destination address 477 478 OR: 479 480 sw_peer_id from the address search entry corresponding 481 to the destination address of the MSDU 482 483 msdu_drop 484 485 When set, REO shall drop this MSDU and not forward it to 486 any other ring... 487 488 <legal all> 489 490 reo_destination_indication 491 492 The ID of the REO exit ring where the MSDU frame shall 493 push after (MPDU level) reordering has finished. 494 495 496 497 <enum 0 reo_destination_tcl> Reo will push the frame 498 into the REO2TCL ring 499 500 <enum 1 reo_destination_sw1> Reo will push the frame 501 into the REO2SW1 ring 502 503 <enum 2 reo_destination_sw2> Reo will push the frame 504 into the REO2SW1 ring 505 506 <enum 3 reo_destination_sw3> Reo will push the frame 507 into the REO2SW1 ring 508 509 <enum 4 reo_destination_sw4> Reo will push the frame 510 into the REO2SW1 ring 511 512 <enum 5 reo_destination_release> Reo will push the frame 513 into the REO_release ring 514 515 <enum 6 reo_destination_fw> Reo will push the frame into 516 the REO2FW ring 517 518 <enum 7 reo_destination_7> REO remaps this 519 520 <enum 8 reo_destination_8> REO remaps this <enum 9 521 reo_destination_9> REO remaps this <enum 10 522 reo_destination_10> REO remaps this 523 524 <enum 11 reo_destination_11> REO remaps this 525 526 <enum 12 reo_destination_12> REO remaps this <enum 13 527 reo_destination_13> REO remaps this 528 529 <enum 14 reo_destination_14> REO remaps this 530 531 <enum 15 reo_destination_15> REO remaps this 532 533 <enum 16 reo_destination_16> REO remaps this 534 535 <enum 17 reo_destination_17> REO remaps this 536 537 <enum 18 reo_destination_18> REO remaps this 538 539 <enum 19 reo_destination_19> REO remaps this 540 541 <enum 20 reo_destination_20> REO remaps this 542 543 <enum 21 reo_destination_21> REO remaps this 544 545 <enum 22 reo_destination_22> REO remaps this 546 547 <enum 23 reo_destination_23> REO remaps this 548 549 <enum 24 reo_destination_24> REO remaps this 550 551 <enum 25 reo_destination_25> REO remaps this 552 553 <enum 26 reo_destination_26> REO remaps this 554 555 <enum 27 reo_destination_27> REO remaps this 556 557 <enum 28 reo_destination_28> REO remaps this 558 559 <enum 29 reo_destination_29> REO remaps this 560 561 <enum 30 reo_destination_30> REO remaps this 562 563 <enum 31 reo_destination_31> REO remaps this 564 565 566 567 <legal all> 568 569 flow_idx 570 571 Flow table index 572 573 <legal all> 574 575 reserved_14 576 577 <legal 0> 578 579 fse_metadata 580 581 FSE related meta data: 582 583 <legal all> 584 585 cce_metadata 586 587 CCE related meta data: 588 589 <legal all> 590 591 sa_sw_peer_id 592 593 sw_peer_id from the address search entry corresponding 594 to the source address of the MSDU 595 596 <legal 0> 597 */ 598 599 600 /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 601 602 Field indicates what the reason was that this MPDU frame 603 was allowed to come into the receive path by RXPCU 604 605 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 606 frame filter programming of rxpcu 607 608 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 609 regular frame filter and would have been dropped, were it 610 not for the frame fitting into the 'monitor_client' 611 category. 612 613 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 614 regular frame filter and also did not pass the 615 rxpcu_monitor_client filter. It would have been dropped 616 accept that it did pass the 'monitor_other' category. 617 618 <legal 0-2> 619 */ 620 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 621 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 622 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 623 624 /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID 625 626 SW processes frames based on certain classifications. 627 This field indicates to what sw classification this MPDU is 628 mapped. 629 630 The classification is given in priority order 631 632 633 634 <enum 0 sw_frame_group_NDP_frame> 635 636 637 638 <enum 1 sw_frame_group_Multicast_data> 639 640 <enum 2 sw_frame_group_Unicast_data> 641 642 <enum 3 sw_frame_group_Null_data > This includes mpdus 643 of type Data Null as well as QoS Data Null 644 645 646 647 <enum 4 sw_frame_group_mgmt_0000 > 648 649 <enum 5 sw_frame_group_mgmt_0001 > 650 651 <enum 6 sw_frame_group_mgmt_0010 > 652 653 <enum 7 sw_frame_group_mgmt_0011 > 654 655 <enum 8 sw_frame_group_mgmt_0100 > 656 657 <enum 9 sw_frame_group_mgmt_0101 > 658 659 <enum 10 sw_frame_group_mgmt_0110 > 660 661 <enum 11 sw_frame_group_mgmt_0111 > 662 663 <enum 12 sw_frame_group_mgmt_1000 > 664 665 <enum 13 sw_frame_group_mgmt_1001 > 666 667 <enum 14 sw_frame_group_mgmt_1010 > 668 669 <enum 15 sw_frame_group_mgmt_1011 > 670 671 <enum 16 sw_frame_group_mgmt_1100 > 672 673 <enum 17 sw_frame_group_mgmt_1101 > 674 675 <enum 18 sw_frame_group_mgmt_1110 > 676 677 <enum 19 sw_frame_group_mgmt_1111 > 678 679 680 681 <enum 20 sw_frame_group_ctrl_0000 > 682 683 <enum 21 sw_frame_group_ctrl_0001 > 684 685 <enum 22 sw_frame_group_ctrl_0010 > 686 687 <enum 23 sw_frame_group_ctrl_0011 > 688 689 <enum 24 sw_frame_group_ctrl_0100 > 690 691 <enum 25 sw_frame_group_ctrl_0101 > 692 693 <enum 26 sw_frame_group_ctrl_0110 > 694 695 <enum 27 sw_frame_group_ctrl_0111 > 696 697 <enum 28 sw_frame_group_ctrl_1000 > 698 699 <enum 29 sw_frame_group_ctrl_1001 > 700 701 <enum 30 sw_frame_group_ctrl_1010 > 702 703 <enum 31 sw_frame_group_ctrl_1011 > 704 705 <enum 32 sw_frame_group_ctrl_1100 > 706 707 <enum 33 sw_frame_group_ctrl_1101 > 708 709 <enum 34 sw_frame_group_ctrl_1110 > 710 711 <enum 35 sw_frame_group_ctrl_1111 > 712 713 714 715 <enum 36 sw_frame_group_unsupported> This covers type 3 716 and protocol version != 0 717 718 719 720 721 722 723 <legal 0-37> 724 */ 725 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 726 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 727 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 728 729 /* Description RX_MSDU_END_0_RESERVED_0 730 731 <legal 0> 732 */ 733 #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 734 #define RX_MSDU_END_0_RESERVED_0_LSB 9 735 #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 736 737 /* Description RX_MSDU_END_0_PHY_PPDU_ID 738 739 A ppdu counter value that PHY increments for every PPDU 740 received. The counter value wraps around 741 742 <legal all> 743 */ 744 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 745 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 746 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 747 748 /* Description RX_MSDU_END_1_IP_HDR_CHKSUM 749 750 This can include the IP header checksum or the pseudo 751 header checksum used by TCP/UDP checksum. 752 753 (with the first byte in the MSB and the second byte in 754 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 755 w.r.t. the byte order in a packet) 756 */ 757 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 758 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 759 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff 760 761 /* Description RX_MSDU_END_1_TCP_UDP_CHKSUM 762 763 The value of the computed TCP/UDP checksum. A mode bit 764 selects whether this checksum is the full checksum or the 765 partial checksum which does not include the pseudo header. 766 (with the first byte in the MSB and the second byte in the 767 LSB, i.e. requiring a byte-swap for little-endian FW/SW 768 w.r.t. the byte order in a packet) 769 */ 770 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET 0x00000004 771 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB 16 772 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK 0xffff0000 773 774 /* Description RX_MSDU_END_2_KEY_ID_OCTET 775 776 The key ID octet from the IV. Only valid when 777 first_msdu is set. 778 */ 779 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 780 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 781 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff 782 783 /* Description RX_MSDU_END_2_CCE_SUPER_RULE 784 785 Indicates the super filter rule 786 */ 787 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 788 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 789 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 790 791 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE 792 793 Classification failed due to truncated frame 794 */ 795 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 796 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 797 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 798 799 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS 800 801 Classification failed due to CCE global disable 802 */ 803 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 804 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 805 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 806 807 /* Description RX_MSDU_END_2_EXT_WAPI_PN_63_48 808 809 Extension PN (packet number) which is only used by WAPI. 810 This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 811 The WAPI PN bits [63:0] are in the pn field of the 812 rx_mpdu_start descriptor. 813 */ 814 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET 0x00000008 815 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB 16 816 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK 0xffff0000 817 818 /* Description RX_MSDU_END_3_EXT_WAPI_PN_95_64 819 820 Extension PN (packet number) which is only used by WAPI. 821 This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 822 and pn11). 823 */ 824 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET 0x0000000c 825 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB 0 826 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK 0xffffffff 827 828 /* Description RX_MSDU_END_4_EXT_WAPI_PN_127_96 829 830 Extension PN (packet number) which is only used by WAPI. 831 This corresponds to WAPI PN bits [127:96] (pn12, pn13, 832 pn14, pn15). 833 */ 834 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET 0x00000010 835 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB 0 836 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK 0xffffffff 837 838 /* Description RX_MSDU_END_5_REPORTED_MPDU_LENGTH 839 840 MPDU length before decapsulation. Only valid when 841 first_msdu is set. This field is taken directly from the 842 length field of the A-MPDU delimiter or the preamble length 843 field for non-A-MPDU frames. 844 */ 845 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_OFFSET 0x00000014 846 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_LSB 0 847 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK 0x00003fff 848 849 /* Description RX_MSDU_END_5_FIRST_MSDU 850 851 Indicates the first MSDU of A-MSDU. If both first_msdu 852 and last_msdu are set in the MSDU then this is a 853 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 854 A-MSDU shall have both first_mpdu and last_mpdu bits set to 855 0. 856 */ 857 #define RX_MSDU_END_5_FIRST_MSDU_OFFSET 0x00000014 858 #define RX_MSDU_END_5_FIRST_MSDU_LSB 14 859 #define RX_MSDU_END_5_FIRST_MSDU_MASK 0x00004000 860 861 /* Description RX_MSDU_END_5_LAST_MSDU 862 863 Indicates the last MSDU of the A-MSDU. MPDU end status 864 is only valid when last_msdu is set. 865 */ 866 #define RX_MSDU_END_5_LAST_MSDU_OFFSET 0x00000014 867 #define RX_MSDU_END_5_LAST_MSDU_LSB 15 868 #define RX_MSDU_END_5_LAST_MSDU_MASK 0x00008000 869 870 /* Description RX_MSDU_END_5_SA_IDX_TIMEOUT 871 872 Indicates an unsuccessful MAC source address search due 873 to the expiring of the search timer. 874 */ 875 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_OFFSET 0x00000014 876 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_LSB 16 877 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK 0x00010000 878 879 /* Description RX_MSDU_END_5_DA_IDX_TIMEOUT 880 881 Indicates an unsuccessful MAC destination address search 882 due to the expiring of the search timer. 883 */ 884 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_OFFSET 0x00000014 885 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_LSB 17 886 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK 0x00020000 887 888 /* Description RX_MSDU_END_5_MSDU_LIMIT_ERROR 889 890 Indicates that the MSDU threshold was exceeded and thus 891 all the rest of the MSDUs will not be scattered and will not 892 be decapsulated but will be DMA'ed in RAW format as a single 893 MSDU buffer 894 */ 895 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_OFFSET 0x00000014 896 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_LSB 18 897 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK 0x00040000 898 899 /* Description RX_MSDU_END_5_FLOW_IDX_TIMEOUT 900 901 Indicates an unsuccessful flow search due to the 902 expiring of the search timer. 903 904 <legal all> 905 */ 906 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET 0x00000014 907 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB 19 908 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK 0x00080000 909 910 /* Description RX_MSDU_END_5_FLOW_IDX_INVALID 911 912 flow id is not valid 913 914 <legal all> 915 */ 916 #define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET 0x00000014 917 #define RX_MSDU_END_5_FLOW_IDX_INVALID_LSB 20 918 #define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK 0x00100000 919 920 /* Description RX_MSDU_END_5_WIFI_PARSER_ERROR 921 922 Indicates that the WiFi frame has one of the following 923 errors 924 925 o has less than minimum allowed bytes as per standard 926 927 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 928 929 <legal all> 930 */ 931 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET 0x00000014 932 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_LSB 21 933 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK 0x00200000 934 935 /* Description RX_MSDU_END_5_AMSDU_PARSER_ERROR 936 937 A-MSDU could not be properly de-agregated. 938 939 <legal all> 940 */ 941 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET 0x00000014 942 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_LSB 22 943 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK 0x00400000 944 945 /* Description RX_MSDU_END_5_SA_IS_VALID 946 947 Indicates that OLE found a valid SA entry 948 */ 949 #define RX_MSDU_END_5_SA_IS_VALID_OFFSET 0x00000014 950 #define RX_MSDU_END_5_SA_IS_VALID_LSB 23 951 #define RX_MSDU_END_5_SA_IS_VALID_MASK 0x00800000 952 953 /* Description RX_MSDU_END_5_DA_IS_VALID 954 955 Indicates that OLE found a valid DA entry 956 */ 957 #define RX_MSDU_END_5_DA_IS_VALID_OFFSET 0x00000014 958 #define RX_MSDU_END_5_DA_IS_VALID_LSB 24 959 #define RX_MSDU_END_5_DA_IS_VALID_MASK 0x01000000 960 961 /* Description RX_MSDU_END_5_DA_IS_MCBC 962 963 Field Only valid if da_is_valid is set 964 965 966 967 Indicates the DA address was a Multicast of Broadcast 968 address. 969 */ 970 #define RX_MSDU_END_5_DA_IS_MCBC_OFFSET 0x00000014 971 #define RX_MSDU_END_5_DA_IS_MCBC_LSB 25 972 #define RX_MSDU_END_5_DA_IS_MCBC_MASK 0x02000000 973 974 /* Description RX_MSDU_END_5_L3_HEADER_PADDING 975 976 Number of bytes padded to make sure that the L3 header 977 will always start of a Dword boundary 978 */ 979 #define RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET 0x00000014 980 #define RX_MSDU_END_5_L3_HEADER_PADDING_LSB 26 981 #define RX_MSDU_END_5_L3_HEADER_PADDING_MASK 0x0c000000 982 983 /* Description RX_MSDU_END_5_RESERVED_5A 984 985 <legal 0> 986 */ 987 #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 988 #define RX_MSDU_END_5_RESERVED_5A_LSB 28 989 #define RX_MSDU_END_5_RESERVED_5A_MASK 0xf0000000 990 991 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC 992 993 32 bit CRC computed out of IP v6 extension headers 994 */ 995 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 996 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 997 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff 998 999 /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER 1000 1001 TCP sequence number (as a number assembled from a TCP 1002 packet in big-endian order, i.e. requiring a byte-swap for 1003 little-endian FW/SW w.r.t. the byte order in a packet) 1004 */ 1005 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c 1006 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 1007 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff 1008 1009 /* Description RX_MSDU_END_8_TCP_ACK_NUMBER 1010 1011 TCP acknowledge number (as a number assembled from a TCP 1012 packet in big-endian order, i.e. requiring a byte-swap for 1013 little-endian FW/SW w.r.t. the byte order in a packet) 1014 */ 1015 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 1016 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 1017 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff 1018 1019 /* Description RX_MSDU_END_9_TCP_FLAG 1020 1021 TCP flags 1022 1023 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 1024 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 1025 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 1026 the byte order in a packet) 1027 */ 1028 #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 1029 #define RX_MSDU_END_9_TCP_FLAG_LSB 0 1030 #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff 1031 1032 /* Description RX_MSDU_END_9_LRO_ELIGIBLE 1033 1034 Computed out of TCP and IP fields to indicate that this 1035 MSDU is eligible for LRO 1036 */ 1037 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 1038 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 1039 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 1040 1041 /* Description RX_MSDU_END_9_RESERVED_9A 1042 1043 NOTE: DO not assign a field... Internally used in 1044 RXOLE.. 1045 1046 <legal 0> 1047 */ 1048 #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 1049 #define RX_MSDU_END_9_RESERVED_9A_LSB 10 1050 #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 1051 1052 /* Description RX_MSDU_END_9_WINDOW_SIZE 1053 1054 TCP receive window size (as a number assembled from a 1055 TCP packet in big-endian order, i.e. requiring a byte-swap 1056 for little-endian FW/SW w.r.t. the byte order in a packet) 1057 */ 1058 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 1059 #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 1060 #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 1061 1062 /* Description RX_MSDU_END_10_DA_OFFSET 1063 1064 Offset into MSDU buffer for DA 1065 */ 1066 #define RX_MSDU_END_10_DA_OFFSET_OFFSET 0x00000028 1067 #define RX_MSDU_END_10_DA_OFFSET_LSB 0 1068 #define RX_MSDU_END_10_DA_OFFSET_MASK 0x0000003f 1069 1070 /* Description RX_MSDU_END_10_SA_OFFSET 1071 1072 Offset into MSDU buffer for SA 1073 */ 1074 #define RX_MSDU_END_10_SA_OFFSET_OFFSET 0x00000028 1075 #define RX_MSDU_END_10_SA_OFFSET_LSB 6 1076 #define RX_MSDU_END_10_SA_OFFSET_MASK 0x00000fc0 1077 1078 /* Description RX_MSDU_END_10_DA_OFFSET_VALID 1079 1080 da_offset field is valid. This will be set to 0 in case 1081 of a dynamic A-MSDU when DA is compressed 1082 */ 1083 #define RX_MSDU_END_10_DA_OFFSET_VALID_OFFSET 0x00000028 1084 #define RX_MSDU_END_10_DA_OFFSET_VALID_LSB 12 1085 #define RX_MSDU_END_10_DA_OFFSET_VALID_MASK 0x00001000 1086 1087 /* Description RX_MSDU_END_10_SA_OFFSET_VALID 1088 1089 sa_offset field is valid. This will be set to 0 in case 1090 of a dynamic A-MSDU when SA is compressed 1091 */ 1092 #define RX_MSDU_END_10_SA_OFFSET_VALID_OFFSET 0x00000028 1093 #define RX_MSDU_END_10_SA_OFFSET_VALID_LSB 13 1094 #define RX_MSDU_END_10_SA_OFFSET_VALID_MASK 0x00002000 1095 1096 /* Description RX_MSDU_END_10_RESERVED_10A 1097 1098 <legal 0> 1099 */ 1100 #define RX_MSDU_END_10_RESERVED_10A_OFFSET 0x00000028 1101 #define RX_MSDU_END_10_RESERVED_10A_LSB 14 1102 #define RX_MSDU_END_10_RESERVED_10A_MASK 0x0000c000 1103 1104 /* Description RX_MSDU_END_10_L3_TYPE 1105 1106 The 16-bit type value indicating the type of L3 later 1107 extracted from LLC/SNAP, set to zero if SNAP is not 1108 available 1109 */ 1110 #define RX_MSDU_END_10_L3_TYPE_OFFSET 0x00000028 1111 #define RX_MSDU_END_10_L3_TYPE_LSB 16 1112 #define RX_MSDU_END_10_L3_TYPE_MASK 0xffff0000 1113 1114 /* Description RX_MSDU_END_11_RULE_INDICATION_31_0 1115 1116 Bitmap indicating which of rules 31-0 have matched 1117 */ 1118 #define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET 0x0000002c 1119 #define RX_MSDU_END_11_RULE_INDICATION_31_0_LSB 0 1120 #define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK 0xffffffff 1121 1122 /* Description RX_MSDU_END_12_RULE_INDICATION_63_32 1123 1124 Bitmap indicating which of rules 63-32 have matched 1125 */ 1126 #define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET 0x00000030 1127 #define RX_MSDU_END_12_RULE_INDICATION_63_32_LSB 0 1128 #define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK 0xffffffff 1129 1130 /* Description RX_MSDU_END_13_SA_IDX 1131 1132 The offset in the address table which matches the MAC 1133 source address. 1134 */ 1135 #define RX_MSDU_END_13_SA_IDX_OFFSET 0x00000034 1136 #define RX_MSDU_END_13_SA_IDX_LSB 0 1137 #define RX_MSDU_END_13_SA_IDX_MASK 0x0000ffff 1138 1139 /* Description RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID 1140 1141 Based on a register configuration in RXOLE, this field 1142 will contain: 1143 1144 The offset in the address table which matches the MAC 1145 destination address 1146 1147 OR: 1148 1149 sw_peer_id from the address search entry corresponding 1150 to the destination address of the MSDU 1151 */ 1152 #define RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET 0x00000034 1153 #define RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB 16 1154 #define RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 1155 1156 /* Description RX_MSDU_END_14_MSDU_DROP 1157 1158 When set, REO shall drop this MSDU and not forward it to 1159 any other ring... 1160 1161 <legal all> 1162 */ 1163 #define RX_MSDU_END_14_MSDU_DROP_OFFSET 0x00000038 1164 #define RX_MSDU_END_14_MSDU_DROP_LSB 0 1165 #define RX_MSDU_END_14_MSDU_DROP_MASK 0x00000001 1166 1167 /* Description RX_MSDU_END_14_REO_DESTINATION_INDICATION 1168 1169 The ID of the REO exit ring where the MSDU frame shall 1170 push after (MPDU level) reordering has finished. 1171 1172 1173 1174 <enum 0 reo_destination_tcl> Reo will push the frame 1175 into the REO2TCL ring 1176 1177 <enum 1 reo_destination_sw1> Reo will push the frame 1178 into the REO2SW1 ring 1179 1180 <enum 2 reo_destination_sw2> Reo will push the frame 1181 into the REO2SW1 ring 1182 1183 <enum 3 reo_destination_sw3> Reo will push the frame 1184 into the REO2SW1 ring 1185 1186 <enum 4 reo_destination_sw4> Reo will push the frame 1187 into the REO2SW1 ring 1188 1189 <enum 5 reo_destination_release> Reo will push the frame 1190 into the REO_release ring 1191 1192 <enum 6 reo_destination_fw> Reo will push the frame into 1193 the REO2FW ring 1194 1195 <enum 7 reo_destination_7> REO remaps this 1196 1197 <enum 8 reo_destination_8> REO remaps this <enum 9 1198 reo_destination_9> REO remaps this <enum 10 1199 reo_destination_10> REO remaps this 1200 1201 <enum 11 reo_destination_11> REO remaps this 1202 1203 <enum 12 reo_destination_12> REO remaps this <enum 13 1204 reo_destination_13> REO remaps this 1205 1206 <enum 14 reo_destination_14> REO remaps this 1207 1208 <enum 15 reo_destination_15> REO remaps this 1209 1210 <enum 16 reo_destination_16> REO remaps this 1211 1212 <enum 17 reo_destination_17> REO remaps this 1213 1214 <enum 18 reo_destination_18> REO remaps this 1215 1216 <enum 19 reo_destination_19> REO remaps this 1217 1218 <enum 20 reo_destination_20> REO remaps this 1219 1220 <enum 21 reo_destination_21> REO remaps this 1221 1222 <enum 22 reo_destination_22> REO remaps this 1223 1224 <enum 23 reo_destination_23> REO remaps this 1225 1226 <enum 24 reo_destination_24> REO remaps this 1227 1228 <enum 25 reo_destination_25> REO remaps this 1229 1230 <enum 26 reo_destination_26> REO remaps this 1231 1232 <enum 27 reo_destination_27> REO remaps this 1233 1234 <enum 28 reo_destination_28> REO remaps this 1235 1236 <enum 29 reo_destination_29> REO remaps this 1237 1238 <enum 30 reo_destination_30> REO remaps this 1239 1240 <enum 31 reo_destination_31> REO remaps this 1241 1242 1243 1244 <legal all> 1245 */ 1246 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET 0x00000038 1247 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_LSB 1 1248 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK 0x0000003e 1249 1250 /* Description RX_MSDU_END_14_FLOW_IDX 1251 1252 Flow table index 1253 1254 <legal all> 1255 */ 1256 #define RX_MSDU_END_14_FLOW_IDX_OFFSET 0x00000038 1257 #define RX_MSDU_END_14_FLOW_IDX_LSB 6 1258 #define RX_MSDU_END_14_FLOW_IDX_MASK 0x03ffffc0 1259 1260 /* Description RX_MSDU_END_14_RESERVED_14 1261 1262 <legal 0> 1263 */ 1264 #define RX_MSDU_END_14_RESERVED_14_OFFSET 0x00000038 1265 #define RX_MSDU_END_14_RESERVED_14_LSB 26 1266 #define RX_MSDU_END_14_RESERVED_14_MASK 0xfc000000 1267 1268 /* Description RX_MSDU_END_15_FSE_METADATA 1269 1270 FSE related meta data: 1271 1272 <legal all> 1273 */ 1274 #define RX_MSDU_END_15_FSE_METADATA_OFFSET 0x0000003c 1275 #define RX_MSDU_END_15_FSE_METADATA_LSB 0 1276 #define RX_MSDU_END_15_FSE_METADATA_MASK 0xffffffff 1277 1278 /* Description RX_MSDU_END_16_CCE_METADATA 1279 1280 CCE related meta data: 1281 1282 <legal all> 1283 */ 1284 #define RX_MSDU_END_16_CCE_METADATA_OFFSET 0x00000040 1285 #define RX_MSDU_END_16_CCE_METADATA_LSB 0 1286 #define RX_MSDU_END_16_CCE_METADATA_MASK 0x0000ffff 1287 1288 /* Description RX_MSDU_END_16_SA_SW_PEER_ID 1289 1290 sw_peer_id from the address search entry corresponding 1291 to the source address of the MSDU 1292 1293 <legal 0> 1294 */ 1295 #define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET 0x00000040 1296 #define RX_MSDU_END_16_SA_SW_PEER_ID_LSB 16 1297 #define RX_MSDU_END_16_SA_SW_PEER_ID_MASK 0xffff0000 1298 1299 1300 #endif // _RX_MSDU_END_H_ 1301