1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _TX_MSDU_EXTENSION_H_ 20 #define _TX_MSDU_EXTENSION_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 tso_enable[0], reserved_0a[6:1], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25] 29 // 1 l2_length[15:0], ip_length[31:16] 30 // 2 tcp_seq_number[31:0] 31 // 3 ip_identification[15:0], udp_length[31:16] 32 // 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30] 33 // 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17] 34 // 6 buf0_ptr_31_0[31:0] 35 // 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16] 36 // 8 buf1_ptr_31_0[31:0] 37 // 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16] 38 // 10 buf2_ptr_31_0[31:0] 39 // 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16] 40 // 12 buf3_ptr_31_0[31:0] 41 // 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16] 42 // 14 buf4_ptr_31_0[31:0] 43 // 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16] 44 // 16 buf5_ptr_31_0[31:0] 45 // 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16] 46 // 47 // ################ END SUMMARY ################# 48 49 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 50 51 struct tx_msdu_extension { 52 uint32_t tso_enable : 1, //[0] 53 reserved_0a : 6, //[6:1] 54 tcp_flag : 9, //[15:7] 55 tcp_flag_mask : 9, //[24:16] 56 reserved_0b : 7; //[31:25] 57 uint32_t l2_length : 16, //[15:0] 58 ip_length : 16; //[31:16] 59 uint32_t tcp_seq_number : 32; //[31:0] 60 uint32_t ip_identification : 16, //[15:0] 61 udp_length : 16; //[31:16] 62 uint32_t checksum_offset : 14, //[13:0] 63 partial_checksum_en : 1, //[14] 64 reserved_4a : 1, //[15] 65 payload_start_offset : 14, //[29:16] 66 reserved_4b : 2; //[31:30] 67 uint32_t payload_end_offset : 14, //[13:0] 68 reserved_5a : 2, //[15:14] 69 wds : 1, //[16] 70 reserved_5b : 15; //[31:17] 71 uint32_t buf0_ptr_31_0 : 32; //[31:0] 72 uint32_t buf0_ptr_39_32 : 8, //[7:0] 73 reserved_7a : 8, //[15:8] 74 buf0_len : 16; //[31:16] 75 uint32_t buf1_ptr_31_0 : 32; //[31:0] 76 uint32_t buf1_ptr_39_32 : 8, //[7:0] 77 reserved_9a : 8, //[15:8] 78 buf1_len : 16; //[31:16] 79 uint32_t buf2_ptr_31_0 : 32; //[31:0] 80 uint32_t buf2_ptr_39_32 : 8, //[7:0] 81 reserved_11a : 8, //[15:8] 82 buf2_len : 16; //[31:16] 83 uint32_t buf3_ptr_31_0 : 32; //[31:0] 84 uint32_t buf3_ptr_39_32 : 8, //[7:0] 85 reserved_13a : 8, //[15:8] 86 buf3_len : 16; //[31:16] 87 uint32_t buf4_ptr_31_0 : 32; //[31:0] 88 uint32_t buf4_ptr_39_32 : 8, //[7:0] 89 reserved_15a : 8, //[15:8] 90 buf4_len : 16; //[31:16] 91 uint32_t buf5_ptr_31_0 : 32; //[31:0] 92 uint32_t buf5_ptr_39_32 : 8, //[7:0] 93 reserved_17a : 8, //[15:8] 94 buf5_len : 16; //[31:16] 95 }; 96 97 /* 98 99 tso_enable 100 101 Enable transmit segmentation offload <legal all> 102 103 reserved_0a 104 105 FW will set to 0, MAC will ignore. <legal 0> 106 107 tcp_flag 108 109 TCP flags 110 111 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all> 112 113 tcp_flag_mask 114 115 TCP flag mask. Tcp_flag is inserted into the header 116 based on the mask, if tso is enabled 117 118 reserved_0b 119 120 FW will set to 0, MAC will ignore. <legal 0> 121 122 l2_length 123 124 L2 length for the msdu, if tso is enabled <legal all> 125 126 ip_length 127 128 Ip length for the msdu, if tso is enabled <legal all> 129 130 tcp_seq_number 131 132 Tcp_seq_number for the msdu, if tso is enabled <legal 133 all> 134 135 ip_identification 136 137 Ip_identification for the msdu, if tso is enabled <legal 138 all> 139 140 udp_length 141 142 TXDMA is copies this field into MSDU START TLV 143 144 checksum_offset 145 146 The calculated checksum from start offset to end offset 147 will be added to the checksum at the offset given by this 148 field<legal all> 149 150 partial_checksum_en 151 152 Partial Checksum Enable Bit. 153 154 <legal 0-1> 155 156 reserved_4a 157 158 <Legal 0> 159 160 payload_start_offset 161 162 L4 checksum calculations will start fromt this offset 163 164 <Legal all> 165 166 reserved_4b 167 168 <Legal 0> 169 170 payload_end_offset 171 172 L4 checksum calculations will end at this offset. 173 174 <Legal all> 175 176 reserved_5a 177 178 <Legal 0> 179 180 wds 181 182 If set the current packet is 4-address frame. Required 183 because an aggregate can include some frames with 3 address 184 format and other frames with 4 address format. Used by the 185 OLE during encapsulation. 186 187 Note: there is also global wds tx control in the 188 TX_PEER_ENTRY 189 190 <legal all> 191 192 reserved_5b 193 194 <Legal 0> 195 196 buf0_ptr_31_0 197 198 Lower 32 bits of the first buffer pointer 199 200 201 202 NOTE: SW/FW manages the 'cookie' info related to this 203 buffer together with the 'cookie' info for this 204 MSDU_EXTENSION descriptor 205 206 <legal all> 207 208 buf0_ptr_39_32 209 210 Upper 8 bits of the first buffer pointer <legal all> 211 212 reserved_7a 213 214 <Legal 0> 215 216 buf0_len 217 218 Length of the first buffer <legal all> 219 220 buf1_ptr_31_0 221 222 Lower 32 bits of the second buffer pointer 223 224 225 226 NOTE: SW/FW manages the 'cookie' info related to this 227 buffer together with the 'cookie' info for this 228 MSDU_EXTENSION descriptor 229 230 <legal all> 231 232 buf1_ptr_39_32 233 234 Upper 8 bits of the second buffer pointer <legal all> 235 236 reserved_9a 237 238 <Legal 0> 239 240 buf1_len 241 242 Length of the second buffer <legal all> 243 244 buf2_ptr_31_0 245 246 Lower 32 bits of the third buffer pointer 247 248 NOTE: SW/FW manages the 'cookie' info related to this 249 buffer together with the 'cookie' info for this 250 MSDU_EXTENSION descriptor 251 252 <legal all> 253 254 buf2_ptr_39_32 255 256 Upper 8 bits of the third buffer pointer <legal all> 257 258 reserved_11a 259 260 <Legal 0> 261 262 buf2_len 263 264 Length of the third buffer <legal all> 265 266 buf3_ptr_31_0 267 268 Lower 32 bits of the fourth buffer pointer 269 270 271 272 NOTE: SW/FW manages the 'cookie' info related to this 273 buffer together with the 'cookie' info for this 274 MSDU_EXTENSION descriptor 275 276 <legal all> 277 278 buf3_ptr_39_32 279 280 Upper 8 bits of the fourth buffer pointer <legal all> 281 282 reserved_13a 283 284 <Legal 0> 285 286 buf3_len 287 288 Length of the fourth buffer <legal all> 289 290 buf4_ptr_31_0 291 292 Lower 32 bits of the fifth buffer pointer 293 294 295 296 NOTE: SW/FW manages the 'cookie' info related to this 297 buffer together with the 'cookie' info for this 298 MSDU_EXTENSION descriptor 299 300 <legal all> 301 302 buf4_ptr_39_32 303 304 Upper 8 bits of the fifth buffer pointer <legal all> 305 306 reserved_15a 307 308 <Legal 0> 309 310 buf4_len 311 312 Length of the fifth buffer <legal all> 313 314 buf5_ptr_31_0 315 316 Lower 32 bits of the sixth buffer pointer 317 318 319 320 NOTE: SW/FW manages the 'cookie' info related to this 321 buffer together with the 'cookie' info for this 322 MSDU_EXTENSION descriptor 323 324 <legal all> 325 326 buf5_ptr_39_32 327 328 Upper 8 bits of the sixth buffer pointer <legal all> 329 330 reserved_17a 331 332 <Legal 0> 333 334 buf5_len 335 336 Length of the sixth buffer <legal all> 337 */ 338 339 340 /* Description TX_MSDU_EXTENSION_0_TSO_ENABLE 341 342 Enable transmit segmentation offload <legal all> 343 */ 344 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 345 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 346 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 347 348 /* Description TX_MSDU_EXTENSION_0_RESERVED_0A 349 350 FW will set to 0, MAC will ignore. <legal 0> 351 */ 352 #define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 353 #define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1 354 #define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e 355 356 /* Description TX_MSDU_EXTENSION_0_TCP_FLAG 357 358 TCP flags 359 360 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all> 361 */ 362 #define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 363 #define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 364 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 365 366 /* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 367 368 TCP flag mask. Tcp_flag is inserted into the header 369 based on the mask, if tso is enabled 370 */ 371 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 372 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 373 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 374 375 /* Description TX_MSDU_EXTENSION_0_RESERVED_0B 376 377 FW will set to 0, MAC will ignore. <legal 0> 378 */ 379 #define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 380 #define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 381 #define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 382 383 /* Description TX_MSDU_EXTENSION_1_L2_LENGTH 384 385 L2 length for the msdu, if tso is enabled <legal all> 386 */ 387 #define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 388 #define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 389 #define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff 390 391 /* Description TX_MSDU_EXTENSION_1_IP_LENGTH 392 393 Ip length for the msdu, if tso is enabled <legal all> 394 */ 395 #define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 396 #define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 397 #define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 398 399 /* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER 400 401 Tcp_seq_number for the msdu, if tso is enabled <legal 402 all> 403 */ 404 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 405 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 406 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff 407 408 /* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION 409 410 Ip_identification for the msdu, if tso is enabled <legal 411 all> 412 */ 413 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c 414 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 415 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff 416 417 /* Description TX_MSDU_EXTENSION_3_UDP_LENGTH 418 419 TXDMA is copies this field into MSDU START TLV 420 */ 421 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c 422 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 423 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 424 425 /* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET 426 427 The calculated checksum from start offset to end offset 428 will be added to the checksum at the offset given by this 429 field<legal all> 430 */ 431 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 432 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 433 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff 434 435 /* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN 436 437 Partial Checksum Enable Bit. 438 439 <legal 0-1> 440 */ 441 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 442 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 443 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 444 445 /* Description TX_MSDU_EXTENSION_4_RESERVED_4A 446 447 <Legal 0> 448 */ 449 #define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 450 #define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 451 #define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 452 453 /* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET 454 455 L4 checksum calculations will start fromt this offset 456 457 <Legal all> 458 */ 459 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 460 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 461 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 462 463 /* Description TX_MSDU_EXTENSION_4_RESERVED_4B 464 465 <Legal 0> 466 */ 467 #define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 468 #define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 469 #define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 470 471 /* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET 472 473 L4 checksum calculations will end at this offset. 474 475 <Legal all> 476 */ 477 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 478 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 479 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff 480 481 /* Description TX_MSDU_EXTENSION_5_RESERVED_5A 482 483 <Legal 0> 484 */ 485 #define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 486 #define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 487 #define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 488 489 /* Description TX_MSDU_EXTENSION_5_WDS 490 491 If set the current packet is 4-address frame. Required 492 because an aggregate can include some frames with 3 address 493 format and other frames with 4 address format. Used by the 494 OLE during encapsulation. 495 496 Note: there is also global wds tx control in the 497 TX_PEER_ENTRY 498 499 <legal all> 500 */ 501 #define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 502 #define TX_MSDU_EXTENSION_5_WDS_LSB 16 503 #define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 504 505 /* Description TX_MSDU_EXTENSION_5_RESERVED_5B 506 507 <Legal 0> 508 */ 509 #define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 510 #define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 511 #define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 512 513 /* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0 514 515 Lower 32 bits of the first buffer pointer 516 517 518 519 NOTE: SW/FW manages the 'cookie' info related to this 520 buffer together with the 'cookie' info for this 521 MSDU_EXTENSION descriptor 522 523 <legal all> 524 */ 525 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 526 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 527 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff 528 529 /* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32 530 531 Upper 8 bits of the first buffer pointer <legal all> 532 */ 533 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c 534 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 535 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff 536 537 /* Description TX_MSDU_EXTENSION_7_RESERVED_7A 538 539 <Legal 0> 540 */ 541 #define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c 542 #define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 543 #define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 544 545 /* Description TX_MSDU_EXTENSION_7_BUF0_LEN 546 547 Length of the first buffer <legal all> 548 */ 549 #define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c 550 #define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 551 #define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 552 553 /* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0 554 555 Lower 32 bits of the second buffer pointer 556 557 558 559 NOTE: SW/FW manages the 'cookie' info related to this 560 buffer together with the 'cookie' info for this 561 MSDU_EXTENSION descriptor 562 563 <legal all> 564 */ 565 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 566 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 567 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff 568 569 /* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32 570 571 Upper 8 bits of the second buffer pointer <legal all> 572 */ 573 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 574 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 575 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff 576 577 /* Description TX_MSDU_EXTENSION_9_RESERVED_9A 578 579 <Legal 0> 580 */ 581 #define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 582 #define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 583 #define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 584 585 /* Description TX_MSDU_EXTENSION_9_BUF1_LEN 586 587 Length of the second buffer <legal all> 588 */ 589 #define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 590 #define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 591 #define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 592 593 /* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0 594 595 Lower 32 bits of the third buffer pointer 596 597 NOTE: SW/FW manages the 'cookie' info related to this 598 buffer together with the 'cookie' info for this 599 MSDU_EXTENSION descriptor 600 601 <legal all> 602 */ 603 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 604 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 605 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff 606 607 /* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32 608 609 Upper 8 bits of the third buffer pointer <legal all> 610 */ 611 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c 612 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 613 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff 614 615 /* Description TX_MSDU_EXTENSION_11_RESERVED_11A 616 617 <Legal 0> 618 */ 619 #define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c 620 #define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 621 #define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 622 623 /* Description TX_MSDU_EXTENSION_11_BUF2_LEN 624 625 Length of the third buffer <legal all> 626 */ 627 #define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c 628 #define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 629 #define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 630 631 /* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0 632 633 Lower 32 bits of the fourth buffer pointer 634 635 636 637 NOTE: SW/FW manages the 'cookie' info related to this 638 buffer together with the 'cookie' info for this 639 MSDU_EXTENSION descriptor 640 641 <legal all> 642 */ 643 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 644 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 645 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff 646 647 /* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32 648 649 Upper 8 bits of the fourth buffer pointer <legal all> 650 */ 651 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 652 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 653 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff 654 655 /* Description TX_MSDU_EXTENSION_13_RESERVED_13A 656 657 <Legal 0> 658 */ 659 #define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 660 #define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 661 #define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 662 663 /* Description TX_MSDU_EXTENSION_13_BUF3_LEN 664 665 Length of the fourth buffer <legal all> 666 */ 667 #define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 668 #define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 669 #define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 670 671 /* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0 672 673 Lower 32 bits of the fifth buffer pointer 674 675 676 677 NOTE: SW/FW manages the 'cookie' info related to this 678 buffer together with the 'cookie' info for this 679 MSDU_EXTENSION descriptor 680 681 <legal all> 682 */ 683 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 684 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 685 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff 686 687 /* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32 688 689 Upper 8 bits of the fifth buffer pointer <legal all> 690 */ 691 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c 692 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 693 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff 694 695 /* Description TX_MSDU_EXTENSION_15_RESERVED_15A 696 697 <Legal 0> 698 */ 699 #define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c 700 #define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 701 #define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 702 703 /* Description TX_MSDU_EXTENSION_15_BUF4_LEN 704 705 Length of the fifth buffer <legal all> 706 */ 707 #define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c 708 #define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 709 #define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 710 711 /* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0 712 713 Lower 32 bits of the sixth buffer pointer 714 715 716 717 NOTE: SW/FW manages the 'cookie' info related to this 718 buffer together with the 'cookie' info for this 719 MSDU_EXTENSION descriptor 720 721 <legal all> 722 */ 723 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 724 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 725 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff 726 727 /* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32 728 729 Upper 8 bits of the sixth buffer pointer <legal all> 730 */ 731 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 732 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 733 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff 734 735 /* Description TX_MSDU_EXTENSION_17_RESERVED_17A 736 737 <Legal 0> 738 */ 739 #define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 740 #define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 741 #define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 742 743 /* Description TX_MSDU_EXTENSION_17_BUF5_LEN 744 745 Length of the sixth buffer <legal all> 746 */ 747 #define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 748 #define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 749 #define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 750 751 752 #endif // _TX_MSDU_EXTENSION_H_ 753