1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 8/13/2018 22 // User Name:pparekh 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __WCSS_SEQ_BASE_H__ 29 #define __WCSS_SEQ_BASE_H__ 30 31 #ifdef SCALE_INCLUDES 32 #include "HALhwio.h" 33 #else 34 #include "msmhwio.h" 35 #endif 36 37 #ifndef SOC_WCSS_BASE_ADDR 38 #if defined(WCSS_BASE) 39 #if ( WCSS_BASE != 0xC000000 ) 40 #error WCSS_BASE incorrectly redefined! 41 #endif 42 #endif 43 #define SOC_WCSS_BASE_ADDR 0x000000 44 #else 45 #endif 46 47 /////////////////////////////////////////////////////////////////////////////////////////////// 48 // Instance Relative Offsets from Block wcss 49 /////////////////////////////////////////////////////////////////////////////////////////////// 50 51 #define SEQ_WCSS_ECAHB_OFFSET 0x00008400 52 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 53 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 54 #define SEQ_WCSS_PHYA_OFFSET 0x00400000 55 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 56 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 57 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 58 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 59 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 60 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 61 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 62 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00481800 63 #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00481c00 64 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC5_REG_MAP_OFFSET 0x00482c00 65 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00484000 66 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 67 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 68 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 69 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 70 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00530000 71 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 72 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 73 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_AO_SYSCTRL_OFFSET 0x005c1000 74 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_AO_TLMM_OFFSET 0x005c1400 75 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_AO_OVERRIDE_REG_OFFSET 0x005c1800 76 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_CM_TLMM_OFFSET 0x005c2000 77 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_CM_TRC_OFFSET 0x005c2200 78 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_HZ_COEX_LTE_REG_OFFSET 0x005c7000 79 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_PMU_OFFSET 0x005cb000 80 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_OFFSET 0x005cc000 81 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x005ceb00 82 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x005cc000 83 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x005d0000 84 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 85 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 86 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x005d4240 87 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d42c0 88 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 89 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4400 90 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4480 91 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 92 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d4c00 93 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x005d5000 94 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x005d5400 95 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 96 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 97 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6100 98 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6140 99 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6180 100 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d61c0 101 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6280 102 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 103 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 104 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6900 105 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6940 106 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6980 107 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d69c0 108 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a80 109 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x005d7000 110 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x005d7040 111 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x005d7100 112 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x005d7140 113 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x005d7180 114 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x005d71c0 115 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x005d7280 116 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 117 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000 118 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x005dc000 119 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005de800 120 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x005de980 121 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005de9c0 122 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x005deac0 123 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TX_OFFSET 0x005dec00 124 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH0_OFFSET 0x005df000 125 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH1_OFFSET 0x005df200 126 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dfc00 127 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40 128 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dfc80 129 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dfcc0 130 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 131 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000 132 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x005e0400 133 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x005e0800 134 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000 135 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300 136 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e2000 137 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x005e2400 138 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x005e2580 139 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x005e25c0 140 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x005e26c0 141 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x005e2734 142 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x005e2740 143 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x005e2800 144 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x005e2840 145 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x005e2880 146 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x005e28c0 147 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x005e2900 148 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x005e299c 149 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000 150 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000 151 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x005e8400 152 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x005e8800 153 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000 154 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300 155 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000 156 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x005ea400 157 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x005ea580 158 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x005ea5c0 159 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x005ea6c0 160 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x005ea734 161 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x005ea740 162 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x005ea800 163 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x005ea840 164 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x005ea880 165 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x005ea8c0 166 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x005ea900 167 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x005ea99c 168 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000 169 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x005f0000 170 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x005f0400 171 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x005f0800 172 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x005f1000 173 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300 174 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000 175 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x005f2400 176 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_OFFSET 0x005f2500 177 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x005f2580 178 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x005f25c0 179 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x005f26c0 180 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x005f2734 181 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x005f2740 182 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x005f2800 183 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x005f2840 184 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x005f2880 185 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x005f28c0 186 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x005f2900 187 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x005f299c 188 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x005f2c00 189 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x005f4000 190 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000 191 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x005f8400 192 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x005f8800 193 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x005f9000 194 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9300 195 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x005fa000 196 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x005fa400 197 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x005fa580 198 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x005fa5c0 199 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x005fa6c0 200 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x005fa734 201 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x005fa740 202 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x005fa800 203 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x005fa840 204 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x005fa880 205 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x005fa8c0 206 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x005fa900 207 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x005fa99c 208 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x005fc000 209 #define SEQ_WCSS_PHYB_OFFSET 0x00600000 210 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00600000 211 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00680000 212 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00680400 213 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00680800 214 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00680c00 215 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00681000 216 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00681400 217 #define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00681800 218 #define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00681c00 219 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET 0x00682c00 220 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00684000 221 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00688000 222 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00700000 223 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00720000 224 #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00728000 225 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00730000 226 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x007a0000 227 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x007c0000 228 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_AO_SYSCTRL_OFFSET 0x007c1000 229 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_AO_TLMM_OFFSET 0x007c1400 230 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_AO_OVERRIDE_REG_OFFSET 0x007c1800 231 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_CM_TLMM_OFFSET 0x007c2000 232 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_CM_TRC_OFFSET 0x007c2200 233 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_HZ_COEX_LTE_REG_OFFSET 0x007c7000 234 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_PMU_OFFSET 0x007cb000 235 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_OFFSET 0x007cc000 236 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x007ceb00 237 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x007cc000 238 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x007d0000 239 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x007d4000 240 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000 241 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x007d4240 242 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x007d42c0 243 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4300 244 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x007d4400 245 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x007d4480 246 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4800 247 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x007d4c00 248 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x007d5000 249 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x007d5400 250 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 251 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 252 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6100 253 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d6140 254 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6180 255 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d61c0 256 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x007d6280 257 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 258 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 259 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d6900 260 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d6940 261 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6980 262 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d69c0 263 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a80 264 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x007d7000 265 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x007d7040 266 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x007d7100 267 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x007d7140 268 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x007d7180 269 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x007d71c0 270 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x007d7280 271 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x007d7c00 272 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET 0x007dc000 273 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x007dc000 274 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x007de800 275 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x007de980 276 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x007de9c0 277 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x007deac0 278 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_TX_OFFSET 0x007dec00 279 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_RX_CH0_OFFSET 0x007df000 280 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_RX_CH1_OFFSET 0x007df200 281 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x007dfc00 282 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x007dfc40 283 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x007dfc80 284 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x007dfcc0 285 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x007e0000 286 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x007e0000 287 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x007e0400 288 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x007e0800 289 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x007e1000 290 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x007e1300 291 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x007e2000 292 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x007e2400 293 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x007e2580 294 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x007e25c0 295 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x007e26c0 296 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x007e2734 297 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x007e2740 298 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x007e2800 299 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x007e2840 300 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x007e2880 301 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x007e28c0 302 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x007e2900 303 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x007e299c 304 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x007e4000 305 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x007e8000 306 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x007e8400 307 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x007e8800 308 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x007e9000 309 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x007e9300 310 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x007ea000 311 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x007ea400 312 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x007ea580 313 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x007ea5c0 314 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x007ea6c0 315 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x007ea734 316 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x007ea740 317 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x007ea800 318 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x007ea840 319 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x007ea880 320 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x007ea8c0 321 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x007ea900 322 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x007ea99c 323 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x007ec000 324 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x007f0000 325 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x007f0400 326 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x007f0800 327 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x007f1000 328 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x007f1300 329 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x007f2000 330 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x007f2400 331 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_OFFSET 0x007f2500 332 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x007f2580 333 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x007f25c0 334 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x007f26c0 335 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x007f2734 336 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x007f2740 337 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x007f2800 338 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x007f2840 339 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x007f2880 340 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x007f28c0 341 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x007f2900 342 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x007f299c 343 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x007f2c00 344 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x007f4000 345 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x007f8000 346 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x007f8400 347 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x007f8800 348 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x007f9000 349 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x007f9300 350 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x007fa000 351 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x007fa400 352 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x007fa580 353 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x007fa5c0 354 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x007fa6c0 355 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x007fa734 356 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x007fa740 357 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x007fa800 358 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x007fa840 359 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x007fa880 360 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x007fa8c0 361 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x007fa900 362 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x007fa99c 363 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x007fc000 364 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 365 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 366 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 367 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 368 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 369 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 370 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 371 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 372 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 373 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 374 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 375 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 376 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 377 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 378 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 379 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 380 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 381 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 382 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 383 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 384 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 385 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 386 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 387 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 388 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 389 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 390 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 391 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 392 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 393 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 394 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 395 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 396 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 397 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 398 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 399 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 400 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 401 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 402 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 403 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 404 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_CE_REG_OFFSET 0x00a47000 405 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 406 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 407 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 408 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 409 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 410 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 411 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 412 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 413 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 414 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 415 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 416 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 417 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 418 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 419 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 420 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 421 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 422 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 423 #define SEQ_WCSS_WMAC1_OFFSET 0x00b00000 424 #define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00b00000 425 #define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00b03000 426 #define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00b06000 427 #define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00b09000 428 #define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00b0c000 429 #define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00b0f000 430 #define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00b12000 431 #define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00b15000 432 #define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 433 #define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00b1b000 434 #define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00b1e000 435 #define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 436 #define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00b24000 437 #define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00b27000 438 #define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00b2a000 439 #define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00b30000 440 #define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00b33000 441 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 442 #define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 443 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 444 #define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 445 #define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b80000 446 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 447 #define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000 448 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 449 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 450 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 451 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 452 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 453 #define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00ba0000 454 #define SEQ_WCSS_DBG_TPDM_OFFSET 0x00ba1000 455 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00ba1280 456 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00ba1000 457 #define SEQ_WCSS_DBG_TPDA_OFFSET 0x00ba2000 458 #define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00ba3000 459 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00ba4000 460 #define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00ba6000 461 #define SEQ_WCSS_DBG_UMACDMUX_ATB_DEMUX_OFFSET 0x00ba7000 462 #define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00ba8000 463 #define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00ba9000 464 #define SEQ_WCSS_DBG_UMAC_UMAC_DBG_OFFSET 0x00bb0000 465 #define SEQ_WCSS_DBG_UMAC_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00bb0000 466 #define SEQ_WCSS_DBG_UMAC_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb8000 467 #define SEQ_WCSS_DBG_UMAC_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00bb9000 468 #define SEQ_WCSS_DBG_UMAC_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x00bba000 469 #define SEQ_WCSS_DBG_UMAC_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x00bbb000 470 #define SEQ_WCSS_DBG_UMAC_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x00bbc000 471 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00bc0000 472 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00bc0000 473 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc4000 474 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00bc5000 475 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00bc6000 476 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00bc8000 477 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00bc9000 478 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET 0x00bca000 479 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET 0x00bcb000 480 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x00bcc000 481 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bcd000 482 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bce000 483 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_OFFSET 0x00bd0000 484 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_PHYB_NOC_OFFSET 0x00bd0000 485 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bd4000 486 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00bd5000 487 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00bd6000 488 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_ITM_OFFSET 0x00bd8000 489 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_DWT_OFFSET 0x00bd9000 490 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_FPB_OFFSET 0x00bda000 491 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_SCS_OFFSET 0x00bdb000 492 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_ETM_OFFSET 0x00bdc000 493 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bdd000 494 #define SEQ_WCSS_DBG_PHYB_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bde000 495 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c01000 496 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 497 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 498 #define SEQ_WCSS_CC_OFFSET 0x00c30000 499 #define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00c40000 500 #define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 501 #define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 502 #define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 503 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000 504 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000 505 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 506 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000 507 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000 508 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000 509 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 510 511 512 /////////////////////////////////////////////////////////////////////////////////////////////// 513 // Instance Relative Offsets from Block wfax_top 514 /////////////////////////////////////////////////////////////////////////////////////////////// 515 516 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 517 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 518 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 519 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 520 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 521 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 522 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 523 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 524 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 525 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC5_REG_MAP_OFFSET 0x00082c00 526 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000 527 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000 528 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 529 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000 530 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 531 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00130000 532 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 533 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000 534 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_AO_SYSCTRL_OFFSET 0x001c1000 535 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_AO_TLMM_OFFSET 0x001c1400 536 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_AO_OVERRIDE_REG_OFFSET 0x001c1800 537 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_CM_TLMM_OFFSET 0x001c2000 538 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_CM_TRC_OFFSET 0x001c2200 539 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_HZ_COEX_LTE_REG_OFFSET 0x001c7000 540 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_PMU_OFFSET 0x001cb000 541 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_OFFSET 0x001cc000 542 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x001ceb00 543 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x001cc000 544 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x001d0000 545 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000 546 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 547 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x001d4240 548 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x001d42c0 549 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 550 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x001d4400 551 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x001d4480 552 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 553 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00 554 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x001d5000 555 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400 556 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 557 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 558 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6100 559 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6140 560 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6180 561 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d61c0 562 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6280 563 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 564 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 565 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6900 566 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6940 567 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6980 568 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d69c0 569 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a80 570 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x001d7000 571 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x001d7040 572 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x001d7100 573 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x001d7140 574 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x001d7180 575 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x001d71c0 576 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x001d7280 577 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x001d7c00 578 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x001dc000 579 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x001dc000 580 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x001de800 581 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x001de980 582 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x001de9c0 583 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x001deac0 584 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TX_OFFSET 0x001dec00 585 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH0_OFFSET 0x001df000 586 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RX_CH1_OFFSET 0x001df200 587 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x001dfc00 588 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dfc40 589 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x001dfc80 590 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x001dfcc0 591 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000 592 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x001e0000 593 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400 594 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800 595 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000 596 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300 597 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000 598 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400 599 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580 600 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x001e25c0 601 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x001e26c0 602 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x001e2734 603 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x001e2740 604 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x001e2800 605 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x001e2840 606 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x001e2880 607 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x001e28c0 608 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x001e2900 609 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x001e299c 610 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x001e4000 611 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x001e8000 612 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400 613 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800 614 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9000 615 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9300 616 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000 617 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400 618 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580 619 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x001ea5c0 620 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x001ea6c0 621 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x001ea734 622 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x001ea740 623 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x001ea800 624 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x001ea840 625 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x001ea880 626 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x001ea8c0 627 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x001ea900 628 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x001ea99c 629 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x001ec000 630 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x001f0000 631 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400 632 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800 633 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000 634 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300 635 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000 636 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400 637 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_OFFSET 0x001f2500 638 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580 639 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x001f25c0 640 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x001f26c0 641 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x001f2734 642 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x001f2740 643 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x001f2800 644 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x001f2840 645 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x001f2880 646 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x001f28c0 647 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x001f2900 648 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x001f299c 649 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x001f2c00 650 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000 651 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000 652 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400 653 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800 654 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9000 655 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9300 656 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000 657 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400 658 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580 659 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x001fa5c0 660 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x001fa6c0 661 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x001fa734 662 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x001fa740 663 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x001fa800 664 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x001fa840 665 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x001fa880 666 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x001fa8c0 667 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x001fa900 668 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x001fa99c 669 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x001fc000 670 671 672 /////////////////////////////////////////////////////////////////////////////////////////////// 673 // Instance Relative Offsets from Block rfa_from_wsi 674 /////////////////////////////////////////////////////////////////////////////////////////////// 675 676 #define SEQ_RFA_FROM_WSI_AO_SYSCTRL_OFFSET 0x00001000 677 #define SEQ_RFA_FROM_WSI_AO_TLMM_OFFSET 0x00001400 678 #define SEQ_RFA_FROM_WSI_AO_OVERRIDE_REG_OFFSET 0x00001800 679 #define SEQ_RFA_FROM_WSI_CM_TLMM_OFFSET 0x00002000 680 #define SEQ_RFA_FROM_WSI_CM_TRC_OFFSET 0x00002200 681 #define SEQ_RFA_FROM_WSI_HZ_COEX_LTE_REG_OFFSET 0x00007000 682 #define SEQ_RFA_FROM_WSI_PMU_OFFSET 0x0000b000 683 #define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_OFFSET 0x0000c000 684 #define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x0000eb00 685 #define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x0000c000 686 #define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x00010000 687 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 688 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 689 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240 690 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0 691 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 692 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400 693 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480 694 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 695 #define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00014c00 696 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_OFFSET 0x00015000 697 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00015400 698 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 699 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 700 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100 701 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140 702 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180 703 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0 704 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016280 705 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 706 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 707 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016900 708 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016940 709 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016980 710 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000169c0 711 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a80 712 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x00017000 713 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x00017040 714 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x00017100 715 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x00017140 716 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00017180 717 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000171c0 718 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00017280 719 #define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 720 #define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 721 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET 0x0001c000 722 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001e800 723 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET 0x0001e980 724 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x0001e9c0 725 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET 0x0001eac0 726 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_TX_OFFSET 0x0001ec00 727 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RX_CH0_OFFSET 0x0001f000 728 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RX_CH1_OFFSET 0x0001f200 729 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001fc00 730 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001fc40 731 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001fc80 732 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001fcc0 733 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 734 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000 735 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x00020400 736 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x00020800 737 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000 738 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300 739 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00022000 740 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x00022400 741 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x00022580 742 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x000225c0 743 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x000226c0 744 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x00022734 745 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x00022740 746 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x00022800 747 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x00022840 748 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x00022880 749 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x000228c0 750 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x00022900 751 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x0002299c 752 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000 753 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000 754 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x00028400 755 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x00028800 756 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000 757 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300 758 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000 759 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x0002a400 760 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x0002a580 761 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x0002a5c0 762 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x0002a6c0 763 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x0002a734 764 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x0002a740 765 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x0002a800 766 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x0002a840 767 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x0002a880 768 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x0002a8c0 769 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x0002a900 770 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x0002a99c 771 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000 772 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00030000 773 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x00030400 774 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x00030800 775 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00031000 776 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00031300 777 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00032000 778 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x00032400 779 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_OFFSET 0x00032500 780 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x00032580 781 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x000325c0 782 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x000326c0 783 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x00032734 784 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x00032740 785 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x00032800 786 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x00032840 787 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x00032880 788 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x000328c0 789 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x00032900 790 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x0003299c 791 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_CAL_CORE_OFFSET 0x00032c00 792 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00034000 793 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00038000 794 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00038400 795 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x00038800 796 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00039000 797 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00039300 798 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0003a000 799 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x0003a400 800 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x0003a580 801 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x0003a5c0 802 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x0003a6c0 803 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x0003a734 804 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x0003a740 805 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x0003a800 806 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x0003a840 807 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x0003a880 808 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x0003a8c0 809 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x0003a900 810 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x0003a99c 811 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0003c000 812 813 814 /////////////////////////////////////////////////////////////////////////////////////////////// 815 // Instance Relative Offsets from Block security_control_bt 816 /////////////////////////////////////////////////////////////////////////////////////////////// 817 818 #define SEQ_SECURITY_CONTROL_BT_BT_SECURITY_CONTROL_CORE_OFFSET 0x00002b00 819 #define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_RAW_FUSE_OFFSET 0x00000000 820 #define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_CORR_FUSE_OFFSET 0x00004000 821 822 823 /////////////////////////////////////////////////////////////////////////////////////////////// 824 // Instance Relative Offsets from Block rfa_cmn 825 /////////////////////////////////////////////////////////////////////////////////////////////// 826 827 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 828 #define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240 829 #define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0 830 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 831 #define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400 832 #define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480 833 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 834 #define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00000c00 835 #define SEQ_RFA_CMN_BBPLL_OFFSET 0x00001000 836 #define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00001400 837 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 838 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 839 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100 840 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140 841 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180 842 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0 843 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002280 844 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 845 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 846 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002900 847 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002940 848 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002980 849 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000029c0 850 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a80 851 #define SEQ_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x00003000 852 #define SEQ_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x00003040 853 #define SEQ_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x00003100 854 #define SEQ_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x00003140 855 #define SEQ_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00003180 856 #define SEQ_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000031c0 857 #define SEQ_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00003280 858 #define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 859 860 861 /////////////////////////////////////////////////////////////////////////////////////////////// 862 // Instance Relative Offsets from Block rfa_bt 863 /////////////////////////////////////////////////////////////////////////////////////////////// 864 865 #define SEQ_RFA_BT_BT_TOP_OFFSET 0x00000000 866 #define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x00002800 867 #define SEQ_RFA_BT_BT_DAC_OFFSET 0x00002980 868 #define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x000029c0 869 #define SEQ_RFA_BT_BT_DAC_MISC_OFFSET 0x00002ac0 870 #define SEQ_RFA_BT_BT_TX_OFFSET 0x00002c00 871 #define SEQ_RFA_BT_BT_RX_CH0_OFFSET 0x00003000 872 #define SEQ_RFA_BT_BT_RX_CH1_OFFSET 0x00003200 873 #define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00003c00 874 #define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00003c40 875 #define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00003c80 876 #define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x00003cc0 877 878 879 /////////////////////////////////////////////////////////////////////////////////////////////// 880 // Instance Relative Offsets from Block rfa_wl 881 /////////////////////////////////////////////////////////////////////////////////////////////// 882 883 #define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000 884 #define SEQ_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x00000400 885 #define SEQ_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x00000800 886 #define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000 887 #define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300 888 #define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00002000 889 #define SEQ_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x00002400 890 #define SEQ_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x00002580 891 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x000025c0 892 #define SEQ_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x000026c0 893 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x00002734 894 #define SEQ_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x00002740 895 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x00002800 896 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x00002840 897 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x00002880 898 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x000028c0 899 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x00002900 900 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x0000299c 901 #define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000 902 #define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000 903 #define SEQ_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x00008400 904 #define SEQ_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x00008800 905 #define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000 906 #define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300 907 #define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000 908 #define SEQ_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x0000a400 909 #define SEQ_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x0000a580 910 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x0000a5c0 911 #define SEQ_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x0000a6c0 912 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x0000a734 913 #define SEQ_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x0000a740 914 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x0000a800 915 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x0000a840 916 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x0000a880 917 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x0000a8c0 918 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x0000a900 919 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x0000a99c 920 #define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000 921 #define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00010000 922 #define SEQ_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x00010400 923 #define SEQ_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x00010800 924 #define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00011000 925 #define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00011300 926 #define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00012000 927 #define SEQ_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x00012400 928 #define SEQ_RFA_WL_RBIST_RX_OFFSET 0x00012500 929 #define SEQ_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x00012580 930 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x000125c0 931 #define SEQ_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x000126c0 932 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x00012734 933 #define SEQ_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x00012740 934 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x00012800 935 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x00012840 936 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x00012880 937 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x000128c0 938 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x00012900 939 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x0001299c 940 #define SEQ_RFA_WL_WL_CAL_CORE_OFFSET 0x00012c00 941 #define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00014000 942 #define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00018000 943 #define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00018400 944 #define SEQ_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x00018800 945 #define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00019000 946 #define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00019300 947 #define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0001a000 948 #define SEQ_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x0001a400 949 #define SEQ_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x0001a580 950 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x0001a5c0 951 #define SEQ_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x0001a6c0 952 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x0001a734 953 #define SEQ_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x0001a740 954 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x0001a800 955 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x0001a840 956 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x0001a880 957 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x0001a8c0 958 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x0001a900 959 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x0001a99c 960 #define SEQ_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0001c000 961 962 963 /////////////////////////////////////////////////////////////////////////////////////////////// 964 // Instance Relative Offsets from Block wfax_top_b 965 /////////////////////////////////////////////////////////////////////////////////////////////// 966 967 #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 968 #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 969 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 970 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 971 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 972 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 973 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 974 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00081800 975 #define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00081c00 976 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET 0x00082c00 977 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 978 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 979 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 980 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 981 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 982 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00130000 983 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 984 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 985 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_AO_SYSCTRL_OFFSET 0x001c1000 986 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_AO_TLMM_OFFSET 0x001c1400 987 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_AO_OVERRIDE_REG_OFFSET 0x001c1800 988 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_CM_TLMM_OFFSET 0x001c2000 989 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_CM_TRC_OFFSET 0x001c2200 990 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_HZ_COEX_LTE_REG_OFFSET 0x001c7000 991 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_PMU_OFFSET 0x001cb000 992 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_OFFSET 0x001cc000 993 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x001ceb00 994 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x001cc000 995 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x001d0000 996 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 997 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 998 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x001d4240 999 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x001d42c0 1000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 1001 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x001d4400 1002 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x001d4480 1003 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 1004 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00 1005 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x001d5000 1006 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400 1007 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 1008 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 1009 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6100 1010 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6140 1011 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6180 1012 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d61c0 1013 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6280 1014 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 1015 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 1016 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6900 1017 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6940 1018 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6980 1019 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d69c0 1020 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a80 1021 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x001d7000 1022 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x001d7040 1023 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x001d7100 1024 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x001d7140 1025 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x001d7180 1026 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x001d71c0 1027 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x001d7280 1028 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x001d7c00 1029 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET 0x001dc000 1030 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x001dc000 1031 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x001de800 1032 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x001de980 1033 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x001de9c0 1034 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x001deac0 1035 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_TX_OFFSET 0x001dec00 1036 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_RX_CH0_OFFSET 0x001df000 1037 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_RX_CH1_OFFSET 0x001df200 1038 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x001dfc00 1039 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dfc40 1040 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x001dfc80 1041 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x001dfcc0 1042 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 1043 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x001e0000 1044 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400 1045 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800 1046 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000 1047 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300 1048 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000 1049 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400 1050 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580 1051 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x001e25c0 1052 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x001e26c0 1053 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET 0x001e2734 1054 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x001e2740 1055 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x001e2800 1056 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET 0x001e2840 1057 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x001e2880 1058 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET 0x001e28c0 1059 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET 0x001e2900 1060 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET 0x001e299c 1061 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x001e4000 1062 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x001e8000 1063 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400 1064 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800 1065 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9000 1066 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9300 1067 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000 1068 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400 1069 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580 1070 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x001ea5c0 1071 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x001ea6c0 1072 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET 0x001ea734 1073 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x001ea740 1074 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x001ea800 1075 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET 0x001ea840 1076 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x001ea880 1077 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET 0x001ea8c0 1078 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET 0x001ea900 1079 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET 0x001ea99c 1080 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x001ec000 1081 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x001f0000 1082 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400 1083 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800 1084 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000 1085 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300 1086 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000 1087 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400 1088 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_OFFSET 0x001f2500 1089 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580 1090 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x001f25c0 1091 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x001f26c0 1092 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET 0x001f2734 1093 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x001f2740 1094 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x001f2800 1095 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET 0x001f2840 1096 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x001f2880 1097 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x001f28c0 1098 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x001f2900 1099 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x001f299c 1100 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x001f2c00 1101 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000 1102 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000 1103 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400 1104 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800 1105 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9000 1106 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9300 1107 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000 1108 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400 1109 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580 1110 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x001fa5c0 1111 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x001fa6c0 1112 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET 0x001fa734 1113 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x001fa740 1114 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x001fa800 1115 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET 0x001fa840 1116 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x001fa880 1117 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET 0x001fa8c0 1118 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET 0x001fa900 1119 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET 0x001fa99c 1120 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x001fc000 1121 1122 1123 /////////////////////////////////////////////////////////////////////////////////////////////// 1124 // Instance Relative Offsets from Block umac_top_reg 1125 /////////////////////////////////////////////////////////////////////////////////////////////// 1126 1127 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 1128 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 1129 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 1130 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 1131 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 1132 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 1133 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 1134 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 1135 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 1136 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 1137 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 1138 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 1139 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 1140 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 1141 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 1142 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 1143 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 1144 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 1145 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 1146 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 1147 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 1148 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 1149 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 1150 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 1151 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 1152 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 1153 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 1154 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 1155 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 1156 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 1157 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 1158 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 1159 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 1160 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 1161 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 1162 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 1163 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 1164 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 1165 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 1166 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_CE_REG_OFFSET 0x00047000 1167 1168 1169 /////////////////////////////////////////////////////////////////////////////////////////////// 1170 // Instance Relative Offsets from Block wfss_ce_reg 1171 /////////////////////////////////////////////////////////////////////////////////////////////// 1172 1173 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 1174 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 1175 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 1176 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 1177 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 1178 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 1179 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 1180 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 1181 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 1182 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 1183 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 1184 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 1185 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 1186 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 1187 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 1188 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 1189 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 1190 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 1191 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 1192 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 1193 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 1194 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 1195 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 1196 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 1197 #define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 1198 1199 1200 /////////////////////////////////////////////////////////////////////////////////////////////// 1201 // Instance Relative Offsets from Block cxc_top_reg 1202 /////////////////////////////////////////////////////////////////////////////////////////////// 1203 1204 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 1205 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 1206 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 1207 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 1208 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 1209 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 1210 1211 1212 /////////////////////////////////////////////////////////////////////////////////////////////// 1213 // Instance Relative Offsets from Block wmac_top_reg 1214 /////////////////////////////////////////////////////////////////////////////////////////////// 1215 1216 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 1217 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 1218 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 1219 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 1220 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 1221 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 1222 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 1223 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 1224 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 1225 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 1226 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 1227 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 1228 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 1229 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 1230 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 1231 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 1232 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 1233 1234 1235 /////////////////////////////////////////////////////////////////////////////////////////////// 1236 // Instance Relative Offsets from Block wcssdbg 1237 /////////////////////////////////////////////////////////////////////////////////////////////// 1238 1239 #define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000 1240 #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 1241 #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 1242 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 1243 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 1244 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 1245 #define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00010000 1246 #define SEQ_WCSSDBG_TPDM_OFFSET 0x00011000 1247 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00011280 1248 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00011000 1249 #define SEQ_WCSSDBG_TPDA_OFFSET 0x00012000 1250 #define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x00013000 1251 #define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x00014000 1252 #define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00016000 1253 #define SEQ_WCSSDBG_UMACDMUX_ATB_DEMUX_OFFSET 0x00017000 1254 #define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00018000 1255 #define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00019000 1256 #define SEQ_WCSSDBG_UMAC_UMAC_DBG_OFFSET 0x00020000 1257 #define SEQ_WCSSDBG_UMAC_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00020000 1258 #define SEQ_WCSSDBG_UMAC_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00028000 1259 #define SEQ_WCSSDBG_UMAC_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00029000 1260 #define SEQ_WCSSDBG_UMAC_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x0002a000 1261 #define SEQ_WCSSDBG_UMAC_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x0002b000 1262 #define SEQ_WCSSDBG_UMAC_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x0002c000 1263 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00030000 1264 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00030000 1265 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00034000 1266 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00035000 1267 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00036000 1268 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00038000 1269 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00039000 1270 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET 0x0003a000 1271 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET 0x0003b000 1272 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x0003c000 1273 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0003d000 1274 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0003e000 1275 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_OFFSET 0x00040000 1276 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_PHYB_NOC_OFFSET 0x00040000 1277 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00044000 1278 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00045000 1279 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00046000 1280 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_ITM_OFFSET 0x00048000 1281 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_DWT_OFFSET 0x00049000 1282 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_FPB_OFFSET 0x0004a000 1283 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_SCS_OFFSET 0x0004b000 1284 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_ETM_OFFSET 0x0004c000 1285 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0004d000 1286 #define SEQ_WCSSDBG_PHYB_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0004e000 1287 #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x00071000 1288 1289 1290 /////////////////////////////////////////////////////////////////////////////////////////////// 1291 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 1292 /////////////////////////////////////////////////////////////////////////////////////////////// 1293 1294 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 1295 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 1296 1297 1298 /////////////////////////////////////////////////////////////////////////////////////////////// 1299 // Instance Relative Offsets from Block umac_dbg 1300 /////////////////////////////////////////////////////////////////////////////////////////////// 1301 1302 #define SEQ_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00000000 1303 #define SEQ_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00008000 1304 #define SEQ_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00009000 1305 #define SEQ_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x0000a000 1306 #define SEQ_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x0000b000 1307 #define SEQ_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x0000c000 1308 1309 1310 /////////////////////////////////////////////////////////////////////////////////////////////// 1311 // Instance Relative Offsets from Block phya_dbg 1312 /////////////////////////////////////////////////////////////////////////////////////////////// 1313 1314 #define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 1315 #define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 1316 #define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 1317 #define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 1318 #define SEQ_PHYA_DBG_ITM_OFFSET 0x00008000 1319 #define SEQ_PHYA_DBG_DWT_OFFSET 0x00009000 1320 #define SEQ_PHYA_DBG_FPB_OFFSET 0x0000a000 1321 #define SEQ_PHYA_DBG_SCS_OFFSET 0x0000b000 1322 #define SEQ_PHYA_DBG_M3_ETM_OFFSET 0x0000c000 1323 #define SEQ_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 1324 #define SEQ_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 1325 1326 1327 /////////////////////////////////////////////////////////////////////////////////////////////// 1328 // Instance Relative Offsets from Block phyb_dbg 1329 /////////////////////////////////////////////////////////////////////////////////////////////// 1330 1331 #define SEQ_PHYB_DBG_PHYB_NOC_OFFSET 0x00000000 1332 #define SEQ_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 1333 #define SEQ_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 1334 #define SEQ_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 1335 #define SEQ_PHYB_DBG_ITM_OFFSET 0x00008000 1336 #define SEQ_PHYB_DBG_DWT_OFFSET 0x00009000 1337 #define SEQ_PHYB_DBG_FPB_OFFSET 0x0000a000 1338 #define SEQ_PHYB_DBG_SCS_OFFSET 0x0000b000 1339 #define SEQ_PHYB_DBG_ETM_OFFSET 0x0000c000 1340 #define SEQ_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 1341 #define SEQ_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 1342 1343 1344 /////////////////////////////////////////////////////////////////////////////////////////////// 1345 // Instance Relative Offsets from Block qdsp6ss_public 1346 /////////////////////////////////////////////////////////////////////////////////////////////// 1347 1348 #define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET 0x00000000 1349 1350 1351 /////////////////////////////////////////////////////////////////////////////////////////////// 1352 // Instance Relative Offsets from Block qdsp6ss_private 1353 /////////////////////////////////////////////////////////////////////////////////////////////// 1354 1355 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET 0x00000000 1356 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET 0x00010000 1357 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 1358 #define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 1359 #define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 1360 #define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 1361 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET 0x00030000 1362 1363 1364 #endif 1365 1366