1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_DESTINATION_RING_H_ 25 #define _REO_DESTINATION_RING_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "buffer_addr_info.h" 30 #include "rx_mpdu_desc_info.h" 31 #include "rx_msdu_desc_info.h" 32 33 // ################ START SUMMARY ################# 34 // 35 // Dword Fields 36 // 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; 37 // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 38 // 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; 39 // 6 rx_reo_queue_desc_addr_31_0[31:0] 40 // 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] 41 // 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], captured_msdu_data_size[20:17], sw_exception[21], reserved_8a[31:22] 42 // 9 reo_destination_struct_signature[31:0] 43 // 10 reserved_10a[31:0] 44 // 11 reserved_11a[31:0] 45 // 12 reserved_12a[31:0] 46 // 13 reserved_13a[31:0] 47 // 14 reserved_14a[31:0] 48 // 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] 49 // 50 // ################ END SUMMARY ################# 51 52 #define NUM_OF_DWORDS_REO_DESTINATION_RING 16 53 54 struct reo_destination_ring { 55 struct buffer_addr_info buf_or_link_desc_addr_info; 56 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 57 struct rx_msdu_desc_info rx_msdu_desc_info_details; 58 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 59 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 60 reo_dest_buffer_type : 1, //[8] 61 reo_push_reason : 2, //[10:9] 62 reo_error_code : 5, //[15:11] 63 receive_queue_number : 16; //[31:16] 64 uint32_t soft_reorder_info_valid : 1, //[0] 65 reorder_opcode : 4, //[4:1] 66 reorder_slot_index : 8, //[12:5] 67 mpdu_fragment_number : 4, //[16:13] 68 captured_msdu_data_size : 4, //[20:17] 69 sw_exception : 1, //[21] 70 reserved_8a : 10; //[31:22] 71 uint32_t reo_destination_struct_signature: 32; //[31:0] 72 uint32_t reserved_10a : 32; //[31:0] 73 uint32_t reserved_11a : 32; //[31:0] 74 uint32_t reserved_12a : 32; //[31:0] 75 uint32_t reserved_13a : 32; //[31:0] 76 uint32_t reserved_14a : 32; //[31:0] 77 uint32_t reserved_15 : 20, //[19:0] 78 ring_id : 8, //[27:20] 79 looping_count : 4; //[31:28] 80 }; 81 82 /* 83 84 struct buffer_addr_info buf_or_link_desc_addr_info 85 86 Consumer: REO/SW/FW 87 88 Producer: RXDMA 89 90 91 92 Details of the physical address of the a buffer or MSDU 93 link descriptor 94 95 struct rx_mpdu_desc_info rx_mpdu_desc_info_details 96 97 Consumer: REO/SW/FW 98 99 Producer: RXDMA 100 101 102 103 General information related to the MPDU that is passed 104 on from REO entrance ring to the REO destination ring 105 106 struct rx_msdu_desc_info rx_msdu_desc_info_details 107 108 General information related to the MSDU that is passed 109 on from RXDMA all the way to to the REO destination ring. 110 111 rx_reo_queue_desc_addr_31_0 112 113 Consumer: REO 114 115 Producer: RXDMA 116 117 118 119 Address (lower 32 bits) of the REO queue descriptor. 120 121 <legal all> 122 123 rx_reo_queue_desc_addr_39_32 124 125 Consumer: REO 126 127 Producer: RXDMA 128 129 130 131 Address (upper 8 bits) of the REO queue descriptor. 132 133 <legal all> 134 135 reo_dest_buffer_type 136 137 Indicates the type of address provided in the 138 'Buf_or_link_desc_addr_info' 139 140 141 142 <enum 0 MSDU_buf_address> The address of an MSDU buffer 143 144 <enum 1 MSDU_link_desc_address> The address of the MSDU 145 link descriptor. 146 147 148 149 <legal all> 150 151 reo_push_reason 152 153 Indicates why REO pushed the frame to this exit ring 154 155 156 157 <enum 0 reo_error_detected> Reo detected an error an 158 pushed this frame to this queue 159 160 <enum 1 reo_routing_instruction> Reo pushed the frame to 161 this queue per received routing instructions. No error 162 within REO was detected 163 164 165 166 167 168 <legal 0 - 1> 169 170 reo_error_code 171 172 Field only valid when 'Reo_push_reason' set to 173 'reo_error_detected'. 174 175 176 177 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 178 provided in the REO_ENTRANCE ring is set to 0 179 180 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 181 valid bit is NOT set 182 183 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 184 session having been setup. 185 186 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 187 SSN, Retry bit set: duplicate frame 188 189 <enum 4 ba_duplicate> BA session, duplicate frame 190 191 <enum 5 regular_frame_2k_jump> A normal (management/data 192 frame) received with 2K jump in SN 193 194 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 195 in SSN 196 197 <enum 7 regular_frame_OOR> A normal (management/data 198 frame) received with SN falling within the OOR window 199 200 <enum 8 bar_frame_OOR> A bar received with SSN falling 201 within the OOR window 202 203 <enum 9 bar_frame_no_ba_session> A bar received without 204 a BA session 205 206 <enum 10 bar_frame_sn_equals_ssn> A bar received with 207 SSN equal to SN 208 209 <enum 11 pn_check_failed> PN Check Failed packet. 210 211 <enum 12 2k_error_handling_flag_set> Frame is forwarded 212 as a result of the 'Seq_2k_error_detected_flag' been set in 213 the REO Queue descriptor 214 215 <enum 13 pn_error_handling_flag_set> Frame is forwarded 216 as a result of the 'pn_error_detected_flag' been set in the 217 REO Queue descriptor 218 219 <enum 14 queue_descriptor_blocked_set> Frame is 220 forwarded as a result of the queue descriptor(address) being 221 blocked as SW/FW seems to be currently in the process of 222 making updates to this descriptor... 223 224 225 226 <legal 0-14> 227 228 receive_queue_number 229 230 This field in NOT valid (should be set to 0), when 231 SW_exception is set. 232 233 This field indicates the REO MPDU reorder queue ID from 234 which this frame originated. This field is populated from a 235 field with the same name in the RX_REO_QUEUE descriptor. 236 237 <legal all> 238 239 soft_reorder_info_valid 240 241 This field in NOT valid (should be set to 0), when 242 SW_exception is set. 243 244 When set, REO has been instructed to not perform the 245 actual re-ordering of frames for this queue, but just to 246 insert the reorder opcodes 247 248 <legal all> 249 250 reorder_opcode 251 252 Field is valid when 'Soft_reorder_info_valid' is set. 253 This field is always valid for debug purpose as well. 254 255 Details are in the MLD. 256 257 258 259 <enum 0 invalid> 260 261 <enum 1 fwdcur_fwdbuf> 262 263 <enum 2 fwdbuf_fwdcur> 264 265 <enum 3 qcur> 266 267 <enum 4 fwdbuf_qcur> 268 269 <enum 5 fwdbuf_drop> 270 271 <enum 6 fwdall_drop> 272 273 <enum 7 fwdall_qcur> 274 275 <enum 8 reserved_reo_opcode_1> 276 277 <enum 9 dropcur> the error reason code is in 278 reo_error_code field. 279 280 <enum 10 reserved_reo_opcode_2> 281 282 <enum 11 reserved_reo_opcode_3> 283 284 <enum 12 reserved_reo_opcode_4> 285 286 <enum 13 reserved_reo_opcode_5> 287 288 <enum 14 reserved_reo_opcode_6> 289 290 <enum 15 reserved_reo_opcode_7> 291 292 293 294 <legal all> 295 296 reorder_slot_index 297 298 Field only valid when 'Soft_reorder_info_valid' is set. 299 300 301 302 TODO: add description 303 304 305 306 <legal all> 307 308 mpdu_fragment_number 309 310 Field only valid when Rx_mpdu_desc_info_details. 311 Fragment_flag is set. 312 313 314 315 The fragment number from the 802.11 header. 316 317 318 319 Note that the sequence number is embedded in the field: 320 Rx_mpdu_desc_info_details. Mpdu_sequence_number 321 322 323 324 <legal all> 325 326 captured_msdu_data_size 327 328 The number of following REO_DESTINATION STRUCTs that 329 have been replaced with msdu_data extracted from the 330 msdu_buffer and copied into the ring for easy FW/SW access. 331 332 Note that it is possible that these STRUCTs wrap around 333 the end of the ring. 334 335 Feature supported only in HastingsPrime 336 337 <legal 0-4> 338 339 sw_exception 340 341 This field has the same setting as the SW_exception 342 field in the corresponding REO_entrance_ring descriptor. 343 344 When set, the REO entrance descriptor is generated by 345 FW, and the MPDU was processed in the following way: 346 347 - NO re-order function is needed. 348 349 - MPDU delinking is determined by the setting of 350 Entrance ring field: SW_excection_mpdu_delink 351 352 - Destination ring selection is based on the setting of 353 354 Feature supported only in HastingsPrime 355 356 <legal all> 357 358 reserved_8a 359 360 <legal 0> 361 362 reo_destination_struct_signature 363 364 Set to value 0x8888_88888 when msdu capture mode is 365 enabled for this ring (supported only in HastingsPrime) 366 367 <legal 0, 2290649224 > 368 369 reserved_10a 370 371 <legal 0> 372 373 reserved_11a 374 375 <legal 0> 376 377 reserved_12a 378 379 <legal 0> 380 381 reserved_13a 382 383 <legal 0> 384 385 reserved_14a 386 387 <legal 0> 388 389 reserved_15 390 391 <legal 0> 392 393 ring_id 394 395 The buffer pointer ring ID. 396 397 0 refers to the IDLE ring 398 399 1 - N refers to other rings 400 401 402 403 Helps with debugging when dumping ring contents. 404 405 <legal all> 406 407 looping_count 408 409 A count value that indicates the number of times the 410 producer of entries into this Ring has looped around the 411 ring. 412 413 At initialization time, this value is set to 0. On the 414 first loop, this value is set to 1. After the max value is 415 reached allowed by the number of bits for this field, the 416 count value continues with 0 again. 417 418 In case SW is the consumer of the ring entries, it can 419 use this field to figure out up to where the producer of 420 entries has created new entries. This eliminates the need to 421 check where the head pointer' of the ring is located once 422 the SW starts processing an interrupt indicating that new 423 entries have been put into this ring... 424 425 426 427 Also note that SW if it wants only needs to look at the 428 LSB bit of this count value. 429 430 <legal all> 431 */ 432 433 434 /* EXTERNAL REFERENCE : struct buffer_addr_info buf_or_link_desc_addr_info */ 435 436 437 /* Description REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 438 439 Address (lower 32 bits) of the MSDU buffer OR 440 MSDU_EXTENSION descriptor OR Link Descriptor 441 442 443 444 In case of 'NULL' pointer, this field is set to 0 445 446 <legal all> 447 */ 448 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 449 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 450 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 451 452 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 453 454 Address (upper 8 bits) of the MSDU buffer OR 455 MSDU_EXTENSION descriptor OR Link Descriptor 456 457 458 459 In case of 'NULL' pointer, this field is set to 0 460 461 <legal all> 462 */ 463 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 464 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 465 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 466 467 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 468 469 Consumer: WBM 470 471 Producer: SW/FW 472 473 474 475 In case of 'NULL' pointer, this field is set to 0 476 477 478 479 Indicates to which buffer manager the buffer OR 480 MSDU_EXTENSION descriptor OR link descriptor that is being 481 pointed to shall be returned after the frame has been 482 processed. It is used by WBM for routing purposes. 483 484 485 486 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 487 to the WMB buffer idle list 488 489 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 490 returned to the WMB idle link descriptor idle list 491 492 <enum 2 FW_BM> This buffer shall be returned to the FW 493 494 <enum 3 SW0_BM> This buffer shall be returned to the SW, 495 ring 0 496 497 <enum 4 SW1_BM> This buffer shall be returned to the SW, 498 ring 1 499 500 <enum 5 SW2_BM> This buffer shall be returned to the SW, 501 ring 2 502 503 <enum 6 SW3_BM> This buffer shall be returned to the SW, 504 ring 3 505 506 <enum 7 SW4_BM> This buffer shall be returned to the SW, 507 ring 4 508 509 510 511 <legal all> 512 */ 513 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 514 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 515 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 516 517 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 518 519 Cookie field exclusively used by SW. 520 521 522 523 In case of 'NULL' pointer, this field is set to 0 524 525 526 527 HW ignores the contents, accept that it passes the 528 programmed value on to other descriptors together with the 529 physical address 530 531 532 533 Field can be used by SW to for example associate the 534 buffers physical address with the virtual address 535 536 The bit definitions as used by SW are within SW HLD 537 specification 538 539 540 541 NOTE: 542 543 The three most significant bits can have a special 544 meaning in case this struct is embedded in a TX_MPDU_DETAILS 545 STRUCT, and field transmit_bw_restriction is set 546 547 548 549 In case of NON punctured transmission: 550 551 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 552 553 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 554 555 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 556 557 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 558 559 560 561 In case of punctured transmission: 562 563 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 564 565 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 566 567 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 568 569 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 570 571 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 572 573 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 574 575 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 576 577 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 578 579 580 581 Note: a punctured transmission is indicated by the 582 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 583 TLV 584 585 586 587 <legal all> 588 */ 589 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 590 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 591 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 592 593 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 594 595 596 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 597 598 Consumer: REO/SW/FW 599 600 Producer: RXDMA 601 602 603 604 The number of MSDUs within the MPDU 605 606 <legal all> 607 */ 608 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 609 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 610 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 611 612 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 613 614 Consumer: REO/SW/FW 615 616 Producer: RXDMA 617 618 619 620 The field can have two different meanings based on the 621 setting of field 'BAR_frame': 622 623 624 625 'BAR_frame' is NOT set: 626 627 The MPDU sequence number of the received frame. 628 629 630 631 'BAR_frame' is set. 632 633 The MPDU Start sequence number from the BAR frame 634 635 <legal all> 636 */ 637 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 638 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 639 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 640 641 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 642 643 Consumer: REO/SW/FW 644 645 Producer: RXDMA 646 647 648 649 When set, this MPDU is a fragment and REO should forward 650 this fragment MPDU to the REO destination ring without any 651 reorder checks, pn checks or bitmap update. This implies 652 that REO is forwarding the pointer to the MSDU link 653 descriptor. The destination ring is coming from a 654 programmable register setting in REO 655 656 657 658 <legal all> 659 */ 660 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 661 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 662 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 663 664 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 665 666 Consumer: REO/SW/FW 667 668 Producer: RXDMA 669 670 671 672 The retry bit setting from the MPDU header of the 673 received frame 674 675 <legal all> 676 */ 677 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 678 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 679 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 680 681 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 682 683 Consumer: REO/SW/FW 684 685 Producer: RXDMA 686 687 688 689 When set, the MPDU was received as part of an A-MPDU. 690 691 <legal all> 692 */ 693 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 694 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 695 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 696 697 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 698 699 Consumer: REO/SW/FW 700 701 Producer: RXDMA 702 703 704 705 When set, the received frame is a BAR frame. After 706 processing, this frame shall be pushed to SW or deleted. 707 708 <legal all> 709 */ 710 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 711 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 712 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 713 714 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 715 716 Consumer: REO/SW/FW 717 718 Producer: RXDMA 719 720 721 722 Copied here by RXDMA from RX_MPDU_END 723 724 When not set, REO will Not perform a PN sequence number 725 check 726 */ 727 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 728 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 729 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 730 731 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 732 733 When set, OLE found a valid SA entry for all MSDUs in 734 this MPDU 735 736 <legal all> 737 */ 738 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 739 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 740 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 741 742 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 743 744 When set, at least 1 MSDU within the MPDU has an 745 unsuccessful MAC source address search due to the expiration 746 of the search timer. 747 748 <legal all> 749 */ 750 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 751 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 752 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 753 754 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 755 756 When set, OLE found a valid DA entry for all MSDUs in 757 this MPDU 758 759 <legal all> 760 */ 761 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 762 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 763 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 764 765 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 766 767 Field Only valid if da_is_valid is set 768 769 770 771 When set, at least one of the DA addresses is a 772 Multicast or Broadcast address. 773 774 <legal all> 775 */ 776 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 777 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 778 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 779 780 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 781 782 When set, at least 1 MSDU within the MPDU has an 783 unsuccessful MAC destination address search due to the 784 expiration of the search timer. 785 786 <legal all> 787 */ 788 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 789 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 790 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 791 792 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 793 794 Field only valid when first_msdu_in_mpdu_flag is set. 795 796 797 798 When set, the contents in the MSDU buffer contains a 799 'RAW' MPDU. This 'RAW' MPDU might be spread out over 800 multiple MSDU buffers. 801 802 <legal all> 803 */ 804 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 805 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 806 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 807 808 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 809 810 The More Fragment bit setting from the MPDU header of 811 the received frame 812 813 814 815 <legal all> 816 */ 817 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 818 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 819 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 820 821 /* Description REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 822 823 Meta data that SW has programmed in the Peer table entry 824 of the transmitting STA. 825 826 <legal all> 827 */ 828 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 829 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 830 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 831 832 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 833 834 835 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 836 837 Parsed from RX_MSDU_END TLV . In the case MSDU spans 838 over multiple buffers, this field will be valid in the Last 839 buffer used by the MSDU 840 841 842 843 <enum 0 Not_first_msdu> This is not the first MSDU in 844 the MPDU. 845 846 <enum 1 first_msdu> This MSDU is the first one in the 847 MPDU. 848 849 850 851 <legal all> 852 */ 853 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 854 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 855 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 856 857 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 858 859 Consumer: WBM/REO/SW/FW 860 861 Producer: RXDMA 862 863 864 865 Parsed from RX_MSDU_END TLV . In the case MSDU spans 866 over multiple buffers, this field will be valid in the Last 867 buffer used by the MSDU 868 869 870 871 <enum 0 Not_last_msdu> There are more MSDUs linked to 872 this MSDU that belongs to this MPDU 873 874 <enum 1 Last_msdu> this MSDU is the last one in the 875 MPDU. This setting is only allowed in combination with 876 'Msdu_continuation' set to 0. This implies that when an msdu 877 is spread out over multiple buffers and thus 878 msdu_continuation is set, only for the very last buffer of 879 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 880 881 882 883 When both first_msdu_in_mpdu_flag and 884 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 885 belongs to only contains a single MSDU. 886 887 888 889 890 891 <legal all> 892 */ 893 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 894 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 895 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 896 897 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 898 899 When set, this MSDU buffer was not able to hold the 900 entire MSDU. The next buffer will therefor contain 901 additional information related to this MSDU. 902 903 904 905 <legal all> 906 */ 907 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 908 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 909 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 910 911 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 912 913 Parsed from RX_MSDU_START TLV . In the case MSDU spans 914 over multiple buffers, this field will be valid in the First 915 buffer used by MSDU. 916 917 918 919 Full MSDU length in bytes after decapsulation. 920 921 922 923 This field is still valid for MPDU frames without 924 A-MSDU. It still represents MSDU length after decapsulation 925 926 927 928 Or in case of RAW MPDUs, it indicates the length of the 929 entire MPDU (without FCS field) 930 931 <legal all> 932 */ 933 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 934 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 935 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 936 937 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 938 939 Parsed from RX_MSDU_END TLV . In the case MSDU spans 940 over multiple buffers, this field will be valid in the Last 941 buffer used by the MSDU 942 943 944 945 The ID of the REO exit ring where the MSDU frame shall 946 push after (MPDU level) reordering has finished. 947 948 949 950 <enum 0 reo_destination_tcl> Reo will push the frame 951 into the REO2TCL ring 952 953 <enum 1 reo_destination_sw1> Reo will push the frame 954 into the REO2SW1 ring 955 956 <enum 2 reo_destination_sw2> Reo will push the frame 957 into the REO2SW2 ring 958 959 <enum 3 reo_destination_sw3> Reo will push the frame 960 into the REO2SW3 ring 961 962 <enum 4 reo_destination_sw4> Reo will push the frame 963 into the REO2SW4 ring 964 965 <enum 5 reo_destination_release> Reo will push the frame 966 into the REO_release ring 967 968 <enum 6 reo_destination_fw> Reo will push the frame into 969 the REO2FW ring 970 971 <enum 7 reo_destination_sw5> Reo will push the frame 972 into the REO2SW5 ring 973 974 <enum 8 reo_destination_sw6> Reo will push the frame 975 into the REO2SW6 ring 976 977 <enum 9 reo_destination_9> REO remaps this <enum 10 978 reo_destination_10> REO remaps this 979 980 <enum 11 reo_destination_11> REO remaps this 981 982 <enum 12 reo_destination_12> REO remaps this <enum 13 983 reo_destination_13> REO remaps this 984 985 <enum 14 reo_destination_14> REO remaps this 986 987 <enum 15 reo_destination_15> REO remaps this 988 989 <enum 16 reo_destination_16> REO remaps this 990 991 <enum 17 reo_destination_17> REO remaps this 992 993 <enum 18 reo_destination_18> REO remaps this 994 995 <enum 19 reo_destination_19> REO remaps this 996 997 <enum 20 reo_destination_20> REO remaps this 998 999 <enum 21 reo_destination_21> REO remaps this 1000 1001 <enum 22 reo_destination_22> REO remaps this 1002 1003 <enum 23 reo_destination_23> REO remaps this 1004 1005 <enum 24 reo_destination_24> REO remaps this 1006 1007 <enum 25 reo_destination_25> REO remaps this 1008 1009 <enum 26 reo_destination_26> REO remaps this 1010 1011 <enum 27 reo_destination_27> REO remaps this 1012 1013 <enum 28 reo_destination_28> REO remaps this 1014 1015 <enum 29 reo_destination_29> REO remaps this 1016 1017 <enum 30 reo_destination_30> REO remaps this 1018 1019 <enum 31 reo_destination_31> REO remaps this 1020 1021 1022 1023 <legal all> 1024 */ 1025 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010 1026 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1027 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1028 1029 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1030 1031 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1032 over multiple buffers, this field will be valid in the Last 1033 buffer used by the MSDU 1034 1035 1036 1037 When set, REO shall drop this MSDU and not forward it to 1038 any other ring... 1039 1040 <legal all> 1041 */ 1042 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 1043 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1044 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1045 1046 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1047 1048 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1049 over multiple buffers, this field will be valid in the Last 1050 buffer used by the MSDU 1051 1052 1053 1054 Indicates that OLE found a valid SA entry for this MSDU 1055 1056 <legal all> 1057 */ 1058 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 1059 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1060 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1061 1062 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1063 1064 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1065 over multiple buffers, this field will be valid in the Last 1066 buffer used by the MSDU 1067 1068 1069 1070 Indicates an unsuccessful MAC source address search due 1071 to the expiring of the search timer for this MSDU 1072 1073 <legal all> 1074 */ 1075 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010 1076 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1077 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1078 1079 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1080 1081 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1082 over multiple buffers, this field will be valid in the Last 1083 buffer used by the MSDU 1084 1085 1086 1087 Indicates that OLE found a valid DA entry for this MSDU 1088 1089 <legal all> 1090 */ 1091 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 1092 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1093 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1094 1095 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1096 1097 Field Only valid if da_is_valid is set 1098 1099 1100 1101 Indicates the DA address was a Multicast of Broadcast 1102 address for this MSDU 1103 1104 <legal all> 1105 */ 1106 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 1107 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1108 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1109 1110 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1111 1112 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1113 over multiple buffers, this field will be valid in the Last 1114 buffer used by the MSDU 1115 1116 1117 1118 Indicates an unsuccessful MAC destination address search 1119 due to the expiring of the search timer for this MSDU 1120 1121 <legal all> 1122 */ 1123 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010 1124 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1125 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1126 1127 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1128 1129 <legal 0> 1130 */ 1131 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010 1132 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1133 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1134 1135 /* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1136 1137 <legal 0> 1138 */ 1139 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 1140 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1141 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1142 1143 /* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 1144 1145 Consumer: REO 1146 1147 Producer: RXDMA 1148 1149 1150 1151 Address (lower 32 bits) of the REO queue descriptor. 1152 1153 <legal all> 1154 */ 1155 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 1156 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 1157 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 1158 1159 /* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 1160 1161 Consumer: REO 1162 1163 Producer: RXDMA 1164 1165 1166 1167 Address (upper 8 bits) of the REO queue descriptor. 1168 1169 <legal all> 1170 */ 1171 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c 1172 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1173 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1174 1175 /* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE 1176 1177 Indicates the type of address provided in the 1178 'Buf_or_link_desc_addr_info' 1179 1180 1181 1182 <enum 0 MSDU_buf_address> The address of an MSDU buffer 1183 1184 <enum 1 MSDU_link_desc_address> The address of the MSDU 1185 link descriptor. 1186 1187 1188 1189 <legal all> 1190 */ 1191 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c 1192 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 1193 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 1194 1195 /* Description REO_DESTINATION_RING_7_REO_PUSH_REASON 1196 1197 Indicates why REO pushed the frame to this exit ring 1198 1199 1200 1201 <enum 0 reo_error_detected> Reo detected an error an 1202 pushed this frame to this queue 1203 1204 <enum 1 reo_routing_instruction> Reo pushed the frame to 1205 this queue per received routing instructions. No error 1206 within REO was detected 1207 1208 1209 1210 1211 1212 <legal 0 - 1> 1213 */ 1214 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c 1215 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 1216 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 1217 1218 /* Description REO_DESTINATION_RING_7_REO_ERROR_CODE 1219 1220 Field only valid when 'Reo_push_reason' set to 1221 'reo_error_detected'. 1222 1223 1224 1225 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 1226 provided in the REO_ENTRANCE ring is set to 0 1227 1228 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 1229 valid bit is NOT set 1230 1231 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 1232 session having been setup. 1233 1234 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 1235 SSN, Retry bit set: duplicate frame 1236 1237 <enum 4 ba_duplicate> BA session, duplicate frame 1238 1239 <enum 5 regular_frame_2k_jump> A normal (management/data 1240 frame) received with 2K jump in SN 1241 1242 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 1243 in SSN 1244 1245 <enum 7 regular_frame_OOR> A normal (management/data 1246 frame) received with SN falling within the OOR window 1247 1248 <enum 8 bar_frame_OOR> A bar received with SSN falling 1249 within the OOR window 1250 1251 <enum 9 bar_frame_no_ba_session> A bar received without 1252 a BA session 1253 1254 <enum 10 bar_frame_sn_equals_ssn> A bar received with 1255 SSN equal to SN 1256 1257 <enum 11 pn_check_failed> PN Check Failed packet. 1258 1259 <enum 12 2k_error_handling_flag_set> Frame is forwarded 1260 as a result of the 'Seq_2k_error_detected_flag' been set in 1261 the REO Queue descriptor 1262 1263 <enum 13 pn_error_handling_flag_set> Frame is forwarded 1264 as a result of the 'pn_error_detected_flag' been set in the 1265 REO Queue descriptor 1266 1267 <enum 14 queue_descriptor_blocked_set> Frame is 1268 forwarded as a result of the queue descriptor(address) being 1269 blocked as SW/FW seems to be currently in the process of 1270 making updates to this descriptor... 1271 1272 1273 1274 <legal 0-14> 1275 */ 1276 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c 1277 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 1278 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 1279 1280 /* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER 1281 1282 This field in NOT valid (should be set to 0), when 1283 SW_exception is set. 1284 1285 This field indicates the REO MPDU reorder queue ID from 1286 which this frame originated. This field is populated from a 1287 field with the same name in the RX_REO_QUEUE descriptor. 1288 1289 <legal all> 1290 */ 1291 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c 1292 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 1293 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 1294 1295 /* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID 1296 1297 This field in NOT valid (should be set to 0), when 1298 SW_exception is set. 1299 1300 When set, REO has been instructed to not perform the 1301 actual re-ordering of frames for this queue, but just to 1302 insert the reorder opcodes 1303 1304 <legal all> 1305 */ 1306 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 1307 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 1308 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 1309 1310 /* Description REO_DESTINATION_RING_8_REORDER_OPCODE 1311 1312 Field is valid when 'Soft_reorder_info_valid' is set. 1313 This field is always valid for debug purpose as well. 1314 1315 Details are in the MLD. 1316 1317 1318 1319 <enum 0 invalid> 1320 1321 <enum 1 fwdcur_fwdbuf> 1322 1323 <enum 2 fwdbuf_fwdcur> 1324 1325 <enum 3 qcur> 1326 1327 <enum 4 fwdbuf_qcur> 1328 1329 <enum 5 fwdbuf_drop> 1330 1331 <enum 6 fwdall_drop> 1332 1333 <enum 7 fwdall_qcur> 1334 1335 <enum 8 reserved_reo_opcode_1> 1336 1337 <enum 9 dropcur> the error reason code is in 1338 reo_error_code field. 1339 1340 <enum 10 reserved_reo_opcode_2> 1341 1342 <enum 11 reserved_reo_opcode_3> 1343 1344 <enum 12 reserved_reo_opcode_4> 1345 1346 <enum 13 reserved_reo_opcode_5> 1347 1348 <enum 14 reserved_reo_opcode_6> 1349 1350 <enum 15 reserved_reo_opcode_7> 1351 1352 1353 1354 <legal all> 1355 */ 1356 #define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 1357 #define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 1358 #define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e 1359 1360 /* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX 1361 1362 Field only valid when 'Soft_reorder_info_valid' is set. 1363 1364 1365 1366 TODO: add description 1367 1368 1369 1370 <legal all> 1371 */ 1372 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 1373 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 1374 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 1375 1376 /* Description REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER 1377 1378 Field only valid when Rx_mpdu_desc_info_details. 1379 Fragment_flag is set. 1380 1381 1382 1383 The fragment number from the 802.11 header. 1384 1385 1386 1387 Note that the sequence number is embedded in the field: 1388 Rx_mpdu_desc_info_details. Mpdu_sequence_number 1389 1390 1391 1392 <legal all> 1393 */ 1394 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 1395 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13 1396 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000 1397 1398 /* Description REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE 1399 1400 The number of following REO_DESTINATION STRUCTs that 1401 have been replaced with msdu_data extracted from the 1402 msdu_buffer and copied into the ring for easy FW/SW access. 1403 1404 Note that it is possible that these STRUCTs wrap around 1405 the end of the ring. 1406 1407 Feature supported only in HastingsPrime 1408 1409 <legal 0-4> 1410 */ 1411 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020 1412 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17 1413 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000 1414 1415 /* Description REO_DESTINATION_RING_8_SW_EXCEPTION 1416 1417 This field has the same setting as the SW_exception 1418 field in the corresponding REO_entrance_ring descriptor. 1419 1420 When set, the REO entrance descriptor is generated by 1421 FW, and the MPDU was processed in the following way: 1422 1423 - NO re-order function is needed. 1424 1425 - MPDU delinking is determined by the setting of 1426 Entrance ring field: SW_excection_mpdu_delink 1427 1428 - Destination ring selection is based on the setting of 1429 1430 Feature supported only in HastingsPrime 1431 1432 <legal all> 1433 */ 1434 #define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020 1435 #define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21 1436 #define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000 1437 1438 /* Description REO_DESTINATION_RING_8_RESERVED_8A 1439 1440 <legal 0> 1441 */ 1442 #define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 1443 #define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22 1444 #define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000 1445 1446 /* Description REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE 1447 1448 Set to value 0x8888_88888 when msdu capture mode is 1449 enabled for this ring (supported only in HastingsPrime) 1450 1451 <legal 0, 2290649224 > 1452 */ 1453 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024 1454 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0 1455 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff 1456 1457 /* Description REO_DESTINATION_RING_10_RESERVED_10A 1458 1459 <legal 0> 1460 */ 1461 #define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 1462 #define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 1463 #define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff 1464 1465 /* Description REO_DESTINATION_RING_11_RESERVED_11A 1466 1467 <legal 0> 1468 */ 1469 #define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c 1470 #define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 1471 #define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff 1472 1473 /* Description REO_DESTINATION_RING_12_RESERVED_12A 1474 1475 <legal 0> 1476 */ 1477 #define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 1478 #define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 1479 #define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff 1480 1481 /* Description REO_DESTINATION_RING_13_RESERVED_13A 1482 1483 <legal 0> 1484 */ 1485 #define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 1486 #define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 1487 #define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff 1488 1489 /* Description REO_DESTINATION_RING_14_RESERVED_14A 1490 1491 <legal 0> 1492 */ 1493 #define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 1494 #define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 1495 #define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff 1496 1497 /* Description REO_DESTINATION_RING_15_RESERVED_15 1498 1499 <legal 0> 1500 */ 1501 #define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c 1502 #define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 1503 #define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff 1504 1505 /* Description REO_DESTINATION_RING_15_RING_ID 1506 1507 The buffer pointer ring ID. 1508 1509 0 refers to the IDLE ring 1510 1511 1 - N refers to other rings 1512 1513 1514 1515 Helps with debugging when dumping ring contents. 1516 1517 <legal all> 1518 */ 1519 #define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c 1520 #define REO_DESTINATION_RING_15_RING_ID_LSB 20 1521 #define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 1522 1523 /* Description REO_DESTINATION_RING_15_LOOPING_COUNT 1524 1525 A count value that indicates the number of times the 1526 producer of entries into this Ring has looped around the 1527 ring. 1528 1529 At initialization time, this value is set to 0. On the 1530 first loop, this value is set to 1. After the max value is 1531 reached allowed by the number of bits for this field, the 1532 count value continues with 0 again. 1533 1534 In case SW is the consumer of the ring entries, it can 1535 use this field to figure out up to where the producer of 1536 entries has created new entries. This eliminates the need to 1537 check where the head pointer' of the ring is located once 1538 the SW starts processing an interrupt indicating that new 1539 entries have been put into this ring... 1540 1541 1542 1543 Also note that SW if it wants only needs to look at the 1544 LSB bit of this count value. 1545 1546 <legal all> 1547 */ 1548 #define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c 1549 #define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 1550 #define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 1551 1552 1553 #endif // _REO_DESTINATION_RING_H_ 1554