1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_ENTRANCE_RING_H_ 25 #define _REO_ENTRANCE_RING_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rx_mpdu_details.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; 35 // 4 rx_reo_queue_desc_addr_31_0[31:0] 36 // 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] 37 // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], sw_exception[11], sw_exception_mpdu_delink[12], sw_exception_destination_ring_valid[13], sw_exception_destination_ring[18:14], reserved_6a[31:19] 38 // 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] 39 // 40 // ################ END SUMMARY ################# 41 42 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 43 44 struct reo_entrance_ring { 45 struct rx_mpdu_details reo_level_mpdu_frame_info; 46 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 47 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 48 rounded_mpdu_byte_count : 14, //[21:8] 49 reo_destination_indication : 5, //[26:22] 50 frameless_bar : 1, //[27] 51 reserved_5a : 4; //[31:28] 52 uint32_t rxdma_push_reason : 2, //[1:0] 53 rxdma_error_code : 5, //[6:2] 54 mpdu_fragment_number : 4, //[10:7] 55 sw_exception : 1, //[11] 56 sw_exception_mpdu_delink : 1, //[12] 57 sw_exception_destination_ring_valid: 1, //[13] 58 sw_exception_destination_ring : 5, //[18:14] 59 reserved_6a : 13; //[31:19] 60 uint32_t reserved_7a : 20, //[19:0] 61 ring_id : 8, //[27:20] 62 looping_count : 4; //[31:28] 63 }; 64 65 /* 66 67 struct rx_mpdu_details reo_level_mpdu_frame_info 68 69 Consumer: REO 70 71 Producer: RXDMA 72 73 74 75 Details related to the MPDU being pushed into the REO 76 77 rx_reo_queue_desc_addr_31_0 78 79 Consumer: REO 80 81 Producer: RXDMA 82 83 84 85 Address (lower 32 bits) of the REO queue descriptor. 86 87 <legal all> 88 89 rx_reo_queue_desc_addr_39_32 90 91 Consumer: REO 92 93 Producer: RXDMA 94 95 96 97 Address (upper 8 bits) of the REO queue descriptor. 98 99 <legal all> 100 101 rounded_mpdu_byte_count 102 103 An approximation of the number of bytes received in this 104 MPDU. 105 106 Used to keeps stats on the amount of data flowing 107 through a queue. 108 109 <legal all> 110 111 reo_destination_indication 112 113 RXDMA copy the MPDU's first MSDU's destination 114 indication field here. This is used for REO to be able to 115 re-route the packet to a different SW destination ring if 116 the packet is detected as error in REO. 117 118 119 120 The ID of the REO exit ring where the MSDU frame shall 121 push after (MPDU level) reordering has finished. 122 123 124 125 <enum 0 reo_destination_tcl> Reo will push the frame 126 into the REO2TCL ring 127 128 <enum 1 reo_destination_sw1> Reo will push the frame 129 into the REO2SW1 ring 130 131 <enum 2 reo_destination_sw2> Reo will push the frame 132 into the REO2SW2 ring 133 134 <enum 3 reo_destination_sw3> Reo will push the frame 135 into the REO2SW3 ring 136 137 <enum 4 reo_destination_sw4> Reo will push the frame 138 into the REO2SW4 ring 139 140 <enum 5 reo_destination_release> Reo will push the frame 141 into the REO_release ring 142 143 <enum 6 reo_destination_fw> Reo will push the frame into 144 the REO2FW ring 145 146 <enum 7 reo_destination_sw5> Reo will push the frame 147 into the REO2SW5 ring 148 149 <enum 8 reo_destination_sw6> Reo will push the frame 150 into the REO2SW6 ring 151 152 <enum 9 reo_destination_9> REO remaps this <enum 10 153 reo_destination_10> REO remaps this 154 155 <enum 11 reo_destination_11> REO remaps this 156 157 <enum 12 reo_destination_12> REO remaps this <enum 13 158 reo_destination_13> REO remaps this 159 160 <enum 14 reo_destination_14> REO remaps this 161 162 <enum 15 reo_destination_15> REO remaps this 163 164 <enum 16 reo_destination_16> REO remaps this 165 166 <enum 17 reo_destination_17> REO remaps this 167 168 <enum 18 reo_destination_18> REO remaps this 169 170 <enum 19 reo_destination_19> REO remaps this 171 172 <enum 20 reo_destination_20> REO remaps this 173 174 <enum 21 reo_destination_21> REO remaps this 175 176 <enum 22 reo_destination_22> REO remaps this 177 178 <enum 23 reo_destination_23> REO remaps this 179 180 <enum 24 reo_destination_24> REO remaps this 181 182 <enum 25 reo_destination_25> REO remaps this 183 184 <enum 26 reo_destination_26> REO remaps this 185 186 <enum 27 reo_destination_27> REO remaps this 187 188 <enum 28 reo_destination_28> REO remaps this 189 190 <enum 29 reo_destination_29> REO remaps this 191 192 <enum 30 reo_destination_30> REO remaps this 193 194 <enum 31 reo_destination_31> REO remaps this 195 196 197 198 <legal all> 199 200 frameless_bar 201 202 When set, this REO entrance ring struct contains BAR 203 info from a multi TID BAR frame. The original multi TID BAR 204 frame itself contained all the REO info for the first TID, 205 but all the subsequent TID info and their linkage to the REO 206 descriptors is passed down as 'frameless' BAR info. 207 208 209 210 The only fields valid in this descriptor when this bit 211 is set are: 212 213 Rx_reo_queue_desc_addr_31_0 214 215 RX_reo_queue_desc_addr_39_32 216 217 218 219 And within the 220 221 Reo_level_mpdu_frame_info: 222 223 Within Rx_mpdu_desc_info_details: 224 225 Mpdu_Sequence_number 226 227 BAR_frame 228 229 Peer_meta_data 230 231 All other fields shall be set to 0 232 233 234 235 <legal all> 236 237 reserved_5a 238 239 <legal 0> 240 241 rxdma_push_reason 242 243 Indicates why rxdma pushed the frame to this ring 244 245 246 247 This field is ignored by REO. 248 249 250 251 <enum 0 rxdma_error_detected> RXDMA detected an error an 252 pushed this frame to this queue 253 254 <enum 1 rxdma_routing_instruction> RXDMA pushed the 255 frame to this queue per received routing instructions. No 256 error within RXDMA was detected 257 258 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 259 result the MSDU link descriptor might not have the 260 last_msdu_in_mpdu_flag set, but instead WBM might just see a 261 NULL pointer in the MSDU link descriptor. This is to be 262 considered a normal condition for this scenario. 263 264 265 266 <legal 0 - 2> 267 268 rxdma_error_code 269 270 Field only valid when 'rxdma_push_reason' set to 271 'rxdma_error_detected'. 272 273 274 275 This field is ignored by REO. 276 277 278 279 <enum 0 rxdma_overflow_err>MPDU frame is not complete 280 due to a FIFO overflow error in RXPCU. 281 282 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 283 due to receiving incomplete MPDU from the PHY 284 285 286 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 287 error or CRYPTO received an encrypted frame, but did not get 288 a valid corresponding key id in the peer entry. 289 290 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 291 error 292 293 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 294 unencrypted frame error when encrypted was expected 295 296 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 297 length error 298 299 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 300 number of MSDUs allowed in an MPDU got exceeded 301 302 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 303 error 304 305 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 306 parsing error 307 308 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 309 during SA search 310 311 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 312 during DA search 313 314 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 315 timeout during flow search 316 317 <enum 13 rxdma_flush_request>RXDMA received a flush 318 request 319 320 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 321 present as well as a fragmented MPDU. A-MSDU defragmentation 322 is not supported in Lithium SW so this is treated as an 323 error. 324 325 mpdu_fragment_number 326 327 Field only valid when Reo_level_mpdu_frame_info. 328 Rx_mpdu_desc_info_details.Fragment_flag is set. 329 330 331 332 The fragment number from the 802.11 header. 333 334 335 336 Note that the sequence number is embedded in the field: 337 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 338 Mpdu_sequence_number 339 340 341 342 <legal all> 343 344 sw_exception 345 346 When not set, REO is performing all its default MPDU 347 processing operations, 348 349 When set, this REO entrance descriptor is generated by 350 FW, and should be processed as an exception. This implies: 351 352 NO re-order function is needed. 353 354 MPDU delinking is determined by the setting of field 355 SW_excection_mpdu_delink 356 357 Destination ring selection is based on the setting of 358 the field SW_exception_destination_ring_valid 359 360 In the destination ring descriptor set bit: 361 SW_exception_entry 362 363 Feature supported only in HastingsPrime 364 365 <legal all> 366 367 sw_exception_mpdu_delink 368 369 Field only valid when SW_exception is set. 370 371 1'b0: REO should NOT delink the MPDU, and thus pass this 372 MPDU on to the destination ring as is. This implies that in 373 the REO_DESTINATION_RING struct field 374 Buf_or_link_desc_addr_info should point to an MSDU link 375 descriptor 376 377 1'b1: REO should perform the normal MPDU delink into 378 MSDU operations. 379 380 Feature supported only in HastingsPrime 381 382 <legal all> 383 384 sw_exception_destination_ring_valid 385 386 Field only valid when SW_exception is set. 387 388 1'b0: REO shall push the MPDU (or delinked MPDU based on 389 the setting of SW_exception_mpdu_delink) to the destination 390 ring according to field reo_destination_indication. 391 392 1'b1: REO shall push the MPDU (or delinked MPDU based on 393 the setting of SW_exception_mpdu_delink) to the destination 394 ring according to field SW_exception_destination_ring. 395 396 Feature supported only in HastingsPrime 397 398 <legal all> 399 400 sw_exception_destination_ring 401 402 Field only valid when fields SW_exception and 403 SW_exception_destination_ring_valid are set. 404 405 The ID of the ring where REO shall push this frame. 406 407 <enum 0 reo_destination_tcl> Reo will push the frame 408 into the REO2TCL ring 409 410 <enum 1 reo_destination_sw1> Reo will push the frame 411 into the REO2SW1 ring 412 413 <enum 2 reo_destination_sw2> Reo will push the frame 414 into the REO2SW1 ring 415 416 <enum 3 reo_destination_sw3> Reo will push the frame 417 into the REO2SW1 ring 418 419 <enum 4 reo_destination_sw4> Reo will push the frame 420 into the REO2SW1 ring 421 422 <enum 5 reo_destination_release> Reo will push the frame 423 into the REO_release ring 424 425 <enum 6 reo_destination_fw> Reo will push the frame into 426 the REO2FW ring 427 428 <enum 7 reo_destination_sw5> REO remaps this 429 430 <enum 8 reo_destination_sw6> REO remaps this 431 432 <enum 9 reo_destination_9> REO remaps this 433 434 <enum 10 reo_destination_10> REO remaps this 435 436 <enum 11 reo_destination_11> REO remaps this 437 438 <enum 12 reo_destination_12> REO remaps this <enum 13 439 reo_destination_13> REO remaps this 440 441 <enum 14 reo_destination_14> REO remaps this 442 443 <enum 15 reo_destination_15> REO remaps this 444 445 <enum 16 reo_destination_16> REO remaps this 446 447 <enum 17 reo_destination_17> REO remaps this 448 449 <enum 18 reo_destination_18> REO remaps this 450 451 <enum 19 reo_destination_19> REO remaps this 452 453 <enum 20 reo_destination_20> REO remaps this 454 455 <enum 21 reo_destination_21> REO remaps this 456 457 <enum 22 reo_destination_22> REO remaps this 458 459 <enum 23 reo_destination_23> REO remaps this 460 461 <enum 24 reo_destination_24> REO remaps this 462 463 <enum 25 reo_destination_25> REO remaps this 464 465 <enum 26 reo_destination_26> REO remaps this 466 467 <enum 27 reo_destination_27> REO remaps this 468 469 <enum 28 reo_destination_28> REO remaps this 470 471 <enum 29 reo_destination_29> REO remaps this 472 473 <enum 30 reo_destination_30> REO remaps this 474 475 <enum 31 reo_destination_31> REO remaps this 476 477 478 479 Feature supported only in HastingsPrime 480 481 <legal all> 482 483 reserved_6a 484 485 <legal 0> 486 487 reserved_7a 488 489 <legal 0> 490 491 ring_id 492 493 Consumer: SW/REO/DEBUG 494 495 Producer: SRNG (of RXDMA) 496 497 498 499 For debugging. 500 501 This field is filled in by the SRNG module. 502 503 It help to identify the ring that is being looked <legal 504 all> 505 506 looping_count 507 508 Consumer: SW/REO/DEBUG 509 510 Producer: SRNG (of RXDMA) 511 512 513 514 For debugging. 515 516 This field is filled in by the SRNG module. 517 518 519 520 A count value that indicates the number of times the 521 producer of entries into this Ring has looped around the 522 ring. 523 524 At initialization time, this value is set to 0. On the 525 first loop, this value is set to 1. After the max value is 526 reached allowed by the number of bits for this field, the 527 count value continues with 0 again. 528 529 530 531 In case SW is the consumer of the ring entries, it can 532 use this field to figure out up to where the producer of 533 entries has created new entries. This eliminates the need to 534 check where the head pointer' of the ring is located once 535 the SW starts processing an interrupt indicating that new 536 entries have been put into this ring... 537 538 539 540 Also note that SW if it wants only needs to look at the 541 LSB bit of this count value. 542 543 <legal all> 544 */ 545 546 547 /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ 548 549 550 /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 551 552 553 /* Description REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 554 555 Address (lower 32 bits) of the MSDU buffer OR 556 MSDU_EXTENSION descriptor OR Link Descriptor 557 558 559 560 In case of 'NULL' pointer, this field is set to 0 561 562 <legal all> 563 */ 564 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 565 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 566 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 567 568 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 569 570 Address (upper 8 bits) of the MSDU buffer OR 571 MSDU_EXTENSION descriptor OR Link Descriptor 572 573 574 575 In case of 'NULL' pointer, this field is set to 0 576 577 <legal all> 578 */ 579 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 580 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 581 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 582 583 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 584 585 Consumer: WBM 586 587 Producer: SW/FW 588 589 590 591 In case of 'NULL' pointer, this field is set to 0 592 593 594 595 Indicates to which buffer manager the buffer OR 596 MSDU_EXTENSION descriptor OR link descriptor that is being 597 pointed to shall be returned after the frame has been 598 processed. It is used by WBM for routing purposes. 599 600 601 602 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 603 to the WMB buffer idle list 604 605 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 606 returned to the WMB idle link descriptor idle list 607 608 <enum 2 FW_BM> This buffer shall be returned to the FW 609 610 <enum 3 SW0_BM> This buffer shall be returned to the SW, 611 ring 0 612 613 <enum 4 SW1_BM> This buffer shall be returned to the SW, 614 ring 1 615 616 <enum 5 SW2_BM> This buffer shall be returned to the SW, 617 ring 2 618 619 <enum 6 SW3_BM> This buffer shall be returned to the SW, 620 ring 3 621 622 <enum 7 SW4_BM> This buffer shall be returned to the SW, 623 ring 4 624 625 626 627 <legal all> 628 */ 629 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 630 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 631 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 632 633 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 634 635 Cookie field exclusively used by SW. 636 637 638 639 In case of 'NULL' pointer, this field is set to 0 640 641 642 643 HW ignores the contents, accept that it passes the 644 programmed value on to other descriptors together with the 645 physical address 646 647 648 649 Field can be used by SW to for example associate the 650 buffers physical address with the virtual address 651 652 The bit definitions as used by SW are within SW HLD 653 specification 654 655 656 657 NOTE: 658 659 The three most significant bits can have a special 660 meaning in case this struct is embedded in a TX_MPDU_DETAILS 661 STRUCT, and field transmit_bw_restriction is set 662 663 664 665 In case of NON punctured transmission: 666 667 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 668 669 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 670 671 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 672 673 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 674 675 676 677 In case of punctured transmission: 678 679 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 680 681 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 682 683 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 684 685 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 686 687 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 688 689 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 690 691 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 692 693 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 694 695 696 697 Note: a punctured transmission is indicated by the 698 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 699 TLV 700 701 702 703 <legal all> 704 */ 705 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 706 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 707 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 708 709 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 710 711 712 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 713 714 Consumer: REO/SW/FW 715 716 Producer: RXDMA 717 718 719 720 The number of MSDUs within the MPDU 721 722 <legal all> 723 */ 724 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 725 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 726 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 727 728 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 729 730 Consumer: REO/SW/FW 731 732 Producer: RXDMA 733 734 735 736 The field can have two different meanings based on the 737 setting of field 'BAR_frame': 738 739 740 741 'BAR_frame' is NOT set: 742 743 The MPDU sequence number of the received frame. 744 745 746 747 'BAR_frame' is set. 748 749 The MPDU Start sequence number from the BAR frame 750 751 <legal all> 752 */ 753 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 754 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 755 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 756 757 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 758 759 Consumer: REO/SW/FW 760 761 Producer: RXDMA 762 763 764 765 When set, this MPDU is a fragment and REO should forward 766 this fragment MPDU to the REO destination ring without any 767 reorder checks, pn checks or bitmap update. This implies 768 that REO is forwarding the pointer to the MSDU link 769 descriptor. The destination ring is coming from a 770 programmable register setting in REO 771 772 773 774 <legal all> 775 */ 776 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 777 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 778 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 779 780 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 781 782 Consumer: REO/SW/FW 783 784 Producer: RXDMA 785 786 787 788 The retry bit setting from the MPDU header of the 789 received frame 790 791 <legal all> 792 */ 793 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 794 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 795 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 796 797 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 798 799 Consumer: REO/SW/FW 800 801 Producer: RXDMA 802 803 804 805 When set, the MPDU was received as part of an A-MPDU. 806 807 <legal all> 808 */ 809 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 810 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 811 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 812 813 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 814 815 Consumer: REO/SW/FW 816 817 Producer: RXDMA 818 819 820 821 When set, the received frame is a BAR frame. After 822 processing, this frame shall be pushed to SW or deleted. 823 824 <legal all> 825 */ 826 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 827 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 828 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 829 830 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 831 832 Consumer: REO/SW/FW 833 834 Producer: RXDMA 835 836 837 838 Copied here by RXDMA from RX_MPDU_END 839 840 When not set, REO will Not perform a PN sequence number 841 check 842 */ 843 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 844 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 845 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 846 847 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 848 849 When set, OLE found a valid SA entry for all MSDUs in 850 this MPDU 851 852 <legal all> 853 */ 854 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 855 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 856 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 857 858 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 859 860 When set, at least 1 MSDU within the MPDU has an 861 unsuccessful MAC source address search due to the expiration 862 of the search timer. 863 864 <legal all> 865 */ 866 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 867 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 868 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 869 870 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 871 872 When set, OLE found a valid DA entry for all MSDUs in 873 this MPDU 874 875 <legal all> 876 */ 877 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 878 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 879 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 880 881 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 882 883 Field Only valid if da_is_valid is set 884 885 886 887 When set, at least one of the DA addresses is a 888 Multicast or Broadcast address. 889 890 <legal all> 891 */ 892 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 893 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 894 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 895 896 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 897 898 When set, at least 1 MSDU within the MPDU has an 899 unsuccessful MAC destination address search due to the 900 expiration of the search timer. 901 902 <legal all> 903 */ 904 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 905 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 906 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 907 908 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 909 910 Field only valid when first_msdu_in_mpdu_flag is set. 911 912 913 914 When set, the contents in the MSDU buffer contains a 915 'RAW' MPDU. This 'RAW' MPDU might be spread out over 916 multiple MSDU buffers. 917 918 <legal all> 919 */ 920 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 921 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 922 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 923 924 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 925 926 The More Fragment bit setting from the MPDU header of 927 the received frame 928 929 930 931 <legal all> 932 */ 933 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 934 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 935 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 936 937 /* Description REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 938 939 Meta data that SW has programmed in the Peer table entry 940 of the transmitting STA. 941 942 <legal all> 943 */ 944 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 945 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 946 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 947 948 /* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 949 950 Consumer: REO 951 952 Producer: RXDMA 953 954 955 956 Address (lower 32 bits) of the REO queue descriptor. 957 958 <legal all> 959 */ 960 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 961 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 962 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 963 964 /* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 965 966 Consumer: REO 967 968 Producer: RXDMA 969 970 971 972 Address (upper 8 bits) of the REO queue descriptor. 973 974 <legal all> 975 */ 976 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 977 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 978 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 979 980 /* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT 981 982 An approximation of the number of bytes received in this 983 MPDU. 984 985 Used to keeps stats on the amount of data flowing 986 through a queue. 987 988 <legal all> 989 */ 990 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 991 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 992 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 993 994 /* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION 995 996 RXDMA copy the MPDU's first MSDU's destination 997 indication field here. This is used for REO to be able to 998 re-route the packet to a different SW destination ring if 999 the packet is detected as error in REO. 1000 1001 1002 1003 The ID of the REO exit ring where the MSDU frame shall 1004 push after (MPDU level) reordering has finished. 1005 1006 1007 1008 <enum 0 reo_destination_tcl> Reo will push the frame 1009 into the REO2TCL ring 1010 1011 <enum 1 reo_destination_sw1> Reo will push the frame 1012 into the REO2SW1 ring 1013 1014 <enum 2 reo_destination_sw2> Reo will push the frame 1015 into the REO2SW2 ring 1016 1017 <enum 3 reo_destination_sw3> Reo will push the frame 1018 into the REO2SW3 ring 1019 1020 <enum 4 reo_destination_sw4> Reo will push the frame 1021 into the REO2SW4 ring 1022 1023 <enum 5 reo_destination_release> Reo will push the frame 1024 into the REO_release ring 1025 1026 <enum 6 reo_destination_fw> Reo will push the frame into 1027 the REO2FW ring 1028 1029 <enum 7 reo_destination_sw5> Reo will push the frame 1030 into the REO2SW5 ring 1031 1032 <enum 8 reo_destination_sw6> Reo will push the frame 1033 into the REO2SW6 ring 1034 1035 <enum 9 reo_destination_9> REO remaps this <enum 10 1036 reo_destination_10> REO remaps this 1037 1038 <enum 11 reo_destination_11> REO remaps this 1039 1040 <enum 12 reo_destination_12> REO remaps this <enum 13 1041 reo_destination_13> REO remaps this 1042 1043 <enum 14 reo_destination_14> REO remaps this 1044 1045 <enum 15 reo_destination_15> REO remaps this 1046 1047 <enum 16 reo_destination_16> REO remaps this 1048 1049 <enum 17 reo_destination_17> REO remaps this 1050 1051 <enum 18 reo_destination_18> REO remaps this 1052 1053 <enum 19 reo_destination_19> REO remaps this 1054 1055 <enum 20 reo_destination_20> REO remaps this 1056 1057 <enum 21 reo_destination_21> REO remaps this 1058 1059 <enum 22 reo_destination_22> REO remaps this 1060 1061 <enum 23 reo_destination_23> REO remaps this 1062 1063 <enum 24 reo_destination_24> REO remaps this 1064 1065 <enum 25 reo_destination_25> REO remaps this 1066 1067 <enum 26 reo_destination_26> REO remaps this 1068 1069 <enum 27 reo_destination_27> REO remaps this 1070 1071 <enum 28 reo_destination_28> REO remaps this 1072 1073 <enum 29 reo_destination_29> REO remaps this 1074 1075 <enum 30 reo_destination_30> REO remaps this 1076 1077 <enum 31 reo_destination_31> REO remaps this 1078 1079 1080 1081 <legal all> 1082 */ 1083 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 1084 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 1085 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 1086 1087 /* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR 1088 1089 When set, this REO entrance ring struct contains BAR 1090 info from a multi TID BAR frame. The original multi TID BAR 1091 frame itself contained all the REO info for the first TID, 1092 but all the subsequent TID info and their linkage to the REO 1093 descriptors is passed down as 'frameless' BAR info. 1094 1095 1096 1097 The only fields valid in this descriptor when this bit 1098 is set are: 1099 1100 Rx_reo_queue_desc_addr_31_0 1101 1102 RX_reo_queue_desc_addr_39_32 1103 1104 1105 1106 And within the 1107 1108 Reo_level_mpdu_frame_info: 1109 1110 Within Rx_mpdu_desc_info_details: 1111 1112 Mpdu_Sequence_number 1113 1114 BAR_frame 1115 1116 Peer_meta_data 1117 1118 All other fields shall be set to 0 1119 1120 1121 1122 <legal all> 1123 */ 1124 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 1125 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 1126 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 1127 1128 /* Description REO_ENTRANCE_RING_5_RESERVED_5A 1129 1130 <legal 0> 1131 */ 1132 #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 1133 #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 1134 #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 1135 1136 /* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON 1137 1138 Indicates why rxdma pushed the frame to this ring 1139 1140 1141 1142 This field is ignored by REO. 1143 1144 1145 1146 <enum 0 rxdma_error_detected> RXDMA detected an error an 1147 pushed this frame to this queue 1148 1149 <enum 1 rxdma_routing_instruction> RXDMA pushed the 1150 frame to this queue per received routing instructions. No 1151 error within RXDMA was detected 1152 1153 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 1154 result the MSDU link descriptor might not have the 1155 last_msdu_in_mpdu_flag set, but instead WBM might just see a 1156 NULL pointer in the MSDU link descriptor. This is to be 1157 considered a normal condition for this scenario. 1158 1159 1160 1161 <legal 0 - 2> 1162 */ 1163 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 1164 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 1165 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 1166 1167 /* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE 1168 1169 Field only valid when 'rxdma_push_reason' set to 1170 'rxdma_error_detected'. 1171 1172 1173 1174 This field is ignored by REO. 1175 1176 1177 1178 <enum 0 rxdma_overflow_err>MPDU frame is not complete 1179 due to a FIFO overflow error in RXPCU. 1180 1181 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 1182 due to receiving incomplete MPDU from the PHY 1183 1184 1185 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 1186 error or CRYPTO received an encrypted frame, but did not get 1187 a valid corresponding key id in the peer entry. 1188 1189 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 1190 error 1191 1192 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 1193 unencrypted frame error when encrypted was expected 1194 1195 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 1196 length error 1197 1198 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 1199 number of MSDUs allowed in an MPDU got exceeded 1200 1201 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 1202 error 1203 1204 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 1205 parsing error 1206 1207 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 1208 during SA search 1209 1210 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 1211 during DA search 1212 1213 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 1214 timeout during flow search 1215 1216 <enum 13 rxdma_flush_request>RXDMA received a flush 1217 request 1218 1219 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 1220 present as well as a fragmented MPDU. A-MSDU defragmentation 1221 is not supported in Lithium SW so this is treated as an 1222 error. 1223 */ 1224 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 1225 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 1226 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c 1227 1228 /* Description REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER 1229 1230 Field only valid when Reo_level_mpdu_frame_info. 1231 Rx_mpdu_desc_info_details.Fragment_flag is set. 1232 1233 1234 1235 The fragment number from the 802.11 header. 1236 1237 1238 1239 Note that the sequence number is embedded in the field: 1240 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 1241 Mpdu_sequence_number 1242 1243 1244 1245 <legal all> 1246 */ 1247 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 1248 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 1249 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 1250 1251 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION 1252 1253 When not set, REO is performing all its default MPDU 1254 processing operations, 1255 1256 When set, this REO entrance descriptor is generated by 1257 FW, and should be processed as an exception. This implies: 1258 1259 NO re-order function is needed. 1260 1261 MPDU delinking is determined by the setting of field 1262 SW_excection_mpdu_delink 1263 1264 Destination ring selection is based on the setting of 1265 the field SW_exception_destination_ring_valid 1266 1267 In the destination ring descriptor set bit: 1268 SW_exception_entry 1269 1270 Feature supported only in HastingsPrime 1271 1272 <legal all> 1273 */ 1274 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018 1275 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11 1276 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800 1277 1278 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK 1279 1280 Field only valid when SW_exception is set. 1281 1282 1'b0: REO should NOT delink the MPDU, and thus pass this 1283 MPDU on to the destination ring as is. This implies that in 1284 the REO_DESTINATION_RING struct field 1285 Buf_or_link_desc_addr_info should point to an MSDU link 1286 descriptor 1287 1288 1'b1: REO should perform the normal MPDU delink into 1289 MSDU operations. 1290 1291 Feature supported only in HastingsPrime 1292 1293 <legal all> 1294 */ 1295 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 1296 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12 1297 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 1298 1299 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID 1300 1301 Field only valid when SW_exception is set. 1302 1303 1'b0: REO shall push the MPDU (or delinked MPDU based on 1304 the setting of SW_exception_mpdu_delink) to the destination 1305 ring according to field reo_destination_indication. 1306 1307 1'b1: REO shall push the MPDU (or delinked MPDU based on 1308 the setting of SW_exception_mpdu_delink) to the destination 1309 ring according to field SW_exception_destination_ring. 1310 1311 Feature supported only in HastingsPrime 1312 1313 <legal all> 1314 */ 1315 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 1316 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 1317 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 1318 1319 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING 1320 1321 Field only valid when fields SW_exception and 1322 SW_exception_destination_ring_valid are set. 1323 1324 The ID of the ring where REO shall push this frame. 1325 1326 <enum 0 reo_destination_tcl> Reo will push the frame 1327 into the REO2TCL ring 1328 1329 <enum 1 reo_destination_sw1> Reo will push the frame 1330 into the REO2SW1 ring 1331 1332 <enum 2 reo_destination_sw2> Reo will push the frame 1333 into the REO2SW1 ring 1334 1335 <enum 3 reo_destination_sw3> Reo will push the frame 1336 into the REO2SW1 ring 1337 1338 <enum 4 reo_destination_sw4> Reo will push the frame 1339 into the REO2SW1 ring 1340 1341 <enum 5 reo_destination_release> Reo will push the frame 1342 into the REO_release ring 1343 1344 <enum 6 reo_destination_fw> Reo will push the frame into 1345 the REO2FW ring 1346 1347 <enum 7 reo_destination_sw5> REO remaps this 1348 1349 <enum 8 reo_destination_sw6> REO remaps this 1350 1351 <enum 9 reo_destination_9> REO remaps this 1352 1353 <enum 10 reo_destination_10> REO remaps this 1354 1355 <enum 11 reo_destination_11> REO remaps this 1356 1357 <enum 12 reo_destination_12> REO remaps this <enum 13 1358 reo_destination_13> REO remaps this 1359 1360 <enum 14 reo_destination_14> REO remaps this 1361 1362 <enum 15 reo_destination_15> REO remaps this 1363 1364 <enum 16 reo_destination_16> REO remaps this 1365 1366 <enum 17 reo_destination_17> REO remaps this 1367 1368 <enum 18 reo_destination_18> REO remaps this 1369 1370 <enum 19 reo_destination_19> REO remaps this 1371 1372 <enum 20 reo_destination_20> REO remaps this 1373 1374 <enum 21 reo_destination_21> REO remaps this 1375 1376 <enum 22 reo_destination_22> REO remaps this 1377 1378 <enum 23 reo_destination_23> REO remaps this 1379 1380 <enum 24 reo_destination_24> REO remaps this 1381 1382 <enum 25 reo_destination_25> REO remaps this 1383 1384 <enum 26 reo_destination_26> REO remaps this 1385 1386 <enum 27 reo_destination_27> REO remaps this 1387 1388 <enum 28 reo_destination_28> REO remaps this 1389 1390 <enum 29 reo_destination_29> REO remaps this 1391 1392 <enum 30 reo_destination_30> REO remaps this 1393 1394 <enum 31 reo_destination_31> REO remaps this 1395 1396 1397 1398 Feature supported only in HastingsPrime 1399 1400 <legal all> 1401 */ 1402 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 1403 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14 1404 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 1405 1406 /* Description REO_ENTRANCE_RING_6_RESERVED_6A 1407 1408 <legal 0> 1409 */ 1410 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 1411 #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19 1412 #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000 1413 1414 /* Description REO_ENTRANCE_RING_7_RESERVED_7A 1415 1416 <legal 0> 1417 */ 1418 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c 1419 #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0 1420 #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff 1421 1422 /* Description REO_ENTRANCE_RING_7_RING_ID 1423 1424 Consumer: SW/REO/DEBUG 1425 1426 Producer: SRNG (of RXDMA) 1427 1428 1429 1430 For debugging. 1431 1432 This field is filled in by the SRNG module. 1433 1434 It help to identify the ring that is being looked <legal 1435 all> 1436 */ 1437 #define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c 1438 #define REO_ENTRANCE_RING_7_RING_ID_LSB 20 1439 #define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 1440 1441 /* Description REO_ENTRANCE_RING_7_LOOPING_COUNT 1442 1443 Consumer: SW/REO/DEBUG 1444 1445 Producer: SRNG (of RXDMA) 1446 1447 1448 1449 For debugging. 1450 1451 This field is filled in by the SRNG module. 1452 1453 1454 1455 A count value that indicates the number of times the 1456 producer of entries into this Ring has looped around the 1457 ring. 1458 1459 At initialization time, this value is set to 0. On the 1460 first loop, this value is set to 1. After the max value is 1461 reached allowed by the number of bits for this field, the 1462 count value continues with 0 again. 1463 1464 1465 1466 In case SW is the consumer of the ring entries, it can 1467 use this field to figure out up to where the producer of 1468 entries has created new entries. This eliminates the need to 1469 check where the head pointer' of the ring is located once 1470 the SW starts processing an interrupt indicating that new 1471 entries have been put into this ring... 1472 1473 1474 1475 Also note that SW if it wants only needs to look at the 1476 LSB bit of this count value. 1477 1478 <legal all> 1479 */ 1480 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 1481 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 1482 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 1483 1484 1485 #endif // _REO_ENTRANCE_RING_H_ 1486