xref: /wlan-driver/fw-api/hw/qca6490/v1/reo_update_rx_reo_queue_status.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2019 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 //
20 // DO NOT EDIT!  This file is automatically generated
21 //               These definitions are tied to a particular hardware layout
22 
23 
24 #ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
25 #define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
26 #if !defined(__ASSEMBLER__)
27 #endif
28 
29 #include "uniform_reo_status_header.h"
30 
31 // ################ START SUMMARY #################
32 //
33 //	Dword	Fields
34 //	0-1	struct uniform_reo_status_header status_header;
35 //	2	reserved_2a[31:0]
36 //	3	reserved_3a[31:0]
37 //	4	reserved_4a[31:0]
38 //	5	reserved_5a[31:0]
39 //	6	reserved_6a[31:0]
40 //	7	reserved_7a[31:0]
41 //	8	reserved_8a[31:0]
42 //	9	reserved_9a[31:0]
43 //	10	reserved_10a[31:0]
44 //	11	reserved_11a[31:0]
45 //	12	reserved_12a[31:0]
46 //	13	reserved_13a[31:0]
47 //	14	reserved_14a[31:0]
48 //	15	reserved_15a[31:0]
49 //	16	reserved_16a[31:0]
50 //	17	reserved_17a[31:0]
51 //	18	reserved_18a[31:0]
52 //	19	reserved_19a[31:0]
53 //	20	reserved_20a[31:0]
54 //	21	reserved_21a[31:0]
55 //	22	reserved_22a[31:0]
56 //	23	reserved_23a[31:0]
57 //	24	reserved_24a[27:0], looping_count[31:28]
58 //
59 // ################ END SUMMARY #################
60 
61 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
62 
63 struct reo_update_rx_reo_queue_status {
64     struct            uniform_reo_status_header                       status_header;
65              uint32_t reserved_2a                     : 32; //[31:0]
66              uint32_t reserved_3a                     : 32; //[31:0]
67              uint32_t reserved_4a                     : 32; //[31:0]
68              uint32_t reserved_5a                     : 32; //[31:0]
69              uint32_t reserved_6a                     : 32; //[31:0]
70              uint32_t reserved_7a                     : 32; //[31:0]
71              uint32_t reserved_8a                     : 32; //[31:0]
72              uint32_t reserved_9a                     : 32; //[31:0]
73              uint32_t reserved_10a                    : 32; //[31:0]
74              uint32_t reserved_11a                    : 32; //[31:0]
75              uint32_t reserved_12a                    : 32; //[31:0]
76              uint32_t reserved_13a                    : 32; //[31:0]
77              uint32_t reserved_14a                    : 32; //[31:0]
78              uint32_t reserved_15a                    : 32; //[31:0]
79              uint32_t reserved_16a                    : 32; //[31:0]
80              uint32_t reserved_17a                    : 32; //[31:0]
81              uint32_t reserved_18a                    : 32; //[31:0]
82              uint32_t reserved_19a                    : 32; //[31:0]
83              uint32_t reserved_20a                    : 32; //[31:0]
84              uint32_t reserved_21a                    : 32; //[31:0]
85              uint32_t reserved_22a                    : 32; //[31:0]
86              uint32_t reserved_23a                    : 32; //[31:0]
87              uint32_t reserved_24a                    : 28, //[27:0]
88                       looping_count                   :  4; //[31:28]
89 };
90 
91 /*
92 
93 struct uniform_reo_status_header status_header
94 
95 			Consumer: SW
96 
97 			Producer: REO
98 
99 
100 
101 			Details that can link this status with the original
102 			command. It also contains info on how long REO took to
103 			execute this command.
104 
105 reserved_2a
106 
107 			<legal 0>
108 
109 reserved_3a
110 
111 			<legal 0>
112 
113 reserved_4a
114 
115 			<legal 0>
116 
117 reserved_5a
118 
119 			<legal 0>
120 
121 reserved_6a
122 
123 			<legal 0>
124 
125 reserved_7a
126 
127 			<legal 0>
128 
129 reserved_8a
130 
131 			<legal 0>
132 
133 reserved_9a
134 
135 			<legal 0>
136 
137 reserved_10a
138 
139 			<legal 0>
140 
141 reserved_11a
142 
143 			<legal 0>
144 
145 reserved_12a
146 
147 			<legal 0>
148 
149 reserved_13a
150 
151 			<legal 0>
152 
153 reserved_14a
154 
155 			<legal 0>
156 
157 reserved_15a
158 
159 			<legal 0>
160 
161 reserved_16a
162 
163 			<legal 0>
164 
165 reserved_17a
166 
167 			<legal 0>
168 
169 reserved_18a
170 
171 			<legal 0>
172 
173 reserved_19a
174 
175 			<legal 0>
176 
177 reserved_20a
178 
179 			<legal 0>
180 
181 reserved_21a
182 
183 			<legal 0>
184 
185 reserved_22a
186 
187 			<legal 0>
188 
189 reserved_23a
190 
191 			<legal 0>
192 
193 reserved_24a
194 
195 			<legal 0>
196 
197 looping_count
198 
199 			A count value that indicates the number of times the
200 			producer of entries into this Ring has looped around the
201 			ring.
202 
203 			At initialization time, this value is set to 0. On the
204 			first loop, this value is set to 1. After the max value is
205 			reached allowed by the number of bits for this field, the
206 			count value continues with 0 again.
207 
208 
209 
210 			In case SW is the consumer of the ring entries, it can
211 			use this field to figure out up to where the producer of
212 			entries has created new entries. This eliminates the need to
213 			check where the head pointer' of the ring is located once
214 			the SW starts processing an interrupt indicating that new
215 			entries have been put into this ring...
216 
217 
218 
219 			Also note that SW if it wants only needs to look at the
220 			LSB bit of this count value.
221 
222 			<legal all>
223 */
224 
225 
226  /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
227 
228 
229 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
230 
231 			Consumer: SW , DEBUG
232 
233 			Producer: REO
234 
235 
236 
237 			The value in this field is equal to value of the
238 			'REO_CMD_Number' field the REO command
239 
240 
241 
242 			This field helps to correlate the statuses with the REO
243 			commands.
244 
245 
246 
247 			<legal all>
248 */
249 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
250 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
251 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
252 
253 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
254 
255 			Consumer: DEBUG
256 
257 			Producer: REO
258 
259 
260 
261 			The amount of time REO took to excecute the command.
262 			Note that this time does not include the duration of the
263 			command waiting in the command ring, before the execution
264 			started.
265 
266 
267 
268 			In us.
269 
270 
271 
272 			<legal all>
273 */
274 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
275 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
276 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
277 
278 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
279 
280 			Consumer: DEBUG
281 
282 			Producer: REO
283 
284 
285 
286 			Execution status of the command.
287 
288 
289 
290 			<enum 0 reo_successful_execution> Command has
291 			successfully be executed
292 
293 			<enum 1 reo_blocked_execution> Command could not be
294 			executed as the queue or cache was blocked
295 
296 			<enum 2 reo_failed_execution> Command has encountered
297 			problems when executing, like the queue descriptor not being
298 			valid. None of the status fields in the entire STATUS TLV
299 			are valid.
300 
301 			<enum 3 reo_resource_blocked> Command is NOT  executed
302 			because one or more descriptors were blocked. This is SW
303 			programming mistake.
304 
305 			None of the status fields in the entire STATUS TLV are
306 			valid.
307 
308 
309 
310 			<legal  0-3>
311 */
312 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
313 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
314 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
315 
316 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A
317 
318 			<legal 0>
319 */
320 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
321 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
322 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
323 
324 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP
325 
326 			Timestamp at the moment that this status report is
327 			written.
328 
329 
330 
331 			<legal all>
332 */
333 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
334 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
335 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
336 
337 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A
338 
339 			<legal 0>
340 */
341 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET          0x00000008
342 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB             0
343 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK            0xffffffff
344 
345 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A
346 
347 			<legal 0>
348 */
349 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET          0x0000000c
350 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB             0
351 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK            0xffffffff
352 
353 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A
354 
355 			<legal 0>
356 */
357 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET          0x00000010
358 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB             0
359 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK            0xffffffff
360 
361 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A
362 
363 			<legal 0>
364 */
365 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET          0x00000014
366 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB             0
367 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK            0xffffffff
368 
369 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A
370 
371 			<legal 0>
372 */
373 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET          0x00000018
374 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB             0
375 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK            0xffffffff
376 
377 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A
378 
379 			<legal 0>
380 */
381 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET          0x0000001c
382 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB             0
383 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK            0xffffffff
384 
385 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A
386 
387 			<legal 0>
388 */
389 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET          0x00000020
390 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB             0
391 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK            0xffffffff
392 
393 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A
394 
395 			<legal 0>
396 */
397 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET          0x00000024
398 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB             0
399 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK            0xffffffff
400 
401 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A
402 
403 			<legal 0>
404 */
405 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET        0x00000028
406 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB           0
407 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK          0xffffffff
408 
409 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A
410 
411 			<legal 0>
412 */
413 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET        0x0000002c
414 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB           0
415 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK          0xffffffff
416 
417 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A
418 
419 			<legal 0>
420 */
421 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET        0x00000030
422 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB           0
423 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK          0xffffffff
424 
425 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A
426 
427 			<legal 0>
428 */
429 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET        0x00000034
430 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB           0
431 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK          0xffffffff
432 
433 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A
434 
435 			<legal 0>
436 */
437 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET        0x00000038
438 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB           0
439 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK          0xffffffff
440 
441 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A
442 
443 			<legal 0>
444 */
445 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET        0x0000003c
446 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB           0
447 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK          0xffffffff
448 
449 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A
450 
451 			<legal 0>
452 */
453 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET        0x00000040
454 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB           0
455 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK          0xffffffff
456 
457 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A
458 
459 			<legal 0>
460 */
461 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET        0x00000044
462 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB           0
463 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK          0xffffffff
464 
465 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A
466 
467 			<legal 0>
468 */
469 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET        0x00000048
470 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB           0
471 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK          0xffffffff
472 
473 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A
474 
475 			<legal 0>
476 */
477 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET        0x0000004c
478 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB           0
479 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK          0xffffffff
480 
481 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A
482 
483 			<legal 0>
484 */
485 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET        0x00000050
486 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB           0
487 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK          0xffffffff
488 
489 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A
490 
491 			<legal 0>
492 */
493 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET        0x00000054
494 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB           0
495 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK          0xffffffff
496 
497 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A
498 
499 			<legal 0>
500 */
501 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET        0x00000058
502 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB           0
503 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK          0xffffffff
504 
505 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A
506 
507 			<legal 0>
508 */
509 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET        0x0000005c
510 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB           0
511 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK          0xffffffff
512 
513 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A
514 
515 			<legal 0>
516 */
517 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET        0x00000060
518 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB           0
519 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK          0x0fffffff
520 
521 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT
522 
523 			A count value that indicates the number of times the
524 			producer of entries into this Ring has looped around the
525 			ring.
526 
527 			At initialization time, this value is set to 0. On the
528 			first loop, this value is set to 1. After the max value is
529 			reached allowed by the number of bits for this field, the
530 			count value continues with 0 again.
531 
532 
533 
534 			In case SW is the consumer of the ring entries, it can
535 			use this field to figure out up to where the producer of
536 			entries has created new entries. This eliminates the need to
537 			check where the head pointer' of the ring is located once
538 			the SW starts processing an interrupt indicating that new
539 			entries have been put into this ring...
540 
541 
542 
543 			Also note that SW if it wants only needs to look at the
544 			LSB bit of this count value.
545 
546 			<legal all>
547 */
548 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET       0x00000060
549 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB          28
550 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK         0xf0000000
551 
552 
553 #endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
554