xref: /wlan-driver/fw-api/hw/qca6490/v1/rx_attention.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2019 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 //
20 // DO NOT EDIT!  This file is automatically generated
21 //               These definitions are tied to a particular hardware layout
22 
23 
24 #ifndef _RX_ATTENTION_H_
25 #define _RX_ATTENTION_H_
26 #if !defined(__ASSEMBLER__)
27 #endif
28 
29 
30 // ################ START SUMMARY #################
31 //
32 //	Dword	Fields
33 //	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
34 //	1	first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31]
35 //	2	flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31]
36 //
37 // ################ END SUMMARY #################
38 
39 #define NUM_OF_DWORDS_RX_ATTENTION 3
40 
41 struct rx_attention {
42              uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
43                       sw_frame_group_id               :  7, //[8:2]
44                       reserved_0                      :  7, //[15:9]
45                       phy_ppdu_id                     : 16; //[31:16]
46              uint32_t first_mpdu                      :  1, //[0]
47                       reserved_1a                     :  1, //[1]
48                       mcast_bcast                     :  1, //[2]
49                       ast_index_not_found             :  1, //[3]
50                       ast_index_timeout               :  1, //[4]
51                       power_mgmt                      :  1, //[5]
52                       non_qos                         :  1, //[6]
53                       null_data                       :  1, //[7]
54                       mgmt_type                       :  1, //[8]
55                       ctrl_type                       :  1, //[9]
56                       more_data                       :  1, //[10]
57                       eosp                            :  1, //[11]
58                       a_msdu_error                    :  1, //[12]
59                       fragment_flag                   :  1, //[13]
60                       order                           :  1, //[14]
61                       cce_match                       :  1, //[15]
62                       overflow_err                    :  1, //[16]
63                       msdu_length_err                 :  1, //[17]
64                       tcp_udp_chksum_fail             :  1, //[18]
65                       ip_chksum_fail                  :  1, //[19]
66                       sa_idx_invalid                  :  1, //[20]
67                       da_idx_invalid                  :  1, //[21]
68                       reserved_1b                     :  1, //[22]
69                       rx_in_tx_decrypt_byp            :  1, //[23]
70                       encrypt_required                :  1, //[24]
71                       directed                        :  1, //[25]
72                       buffer_fragment                 :  1, //[26]
73                       mpdu_length_err                 :  1, //[27]
74                       tkip_mic_err                    :  1, //[28]
75                       decrypt_err                     :  1, //[29]
76                       unencrypted_frame_err           :  1, //[30]
77                       fcs_err                         :  1; //[31]
78              uint32_t flow_idx_timeout                :  1, //[0]
79                       flow_idx_invalid                :  1, //[1]
80                       wifi_parser_error               :  1, //[2]
81                       amsdu_parser_error              :  1, //[3]
82                       sa_idx_timeout                  :  1, //[4]
83                       da_idx_timeout                  :  1, //[5]
84                       msdu_limit_error                :  1, //[6]
85                       da_is_valid                     :  1, //[7]
86                       da_is_mcbc                      :  1, //[8]
87                       sa_is_valid                     :  1, //[9]
88                       decrypt_status_code             :  3, //[12:10]
89                       rx_bitmap_not_updated           :  1, //[13]
90                       reserved_2                      : 17, //[30:14]
91                       msdu_done                       :  1; //[31]
92 };
93 
94 /*
95 
96 rxpcu_mpdu_filter_in_category
97 
98 			Field indicates what the reason was that this MPDU frame
99 			was allowed to come into the receive path by RXPCU
100 
101 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
102 			frame filter programming of rxpcu
103 
104 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
105 			regular frame filter and would have been dropped, were it
106 			not for the frame fitting into the 'monitor_client'
107 			category.
108 
109 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
110 			regular frame filter and also did not pass the
111 			rxpcu_monitor_client filter. It would have been dropped
112 			accept that it did pass the 'monitor_other' category.
113 
114 			<legal 0-2>
115 
116 sw_frame_group_id
117 
118 			SW processes frames based on certain classifications.
119 			This field indicates to what sw classification this MPDU is
120 			mapped.
121 
122 			The classification is given in priority order
123 
124 
125 
126 			<enum 0 sw_frame_group_NDP_frame>
127 
128 
129 
130 			<enum 1 sw_frame_group_Multicast_data>
131 
132 			<enum 2 sw_frame_group_Unicast_data>
133 
134 			<enum 3 sw_frame_group_Null_data > This includes mpdus
135 			of type Data Null as well as QoS Data Null
136 
137 
138 
139 			<enum 4 sw_frame_group_mgmt_0000 >
140 
141 			<enum 5 sw_frame_group_mgmt_0001 >
142 
143 			<enum 6 sw_frame_group_mgmt_0010 >
144 
145 			<enum 7 sw_frame_group_mgmt_0011 >
146 
147 			<enum 8 sw_frame_group_mgmt_0100 >
148 
149 			<enum 9 sw_frame_group_mgmt_0101 >
150 
151 			<enum 10 sw_frame_group_mgmt_0110 >
152 
153 			<enum 11 sw_frame_group_mgmt_0111 >
154 
155 			<enum 12 sw_frame_group_mgmt_1000 >
156 
157 			<enum 13 sw_frame_group_mgmt_1001 >
158 
159 			<enum 14 sw_frame_group_mgmt_1010 >
160 
161 			<enum 15 sw_frame_group_mgmt_1011 >
162 
163 			<enum 16 sw_frame_group_mgmt_1100 >
164 
165 			<enum 17 sw_frame_group_mgmt_1101 >
166 
167 			<enum 18 sw_frame_group_mgmt_1110 >
168 
169 			<enum 19 sw_frame_group_mgmt_1111 >
170 
171 
172 
173 			<enum 20 sw_frame_group_ctrl_0000 >
174 
175 			<enum 21 sw_frame_group_ctrl_0001 >
176 
177 			<enum 22 sw_frame_group_ctrl_0010 >
178 
179 			<enum 23 sw_frame_group_ctrl_0011 >
180 
181 			<enum 24 sw_frame_group_ctrl_0100 >
182 
183 			<enum 25 sw_frame_group_ctrl_0101 >
184 
185 			<enum 26 sw_frame_group_ctrl_0110 >
186 
187 			<enum 27 sw_frame_group_ctrl_0111 >
188 
189 			<enum 28 sw_frame_group_ctrl_1000 >
190 
191 			<enum 29 sw_frame_group_ctrl_1001 >
192 
193 			<enum 30 sw_frame_group_ctrl_1010 >
194 
195 			<enum 31 sw_frame_group_ctrl_1011 >
196 
197 			<enum 32 sw_frame_group_ctrl_1100 >
198 
199 			<enum 33 sw_frame_group_ctrl_1101 >
200 
201 			<enum 34 sw_frame_group_ctrl_1110 >
202 
203 			<enum 35 sw_frame_group_ctrl_1111 >
204 
205 
206 
207 			<enum 36 sw_frame_group_unsupported> This covers type 3
208 			and protocol version != 0
209 
210 
211 
212 
213 
214 
215 			<legal 0-37>
216 
217 reserved_0
218 
219 			<legal 0>
220 
221 phy_ppdu_id
222 
223 			A ppdu counter value that PHY increments for every PPDU
224 			received. The counter value wraps around
225 
226 			<legal all>
227 
228 first_mpdu
229 
230 			Indicates the first MSDU of the PPDU.  If both
231 			first_mpdu and last_mpdu are set in the MSDU then this is a
232 			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
233 			in an A-MPDU shall have both first_mpdu and last_mpdu bits
234 			set to 0.  The PPDU start status will only be valid when
235 			this bit is set.
236 
237 reserved_1a
238 
239 			<legal 0>
240 
241 mcast_bcast
242 
243 			Multicast / broadcast indicator.  Only set when the MAC
244 			address 1 bit 0 is set indicating mcast/bcast and the BSSID
245 			matches one of the 4 BSSID registers. Only set when
246 			first_msdu is set.
247 
248 ast_index_not_found
249 
250 			Only valid when first_msdu is set.
251 
252 
253 
254 			Indicates no AST matching entries within the the max
255 			search count.
256 
257 ast_index_timeout
258 
259 			Only valid when first_msdu is set.
260 
261 
262 
263 			Indicates an unsuccessful search in the address seach
264 			table due to timeout.
265 
266 power_mgmt
267 
268 			Power management bit set in the 802.11 header.  Only set
269 			when first_msdu is set.
270 
271 non_qos
272 
273 			Set if packet is not a non-QoS data frame.  Only set
274 			when first_msdu is set.
275 
276 null_data
277 
278 			Set if frame type indicates either null data or QoS null
279 			data format.  Only set when first_msdu is set.
280 
281 mgmt_type
282 
283 			Set if packet is a management packet.  Only set when
284 			first_msdu is set.
285 
286 ctrl_type
287 
288 			Set if packet is a control packet.  Only set when
289 			first_msdu is set.
290 
291 more_data
292 
293 			Set if more bit in frame control is set.  Only set when
294 			first_msdu is set.
295 
296 eosp
297 
298 			Set if the EOSP (end of service period) bit in the QoS
299 			control field is set.  Only set when first_msdu is set.
300 
301 a_msdu_error
302 
303 			Set if number of MSDUs in A-MSDU is above a threshold or
304 			if the size of the MSDU is invalid.  This receive buffer
305 			will contain all of the remainder of the MSDUs in this MPDU
306 			without decapsulation.
307 
308 fragment_flag
309 
310 			Indicates that this is an 802.11 fragment frame.  This
311 			is set when either the more_frag bit is set in the frame
312 			control or the fragment number is not zero.  Only set when
313 			first_msdu is set.
314 
315 order
316 
317 			Set if the order bit in the frame control is set.  Only
318 			set when first_msdu is set.
319 
320 cce_match
321 
322 			Indicates that this status has a corresponding MSDU that
323 			requires FW processing.  The OLE will have classification
324 			ring mask registers which will indicate the ring(s) for
325 			packets and descriptors which need FW attention.
326 
327 overflow_err
328 
329 			RXPCU Receive FIFO ran out of space to receive the full
330 			MPDU. Therefor this MPDU is terminated early and is thus
331 			corrupted.
332 
333 
334 
335 			This MPDU will not be ACKed.
336 
337 			RXPCU might still be able to correctly receive the
338 			following MPDUs in the PPDU if enough fifo space became
339 			available in time
340 
341 msdu_length_err
342 
343 			Indicates that the MSDU length from the 802.3
344 			encapsulated length field extends beyond the MPDU boundary
345 			or if the length is less than 14 bytes.
346 
347 			Merged with original other_msdu_err: Indicates that the
348 			MSDU threshold was exceeded and thus all the rest of the
349 			MSDUs will not be scattered and will not be decasulated but
350 			will be DMA'ed in RAW format as a single MSDU buffer
351 
352 tcp_udp_chksum_fail
353 
354 			Indicates that the computed checksum (tcp_udp_chksum)
355 			did not match the checksum in the TCP/UDP header.
356 
357 ip_chksum_fail
358 
359 			Indicates that the computed checksum did not match the
360 			checksum in the IP header.
361 
362 sa_idx_invalid
363 
364 			Indicates no matching entry was found in the address
365 			search table for the source MAC address.
366 
367 da_idx_invalid
368 
369 			Indicates no matching entry was found in the address
370 			search table for the destination MAC address.
371 
372 reserved_1b
373 
374 			<legal 0>
375 
376 rx_in_tx_decrypt_byp
377 
378 			Indicates that RX packet is not decrypted as Crypto is
379 			busy with TX packet processing.
380 
381 encrypt_required
382 
383 			Indicates that this data type frame is not encrypted
384 			even if the policy for this MPDU requires encryption as
385 			indicated in the peer entry key type.
386 
387 directed
388 
389 			MPDU is a directed packet which means that the RA
390 			matched our STA addresses.  In proxySTA it means that the TA
391 			matched an entry in our address search table with the
392 			corresponding no_ack bit is the address search entry
393 			cleared.
394 
395 buffer_fragment
396 
397 			Indicates that at least one of the rx buffers has been
398 			fragmented.  If set the FW should look at the rx_frag_info
399 			descriptor described below.
400 
401 mpdu_length_err
402 
403 			Indicates that the MPDU was pre-maturely terminated
404 			resulting in a truncated MPDU.  Don't trust the MPDU length
405 			field.
406 
407 tkip_mic_err
408 
409 			Indicates that the MPDU Michael integrity check failed
410 
411 decrypt_err
412 
413 			Indicates that the MPDU decrypt integrity check failed
414 			or CRYPTO received an encrypted frame, but did not get a
415 			valid corresponding key id in the peer entry.
416 
417 unencrypted_frame_err
418 
419 			Copied here by RX OLE from the RX_MPDU_END TLV
420 
421 fcs_err
422 
423 			Indicates that the MPDU FCS check failed
424 
425 flow_idx_timeout
426 
427 			Indicates an unsuccessful flow search due to the
428 			expiring of the search timer.
429 
430 			<legal all>
431 
432 flow_idx_invalid
433 
434 			flow id is not valid
435 
436 			<legal all>
437 
438 wifi_parser_error
439 
440 			Indicates that the WiFi frame has one of the following
441 			errors
442 
443 			o has less than minimum allowed bytes as per standard
444 
445 			o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
446 
447 			<legal all>
448 
449 amsdu_parser_error
450 
451 			A-MSDU could not be properly de-agregated.
452 
453 			<legal all>
454 
455 sa_idx_timeout
456 
457 			Indicates an unsuccessful MAC source address search due
458 			to the expiring of the search timer.
459 
460 da_idx_timeout
461 
462 			Indicates an unsuccessful MAC destination address search
463 			due to the expiring of the search timer.
464 
465 msdu_limit_error
466 
467 			Indicates that the MSDU threshold was exceeded and thus
468 			all the rest of the MSDUs will not be scattered and will not
469 			be decasulated but will be DMA'ed in RAW format as a single
470 			MSDU buffer
471 
472 da_is_valid
473 
474 			Indicates that OLE found a valid DA entry
475 
476 da_is_mcbc
477 
478 			Field Only valid if da_is_valid is set
479 
480 
481 
482 			Indicates the DA address was a Multicast of Broadcast
483 			address.
484 
485 sa_is_valid
486 
487 			Indicates that OLE found a valid SA entry
488 
489 decrypt_status_code
490 
491 			Field provides insight into the decryption performed
492 
493 
494 
495 			<enum 0 decrypt_ok> Frame had protection enabled and
496 			decrypted properly
497 
498 			<enum 1 decrypt_unprotected_frame > Frame is unprotected
499 			and hence bypassed
500 
501 			<enum 2 decrypt_data_err > Frame has protection enabled
502 			and could not be properly decrypted due to MIC/ICV mismatch
503 			etc.
504 
505 			<enum 3 decrypt_key_invalid > Frame has protection
506 			enabled but the key that was required to decrypt this frame
507 			was not valid
508 
509 			<enum 4 decrypt_peer_entry_invalid > Frame has
510 			protection enabled but the key that was required to decrypt
511 			this frame was not valid
512 
513 			<enum 5 decrypt_other > Reserved for other indications
514 
515 
516 
517 			<legal 0 - 5>
518 
519 rx_bitmap_not_updated
520 
521 			Frame is received, but RXPCU could not update the
522 			receive bitmap due to (temporary) fifo contraints.
523 
524 			<legal all>
525 
526 reserved_2
527 
528 			<legal 0>
529 
530 msdu_done
531 
532 			If set indicates that the RX packet data, RX header
533 			data, RX PPDU start descriptor, RX MPDU start/end
534 			descriptor, RX MSDU start/end descriptors and RX Attention
535 			descriptor are all valid.  This bit must be in the last
536 			octet of the descriptor.
537 */
538 
539 
540 /* Description		RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY
541 
542 			Field indicates what the reason was that this MPDU frame
543 			was allowed to come into the receive path by RXPCU
544 
545 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
546 			frame filter programming of rxpcu
547 
548 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
549 			regular frame filter and would have been dropped, were it
550 			not for the frame fitting into the 'monitor_client'
551 			category.
552 
553 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
554 			regular frame filter and also did not pass the
555 			rxpcu_monitor_client filter. It would have been dropped
556 			accept that it did pass the 'monitor_other' category.
557 
558 			<legal 0-2>
559 */
560 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000000
561 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
562 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
563 
564 /* Description		RX_ATTENTION_0_SW_FRAME_GROUP_ID
565 
566 			SW processes frames based on certain classifications.
567 			This field indicates to what sw classification this MPDU is
568 			mapped.
569 
570 			The classification is given in priority order
571 
572 
573 
574 			<enum 0 sw_frame_group_NDP_frame>
575 
576 
577 
578 			<enum 1 sw_frame_group_Multicast_data>
579 
580 			<enum 2 sw_frame_group_Unicast_data>
581 
582 			<enum 3 sw_frame_group_Null_data > This includes mpdus
583 			of type Data Null as well as QoS Data Null
584 
585 
586 
587 			<enum 4 sw_frame_group_mgmt_0000 >
588 
589 			<enum 5 sw_frame_group_mgmt_0001 >
590 
591 			<enum 6 sw_frame_group_mgmt_0010 >
592 
593 			<enum 7 sw_frame_group_mgmt_0011 >
594 
595 			<enum 8 sw_frame_group_mgmt_0100 >
596 
597 			<enum 9 sw_frame_group_mgmt_0101 >
598 
599 			<enum 10 sw_frame_group_mgmt_0110 >
600 
601 			<enum 11 sw_frame_group_mgmt_0111 >
602 
603 			<enum 12 sw_frame_group_mgmt_1000 >
604 
605 			<enum 13 sw_frame_group_mgmt_1001 >
606 
607 			<enum 14 sw_frame_group_mgmt_1010 >
608 
609 			<enum 15 sw_frame_group_mgmt_1011 >
610 
611 			<enum 16 sw_frame_group_mgmt_1100 >
612 
613 			<enum 17 sw_frame_group_mgmt_1101 >
614 
615 			<enum 18 sw_frame_group_mgmt_1110 >
616 
617 			<enum 19 sw_frame_group_mgmt_1111 >
618 
619 
620 
621 			<enum 20 sw_frame_group_ctrl_0000 >
622 
623 			<enum 21 sw_frame_group_ctrl_0001 >
624 
625 			<enum 22 sw_frame_group_ctrl_0010 >
626 
627 			<enum 23 sw_frame_group_ctrl_0011 >
628 
629 			<enum 24 sw_frame_group_ctrl_0100 >
630 
631 			<enum 25 sw_frame_group_ctrl_0101 >
632 
633 			<enum 26 sw_frame_group_ctrl_0110 >
634 
635 			<enum 27 sw_frame_group_ctrl_0111 >
636 
637 			<enum 28 sw_frame_group_ctrl_1000 >
638 
639 			<enum 29 sw_frame_group_ctrl_1001 >
640 
641 			<enum 30 sw_frame_group_ctrl_1010 >
642 
643 			<enum 31 sw_frame_group_ctrl_1011 >
644 
645 			<enum 32 sw_frame_group_ctrl_1100 >
646 
647 			<enum 33 sw_frame_group_ctrl_1101 >
648 
649 			<enum 34 sw_frame_group_ctrl_1110 >
650 
651 			<enum 35 sw_frame_group_ctrl_1111 >
652 
653 
654 
655 			<enum 36 sw_frame_group_unsupported> This covers type 3
656 			and protocol version != 0
657 
658 
659 
660 
661 
662 
663 			<legal 0-37>
664 */
665 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET                      0x00000000
666 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB                         2
667 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK                        0x000001fc
668 
669 /* Description		RX_ATTENTION_0_RESERVED_0
670 
671 			<legal 0>
672 */
673 #define RX_ATTENTION_0_RESERVED_0_OFFSET                             0x00000000
674 #define RX_ATTENTION_0_RESERVED_0_LSB                                9
675 #define RX_ATTENTION_0_RESERVED_0_MASK                               0x0000fe00
676 
677 /* Description		RX_ATTENTION_0_PHY_PPDU_ID
678 
679 			A ppdu counter value that PHY increments for every PPDU
680 			received. The counter value wraps around
681 
682 			<legal all>
683 */
684 #define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET                            0x00000000
685 #define RX_ATTENTION_0_PHY_PPDU_ID_LSB                               16
686 #define RX_ATTENTION_0_PHY_PPDU_ID_MASK                              0xffff0000
687 
688 /* Description		RX_ATTENTION_1_FIRST_MPDU
689 
690 			Indicates the first MSDU of the PPDU.  If both
691 			first_mpdu and last_mpdu are set in the MSDU then this is a
692 			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
693 			in an A-MPDU shall have both first_mpdu and last_mpdu bits
694 			set to 0.  The PPDU start status will only be valid when
695 			this bit is set.
696 */
697 #define RX_ATTENTION_1_FIRST_MPDU_OFFSET                             0x00000004
698 #define RX_ATTENTION_1_FIRST_MPDU_LSB                                0
699 #define RX_ATTENTION_1_FIRST_MPDU_MASK                               0x00000001
700 
701 /* Description		RX_ATTENTION_1_RESERVED_1A
702 
703 			<legal 0>
704 */
705 #define RX_ATTENTION_1_RESERVED_1A_OFFSET                            0x00000004
706 #define RX_ATTENTION_1_RESERVED_1A_LSB                               1
707 #define RX_ATTENTION_1_RESERVED_1A_MASK                              0x00000002
708 
709 /* Description		RX_ATTENTION_1_MCAST_BCAST
710 
711 			Multicast / broadcast indicator.  Only set when the MAC
712 			address 1 bit 0 is set indicating mcast/bcast and the BSSID
713 			matches one of the 4 BSSID registers. Only set when
714 			first_msdu is set.
715 */
716 #define RX_ATTENTION_1_MCAST_BCAST_OFFSET                            0x00000004
717 #define RX_ATTENTION_1_MCAST_BCAST_LSB                               2
718 #define RX_ATTENTION_1_MCAST_BCAST_MASK                              0x00000004
719 
720 /* Description		RX_ATTENTION_1_AST_INDEX_NOT_FOUND
721 
722 			Only valid when first_msdu is set.
723 
724 
725 
726 			Indicates no AST matching entries within the the max
727 			search count.
728 */
729 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET                    0x00000004
730 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB                       3
731 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK                      0x00000008
732 
733 /* Description		RX_ATTENTION_1_AST_INDEX_TIMEOUT
734 
735 			Only valid when first_msdu is set.
736 
737 
738 
739 			Indicates an unsuccessful search in the address seach
740 			table due to timeout.
741 */
742 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET                      0x00000004
743 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB                         4
744 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK                        0x00000010
745 
746 /* Description		RX_ATTENTION_1_POWER_MGMT
747 
748 			Power management bit set in the 802.11 header.  Only set
749 			when first_msdu is set.
750 */
751 #define RX_ATTENTION_1_POWER_MGMT_OFFSET                             0x00000004
752 #define RX_ATTENTION_1_POWER_MGMT_LSB                                5
753 #define RX_ATTENTION_1_POWER_MGMT_MASK                               0x00000020
754 
755 /* Description		RX_ATTENTION_1_NON_QOS
756 
757 			Set if packet is not a non-QoS data frame.  Only set
758 			when first_msdu is set.
759 */
760 #define RX_ATTENTION_1_NON_QOS_OFFSET                                0x00000004
761 #define RX_ATTENTION_1_NON_QOS_LSB                                   6
762 #define RX_ATTENTION_1_NON_QOS_MASK                                  0x00000040
763 
764 /* Description		RX_ATTENTION_1_NULL_DATA
765 
766 			Set if frame type indicates either null data or QoS null
767 			data format.  Only set when first_msdu is set.
768 */
769 #define RX_ATTENTION_1_NULL_DATA_OFFSET                              0x00000004
770 #define RX_ATTENTION_1_NULL_DATA_LSB                                 7
771 #define RX_ATTENTION_1_NULL_DATA_MASK                                0x00000080
772 
773 /* Description		RX_ATTENTION_1_MGMT_TYPE
774 
775 			Set if packet is a management packet.  Only set when
776 			first_msdu is set.
777 */
778 #define RX_ATTENTION_1_MGMT_TYPE_OFFSET                              0x00000004
779 #define RX_ATTENTION_1_MGMT_TYPE_LSB                                 8
780 #define RX_ATTENTION_1_MGMT_TYPE_MASK                                0x00000100
781 
782 /* Description		RX_ATTENTION_1_CTRL_TYPE
783 
784 			Set if packet is a control packet.  Only set when
785 			first_msdu is set.
786 */
787 #define RX_ATTENTION_1_CTRL_TYPE_OFFSET                              0x00000004
788 #define RX_ATTENTION_1_CTRL_TYPE_LSB                                 9
789 #define RX_ATTENTION_1_CTRL_TYPE_MASK                                0x00000200
790 
791 /* Description		RX_ATTENTION_1_MORE_DATA
792 
793 			Set if more bit in frame control is set.  Only set when
794 			first_msdu is set.
795 */
796 #define RX_ATTENTION_1_MORE_DATA_OFFSET                              0x00000004
797 #define RX_ATTENTION_1_MORE_DATA_LSB                                 10
798 #define RX_ATTENTION_1_MORE_DATA_MASK                                0x00000400
799 
800 /* Description		RX_ATTENTION_1_EOSP
801 
802 			Set if the EOSP (end of service period) bit in the QoS
803 			control field is set.  Only set when first_msdu is set.
804 */
805 #define RX_ATTENTION_1_EOSP_OFFSET                                   0x00000004
806 #define RX_ATTENTION_1_EOSP_LSB                                      11
807 #define RX_ATTENTION_1_EOSP_MASK                                     0x00000800
808 
809 /* Description		RX_ATTENTION_1_A_MSDU_ERROR
810 
811 			Set if number of MSDUs in A-MSDU is above a threshold or
812 			if the size of the MSDU is invalid.  This receive buffer
813 			will contain all of the remainder of the MSDUs in this MPDU
814 			without decapsulation.
815 */
816 #define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET                           0x00000004
817 #define RX_ATTENTION_1_A_MSDU_ERROR_LSB                              12
818 #define RX_ATTENTION_1_A_MSDU_ERROR_MASK                             0x00001000
819 
820 /* Description		RX_ATTENTION_1_FRAGMENT_FLAG
821 
822 			Indicates that this is an 802.11 fragment frame.  This
823 			is set when either the more_frag bit is set in the frame
824 			control or the fragment number is not zero.  Only set when
825 			first_msdu is set.
826 */
827 #define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET                          0x00000004
828 #define RX_ATTENTION_1_FRAGMENT_FLAG_LSB                             13
829 #define RX_ATTENTION_1_FRAGMENT_FLAG_MASK                            0x00002000
830 
831 /* Description		RX_ATTENTION_1_ORDER
832 
833 			Set if the order bit in the frame control is set.  Only
834 			set when first_msdu is set.
835 */
836 #define RX_ATTENTION_1_ORDER_OFFSET                                  0x00000004
837 #define RX_ATTENTION_1_ORDER_LSB                                     14
838 #define RX_ATTENTION_1_ORDER_MASK                                    0x00004000
839 
840 /* Description		RX_ATTENTION_1_CCE_MATCH
841 
842 			Indicates that this status has a corresponding MSDU that
843 			requires FW processing.  The OLE will have classification
844 			ring mask registers which will indicate the ring(s) for
845 			packets and descriptors which need FW attention.
846 */
847 #define RX_ATTENTION_1_CCE_MATCH_OFFSET                              0x00000004
848 #define RX_ATTENTION_1_CCE_MATCH_LSB                                 15
849 #define RX_ATTENTION_1_CCE_MATCH_MASK                                0x00008000
850 
851 /* Description		RX_ATTENTION_1_OVERFLOW_ERR
852 
853 			RXPCU Receive FIFO ran out of space to receive the full
854 			MPDU. Therefor this MPDU is terminated early and is thus
855 			corrupted.
856 
857 
858 
859 			This MPDU will not be ACKed.
860 
861 			RXPCU might still be able to correctly receive the
862 			following MPDUs in the PPDU if enough fifo space became
863 			available in time
864 */
865 #define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET                           0x00000004
866 #define RX_ATTENTION_1_OVERFLOW_ERR_LSB                              16
867 #define RX_ATTENTION_1_OVERFLOW_ERR_MASK                             0x00010000
868 
869 /* Description		RX_ATTENTION_1_MSDU_LENGTH_ERR
870 
871 			Indicates that the MSDU length from the 802.3
872 			encapsulated length field extends beyond the MPDU boundary
873 			or if the length is less than 14 bytes.
874 
875 			Merged with original other_msdu_err: Indicates that the
876 			MSDU threshold was exceeded and thus all the rest of the
877 			MSDUs will not be scattered and will not be decasulated but
878 			will be DMA'ed in RAW format as a single MSDU buffer
879 */
880 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET                        0x00000004
881 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB                           17
882 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK                          0x00020000
883 
884 /* Description		RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL
885 
886 			Indicates that the computed checksum (tcp_udp_chksum)
887 			did not match the checksum in the TCP/UDP header.
888 */
889 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET                    0x00000004
890 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB                       18
891 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK                      0x00040000
892 
893 /* Description		RX_ATTENTION_1_IP_CHKSUM_FAIL
894 
895 			Indicates that the computed checksum did not match the
896 			checksum in the IP header.
897 */
898 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET                         0x00000004
899 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB                            19
900 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK                           0x00080000
901 
902 /* Description		RX_ATTENTION_1_SA_IDX_INVALID
903 
904 			Indicates no matching entry was found in the address
905 			search table for the source MAC address.
906 */
907 #define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET                         0x00000004
908 #define RX_ATTENTION_1_SA_IDX_INVALID_LSB                            20
909 #define RX_ATTENTION_1_SA_IDX_INVALID_MASK                           0x00100000
910 
911 /* Description		RX_ATTENTION_1_DA_IDX_INVALID
912 
913 			Indicates no matching entry was found in the address
914 			search table for the destination MAC address.
915 */
916 #define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET                         0x00000004
917 #define RX_ATTENTION_1_DA_IDX_INVALID_LSB                            21
918 #define RX_ATTENTION_1_DA_IDX_INVALID_MASK                           0x00200000
919 
920 /* Description		RX_ATTENTION_1_RESERVED_1B
921 
922 			<legal 0>
923 */
924 #define RX_ATTENTION_1_RESERVED_1B_OFFSET                            0x00000004
925 #define RX_ATTENTION_1_RESERVED_1B_LSB                               22
926 #define RX_ATTENTION_1_RESERVED_1B_MASK                              0x00400000
927 
928 /* Description		RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP
929 
930 			Indicates that RX packet is not decrypted as Crypto is
931 			busy with TX packet processing.
932 */
933 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET                   0x00000004
934 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB                      23
935 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK                     0x00800000
936 
937 /* Description		RX_ATTENTION_1_ENCRYPT_REQUIRED
938 
939 			Indicates that this data type frame is not encrypted
940 			even if the policy for this MPDU requires encryption as
941 			indicated in the peer entry key type.
942 */
943 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET                       0x00000004
944 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB                          24
945 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK                         0x01000000
946 
947 /* Description		RX_ATTENTION_1_DIRECTED
948 
949 			MPDU is a directed packet which means that the RA
950 			matched our STA addresses.  In proxySTA it means that the TA
951 			matched an entry in our address search table with the
952 			corresponding no_ack bit is the address search entry
953 			cleared.
954 */
955 #define RX_ATTENTION_1_DIRECTED_OFFSET                               0x00000004
956 #define RX_ATTENTION_1_DIRECTED_LSB                                  25
957 #define RX_ATTENTION_1_DIRECTED_MASK                                 0x02000000
958 
959 /* Description		RX_ATTENTION_1_BUFFER_FRAGMENT
960 
961 			Indicates that at least one of the rx buffers has been
962 			fragmented.  If set the FW should look at the rx_frag_info
963 			descriptor described below.
964 */
965 #define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET                        0x00000004
966 #define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB                           26
967 #define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK                          0x04000000
968 
969 /* Description		RX_ATTENTION_1_MPDU_LENGTH_ERR
970 
971 			Indicates that the MPDU was pre-maturely terminated
972 			resulting in a truncated MPDU.  Don't trust the MPDU length
973 			field.
974 */
975 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET                        0x00000004
976 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB                           27
977 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK                          0x08000000
978 
979 /* Description		RX_ATTENTION_1_TKIP_MIC_ERR
980 
981 			Indicates that the MPDU Michael integrity check failed
982 */
983 #define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET                           0x00000004
984 #define RX_ATTENTION_1_TKIP_MIC_ERR_LSB                              28
985 #define RX_ATTENTION_1_TKIP_MIC_ERR_MASK                             0x10000000
986 
987 /* Description		RX_ATTENTION_1_DECRYPT_ERR
988 
989 			Indicates that the MPDU decrypt integrity check failed
990 			or CRYPTO received an encrypted frame, but did not get a
991 			valid corresponding key id in the peer entry.
992 */
993 #define RX_ATTENTION_1_DECRYPT_ERR_OFFSET                            0x00000004
994 #define RX_ATTENTION_1_DECRYPT_ERR_LSB                               29
995 #define RX_ATTENTION_1_DECRYPT_ERR_MASK                              0x20000000
996 
997 /* Description		RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR
998 
999 			Copied here by RX OLE from the RX_MPDU_END TLV
1000 */
1001 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET                  0x00000004
1002 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB                     30
1003 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK                    0x40000000
1004 
1005 /* Description		RX_ATTENTION_1_FCS_ERR
1006 
1007 			Indicates that the MPDU FCS check failed
1008 */
1009 #define RX_ATTENTION_1_FCS_ERR_OFFSET                                0x00000004
1010 #define RX_ATTENTION_1_FCS_ERR_LSB                                   31
1011 #define RX_ATTENTION_1_FCS_ERR_MASK                                  0x80000000
1012 
1013 /* Description		RX_ATTENTION_2_FLOW_IDX_TIMEOUT
1014 
1015 			Indicates an unsuccessful flow search due to the
1016 			expiring of the search timer.
1017 
1018 			<legal all>
1019 */
1020 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET                       0x00000008
1021 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB                          0
1022 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK                         0x00000001
1023 
1024 /* Description		RX_ATTENTION_2_FLOW_IDX_INVALID
1025 
1026 			flow id is not valid
1027 
1028 			<legal all>
1029 */
1030 #define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET                       0x00000008
1031 #define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB                          1
1032 #define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK                         0x00000002
1033 
1034 /* Description		RX_ATTENTION_2_WIFI_PARSER_ERROR
1035 
1036 			Indicates that the WiFi frame has one of the following
1037 			errors
1038 
1039 			o has less than minimum allowed bytes as per standard
1040 
1041 			o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
1042 
1043 			<legal all>
1044 */
1045 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET                      0x00000008
1046 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB                         2
1047 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK                        0x00000004
1048 
1049 /* Description		RX_ATTENTION_2_AMSDU_PARSER_ERROR
1050 
1051 			A-MSDU could not be properly de-agregated.
1052 
1053 			<legal all>
1054 */
1055 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET                     0x00000008
1056 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB                        3
1057 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK                       0x00000008
1058 
1059 /* Description		RX_ATTENTION_2_SA_IDX_TIMEOUT
1060 
1061 			Indicates an unsuccessful MAC source address search due
1062 			to the expiring of the search timer.
1063 */
1064 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET                         0x00000008
1065 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB                            4
1066 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK                           0x00000010
1067 
1068 /* Description		RX_ATTENTION_2_DA_IDX_TIMEOUT
1069 
1070 			Indicates an unsuccessful MAC destination address search
1071 			due to the expiring of the search timer.
1072 */
1073 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET                         0x00000008
1074 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB                            5
1075 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK                           0x00000020
1076 
1077 /* Description		RX_ATTENTION_2_MSDU_LIMIT_ERROR
1078 
1079 			Indicates that the MSDU threshold was exceeded and thus
1080 			all the rest of the MSDUs will not be scattered and will not
1081 			be decasulated but will be DMA'ed in RAW format as a single
1082 			MSDU buffer
1083 */
1084 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET                       0x00000008
1085 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB                          6
1086 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK                         0x00000040
1087 
1088 /* Description		RX_ATTENTION_2_DA_IS_VALID
1089 
1090 			Indicates that OLE found a valid DA entry
1091 */
1092 #define RX_ATTENTION_2_DA_IS_VALID_OFFSET                            0x00000008
1093 #define RX_ATTENTION_2_DA_IS_VALID_LSB                               7
1094 #define RX_ATTENTION_2_DA_IS_VALID_MASK                              0x00000080
1095 
1096 /* Description		RX_ATTENTION_2_DA_IS_MCBC
1097 
1098 			Field Only valid if da_is_valid is set
1099 
1100 
1101 
1102 			Indicates the DA address was a Multicast of Broadcast
1103 			address.
1104 */
1105 #define RX_ATTENTION_2_DA_IS_MCBC_OFFSET                             0x00000008
1106 #define RX_ATTENTION_2_DA_IS_MCBC_LSB                                8
1107 #define RX_ATTENTION_2_DA_IS_MCBC_MASK                               0x00000100
1108 
1109 /* Description		RX_ATTENTION_2_SA_IS_VALID
1110 
1111 			Indicates that OLE found a valid SA entry
1112 */
1113 #define RX_ATTENTION_2_SA_IS_VALID_OFFSET                            0x00000008
1114 #define RX_ATTENTION_2_SA_IS_VALID_LSB                               9
1115 #define RX_ATTENTION_2_SA_IS_VALID_MASK                              0x00000200
1116 
1117 /* Description		RX_ATTENTION_2_DECRYPT_STATUS_CODE
1118 
1119 			Field provides insight into the decryption performed
1120 
1121 
1122 
1123 			<enum 0 decrypt_ok> Frame had protection enabled and
1124 			decrypted properly
1125 
1126 			<enum 1 decrypt_unprotected_frame > Frame is unprotected
1127 			and hence bypassed
1128 
1129 			<enum 2 decrypt_data_err > Frame has protection enabled
1130 			and could not be properly decrypted due to MIC/ICV mismatch
1131 			etc.
1132 
1133 			<enum 3 decrypt_key_invalid > Frame has protection
1134 			enabled but the key that was required to decrypt this frame
1135 			was not valid
1136 
1137 			<enum 4 decrypt_peer_entry_invalid > Frame has
1138 			protection enabled but the key that was required to decrypt
1139 			this frame was not valid
1140 
1141 			<enum 5 decrypt_other > Reserved for other indications
1142 
1143 
1144 
1145 			<legal 0 - 5>
1146 */
1147 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET                    0x00000008
1148 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB                       10
1149 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK                      0x00001c00
1150 
1151 /* Description		RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED
1152 
1153 			Frame is received, but RXPCU could not update the
1154 			receive bitmap due to (temporary) fifo contraints.
1155 
1156 			<legal all>
1157 */
1158 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET                  0x00000008
1159 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB                     13
1160 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK                    0x00002000
1161 
1162 /* Description		RX_ATTENTION_2_RESERVED_2
1163 
1164 			<legal 0>
1165 */
1166 #define RX_ATTENTION_2_RESERVED_2_OFFSET                             0x00000008
1167 #define RX_ATTENTION_2_RESERVED_2_LSB                                14
1168 #define RX_ATTENTION_2_RESERVED_2_MASK                               0x7fffc000
1169 
1170 /* Description		RX_ATTENTION_2_MSDU_DONE
1171 
1172 			If set indicates that the RX packet data, RX header
1173 			data, RX PPDU start descriptor, RX MPDU start/end
1174 			descriptor, RX MSDU start/end descriptors and RX Attention
1175 			descriptor are all valid.  This bit must be in the last
1176 			octet of the descriptor.
1177 */
1178 #define RX_ATTENTION_2_MSDU_DONE_OFFSET                              0x00000008
1179 #define RX_ATTENTION_2_MSDU_DONE_LSB                                 31
1180 #define RX_ATTENTION_2_MSDU_DONE_MASK                                0x80000000
1181 
1182 
1183 #endif // _RX_ATTENTION_H_
1184