1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MSDU_LINK_H_ 25 #define _RX_MSDU_LINK_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_descriptor_header.h" 30 #include "buffer_addr_info.h" 31 #include "rx_msdu_details.h" 32 33 // ################ START SUMMARY ################# 34 // 35 // Dword Fields 36 // 0 struct uniform_descriptor_header descriptor_header; 37 // 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info; 38 // 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17] 39 // 4 pn_31_0[31:0] 40 // 5 pn_63_32[31:0] 41 // 6 pn_95_64[31:0] 42 // 7 pn_127_96[31:0] 43 // 8-11 struct rx_msdu_details msdu_0; 44 // 12-15 struct rx_msdu_details msdu_1; 45 // 16-19 struct rx_msdu_details msdu_2; 46 // 20-23 struct rx_msdu_details msdu_3; 47 // 24-27 struct rx_msdu_details msdu_4; 48 // 28-31 struct rx_msdu_details msdu_5; 49 // 50 // ################ END SUMMARY ################# 51 52 #define NUM_OF_DWORDS_RX_MSDU_LINK 32 53 54 struct rx_msdu_link { 55 struct uniform_descriptor_header descriptor_header; 56 struct buffer_addr_info next_msdu_link_desc_addr_info; 57 uint32_t receive_queue_number : 16, //[15:0] 58 first_rx_msdu_link_struct : 1, //[16] 59 reserved_3a : 15; //[31:17] 60 uint32_t pn_31_0 : 32; //[31:0] 61 uint32_t pn_63_32 : 32; //[31:0] 62 uint32_t pn_95_64 : 32; //[31:0] 63 uint32_t pn_127_96 : 32; //[31:0] 64 struct rx_msdu_details msdu_0; 65 struct rx_msdu_details msdu_1; 66 struct rx_msdu_details msdu_2; 67 struct rx_msdu_details msdu_3; 68 struct rx_msdu_details msdu_4; 69 struct rx_msdu_details msdu_5; 70 }; 71 72 /* 73 74 struct uniform_descriptor_header descriptor_header 75 76 Details about which module owns this struct. 77 78 Note that sub field Buffer_type shall be set to 79 Receive_MSDU_Link_descriptor 80 81 struct buffer_addr_info next_msdu_link_desc_addr_info 82 83 Details of the physical address of the next MSDU link 84 descriptor that contains info about additional MSDUs that 85 are part of this MPDU. 86 87 receive_queue_number 88 89 Indicates the Receive queue to which this MPDU 90 descriptor belongs 91 92 Used for tracking, finding bugs and debugging. 93 94 <legal all> 95 96 first_rx_msdu_link_struct 97 98 When set, this RX_MSDU_link descriptor is the first one 99 in the MSDU link list. Field MSDU_0 points to the very first 100 MSDU buffer descriptor in the MPDU 101 102 <legal all> 103 104 reserved_3a 105 106 <legal 0> 107 108 pn_31_0 109 110 111 112 113 31-0 bits of the 256-bit packet number bitmap. 114 115 <legal all> 116 117 pn_63_32 118 119 120 121 122 63-32 bits of the 256-bit packet number bitmap. 123 124 <legal all> 125 126 pn_95_64 127 128 129 130 131 95-64 bits of the 256-bit packet number bitmap. 132 133 <legal all> 134 135 pn_127_96 136 137 138 139 140 127-96 bits of the 256-bit packet number bitmap. 141 142 <legal all> 143 144 struct rx_msdu_details msdu_0 145 146 When First_RX_MSDU_link_struct is set, this MSDU is the 147 first in the MPDU 148 149 150 151 When First_RX_MSDU_link_struct is NOT set, this MSDU 152 follows the last MSDU in the previous RX_MSDU_link data 153 structure 154 155 struct rx_msdu_details msdu_1 156 157 Details of next MSDU in this (MSDU flow) linked list 158 159 struct rx_msdu_details msdu_2 160 161 Details of next MSDU in this (MSDU flow) linked list 162 163 struct rx_msdu_details msdu_3 164 165 Details of next MSDU in this (MSDU flow) linked list 166 167 struct rx_msdu_details msdu_4 168 169 Details of next MSDU in this (MSDU flow) linked list 170 171 struct rx_msdu_details msdu_5 172 173 Details of next MSDU in this (MSDU flow) linked list 174 */ 175 176 177 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 178 179 180 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER 181 182 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 183 184 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 185 186 187 188 The owner of this data structure: 189 190 <enum 0 WBM_owned> Buffer Manager currently owns this 191 data structure. 192 193 <enum 1 SW_OR_FW_owned> Software of FW currently owns 194 this data structure. 195 196 <enum 2 TQM_owned> Transmit Queue Manager currently owns 197 this data structure. 198 199 <enum 3 RXDMA_owned> Receive DMA currently owns this 200 data structure. 201 202 <enum 4 REO_owned> Reorder currently owns this data 203 structure. 204 205 <enum 5 SWITCH_owned> SWITCH currently owns this data 206 structure. 207 208 209 210 <legal 0-5> 211 */ 212 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 213 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0 214 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 215 216 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE 217 218 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 219 220 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 221 222 223 224 Field describing what contents format is of this 225 descriptor 226 227 228 229 <enum 0 Transmit_MSDU_Link_descriptor > 230 231 <enum 1 Transmit_MPDU_Link_descriptor > 232 233 <enum 2 Transmit_MPDU_Queue_head_descriptor> 234 235 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 236 237 <enum 4 Transmit_flow_descriptor> 238 239 <enum 5 Transmit_buffer > NOT TO BE USED: 240 241 242 243 <enum 6 Receive_MSDU_Link_descriptor > 244 245 <enum 7 Receive_MPDU_Link_descriptor > 246 247 <enum 8 Receive_REO_queue_descriptor > 248 249 <enum 9 Receive_REO_queue_ext_descriptor > 250 251 252 253 <enum 10 Receive_buffer > 254 255 256 257 <enum 11 Idle_link_list_entry> 258 259 260 261 <legal 0-11> 262 */ 263 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 264 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 265 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 266 267 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A 268 269 <legal 0> 270 */ 271 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 272 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 273 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 274 275 /* EXTERNAL REFERENCE : struct buffer_addr_info next_msdu_link_desc_addr_info */ 276 277 278 /* Description RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 279 280 Address (lower 32 bits) of the MSDU buffer OR 281 MSDU_EXTENSION descriptor OR Link Descriptor 282 283 284 285 In case of 'NULL' pointer, this field is set to 0 286 287 <legal all> 288 */ 289 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 290 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 291 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 292 293 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 294 295 Address (upper 8 bits) of the MSDU buffer OR 296 MSDU_EXTENSION descriptor OR Link Descriptor 297 298 299 300 In case of 'NULL' pointer, this field is set to 0 301 302 <legal all> 303 */ 304 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 305 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 306 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 307 308 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 309 310 Consumer: WBM 311 312 Producer: SW/FW 313 314 315 316 In case of 'NULL' pointer, this field is set to 0 317 318 319 320 Indicates to which buffer manager the buffer OR 321 MSDU_EXTENSION descriptor OR link descriptor that is being 322 pointed to shall be returned after the frame has been 323 processed. It is used by WBM for routing purposes. 324 325 326 327 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 328 to the WMB buffer idle list 329 330 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 331 returned to the WMB idle link descriptor idle list 332 333 <enum 2 FW_BM> This buffer shall be returned to the FW 334 335 <enum 3 SW0_BM> This buffer shall be returned to the SW, 336 ring 0 337 338 <enum 4 SW1_BM> This buffer shall be returned to the SW, 339 ring 1 340 341 <enum 5 SW2_BM> This buffer shall be returned to the SW, 342 ring 2 343 344 <enum 6 SW3_BM> This buffer shall be returned to the SW, 345 ring 3 346 347 <enum 7 SW4_BM> This buffer shall be returned to the SW, 348 ring 4 349 350 351 352 <legal all> 353 */ 354 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 355 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 356 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 357 358 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 359 360 Cookie field exclusively used by SW. 361 362 363 364 In case of 'NULL' pointer, this field is set to 0 365 366 367 368 HW ignores the contents, accept that it passes the 369 programmed value on to other descriptors together with the 370 physical address 371 372 373 374 Field can be used by SW to for example associate the 375 buffers physical address with the virtual address 376 377 The bit definitions as used by SW are within SW HLD 378 specification 379 380 381 382 NOTE: 383 384 The three most significant bits can have a special 385 meaning in case this struct is embedded in a TX_MPDU_DETAILS 386 STRUCT, and field transmit_bw_restriction is set 387 388 389 390 In case of NON punctured transmission: 391 392 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 393 394 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 395 396 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 397 398 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 399 400 401 402 In case of punctured transmission: 403 404 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 405 406 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 407 408 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 409 410 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 411 412 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 413 414 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 415 416 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 417 418 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 419 420 421 422 Note: a punctured transmission is indicated by the 423 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 424 TLV 425 426 427 428 <legal all> 429 */ 430 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 431 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 432 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 433 434 /* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER 435 436 Indicates the Receive queue to which this MPDU 437 descriptor belongs 438 439 Used for tracking, finding bugs and debugging. 440 441 <legal all> 442 */ 443 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 444 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 445 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 446 447 /* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT 448 449 When set, this RX_MSDU_link descriptor is the first one 450 in the MSDU link list. Field MSDU_0 points to the very first 451 MSDU buffer descriptor in the MPDU 452 453 <legal all> 454 */ 455 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c 456 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 457 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 458 459 /* Description RX_MSDU_LINK_3_RESERVED_3A 460 461 <legal 0> 462 */ 463 #define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c 464 #define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 465 #define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 466 467 /* Description RX_MSDU_LINK_4_PN_31_0 468 469 470 471 472 31-0 bits of the 256-bit packet number bitmap. 473 474 <legal all> 475 */ 476 #define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 477 #define RX_MSDU_LINK_4_PN_31_0_LSB 0 478 #define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff 479 480 /* Description RX_MSDU_LINK_5_PN_63_32 481 482 483 484 485 63-32 bits of the 256-bit packet number bitmap. 486 487 <legal all> 488 */ 489 #define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 490 #define RX_MSDU_LINK_5_PN_63_32_LSB 0 491 #define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff 492 493 /* Description RX_MSDU_LINK_6_PN_95_64 494 495 496 497 498 95-64 bits of the 256-bit packet number bitmap. 499 500 <legal all> 501 */ 502 #define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 503 #define RX_MSDU_LINK_6_PN_95_64_LSB 0 504 #define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff 505 506 /* Description RX_MSDU_LINK_7_PN_127_96 507 508 509 510 511 127-96 bits of the 256-bit packet number bitmap. 512 513 <legal all> 514 */ 515 #define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c 516 #define RX_MSDU_LINK_7_PN_127_96_LSB 0 517 #define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff 518 519 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_0 */ 520 521 522 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 523 524 525 /* Description RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 526 527 Address (lower 32 bits) of the MSDU buffer OR 528 MSDU_EXTENSION descriptor OR Link Descriptor 529 530 531 532 In case of 'NULL' pointer, this field is set to 0 533 534 <legal all> 535 */ 536 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 537 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 538 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 539 540 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 541 542 Address (upper 8 bits) of the MSDU buffer OR 543 MSDU_EXTENSION descriptor OR Link Descriptor 544 545 546 547 In case of 'NULL' pointer, this field is set to 0 548 549 <legal all> 550 */ 551 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 552 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 553 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 554 555 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 556 557 Consumer: WBM 558 559 Producer: SW/FW 560 561 562 563 In case of 'NULL' pointer, this field is set to 0 564 565 566 567 Indicates to which buffer manager the buffer OR 568 MSDU_EXTENSION descriptor OR link descriptor that is being 569 pointed to shall be returned after the frame has been 570 processed. It is used by WBM for routing purposes. 571 572 573 574 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 575 to the WMB buffer idle list 576 577 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 578 returned to the WMB idle link descriptor idle list 579 580 <enum 2 FW_BM> This buffer shall be returned to the FW 581 582 <enum 3 SW0_BM> This buffer shall be returned to the SW, 583 ring 0 584 585 <enum 4 SW1_BM> This buffer shall be returned to the SW, 586 ring 1 587 588 <enum 5 SW2_BM> This buffer shall be returned to the SW, 589 ring 2 590 591 <enum 6 SW3_BM> This buffer shall be returned to the SW, 592 ring 3 593 594 <enum 7 SW4_BM> This buffer shall be returned to the SW, 595 ring 4 596 597 598 599 <legal all> 600 */ 601 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 602 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 603 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 604 605 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 606 607 Cookie field exclusively used by SW. 608 609 610 611 In case of 'NULL' pointer, this field is set to 0 612 613 614 615 HW ignores the contents, accept that it passes the 616 programmed value on to other descriptors together with the 617 physical address 618 619 620 621 Field can be used by SW to for example associate the 622 buffers physical address with the virtual address 623 624 The bit definitions as used by SW are within SW HLD 625 specification 626 627 628 629 NOTE: 630 631 The three most significant bits can have a special 632 meaning in case this struct is embedded in a TX_MPDU_DETAILS 633 STRUCT, and field transmit_bw_restriction is set 634 635 636 637 In case of NON punctured transmission: 638 639 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 640 641 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 642 643 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 644 645 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 646 647 648 649 In case of punctured transmission: 650 651 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 652 653 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 654 655 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 656 657 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 658 659 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 660 661 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 662 663 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 664 665 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 666 667 668 669 Note: a punctured transmission is indicated by the 670 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 671 TLV 672 673 674 675 <legal all> 676 */ 677 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 678 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 679 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 680 681 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 682 683 684 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 685 686 Parsed from RX_MSDU_END TLV . In the case MSDU spans 687 over multiple buffers, this field will be valid in the Last 688 buffer used by the MSDU 689 690 691 692 <enum 0 Not_first_msdu> This is not the first MSDU in 693 the MPDU. 694 695 <enum 1 first_msdu> This MSDU is the first one in the 696 MPDU. 697 698 699 700 <legal all> 701 */ 702 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 703 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 704 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 705 706 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 707 708 Consumer: WBM/REO/SW/FW 709 710 Producer: RXDMA 711 712 713 714 Parsed from RX_MSDU_END TLV . In the case MSDU spans 715 over multiple buffers, this field will be valid in the Last 716 buffer used by the MSDU 717 718 719 720 <enum 0 Not_last_msdu> There are more MSDUs linked to 721 this MSDU that belongs to this MPDU 722 723 <enum 1 Last_msdu> this MSDU is the last one in the 724 MPDU. This setting is only allowed in combination with 725 'Msdu_continuation' set to 0. This implies that when an msdu 726 is spread out over multiple buffers and thus 727 msdu_continuation is set, only for the very last buffer of 728 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 729 730 731 732 When both first_msdu_in_mpdu_flag and 733 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 734 belongs to only contains a single MSDU. 735 736 737 738 739 740 <legal all> 741 */ 742 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 743 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 744 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 745 746 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 747 748 When set, this MSDU buffer was not able to hold the 749 entire MSDU. The next buffer will therefor contain 750 additional information related to this MSDU. 751 752 753 754 <legal all> 755 */ 756 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 757 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 758 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 759 760 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 761 762 Parsed from RX_MSDU_START TLV . In the case MSDU spans 763 over multiple buffers, this field will be valid in the First 764 buffer used by MSDU. 765 766 767 768 Full MSDU length in bytes after decapsulation. 769 770 771 772 This field is still valid for MPDU frames without 773 A-MSDU. It still represents MSDU length after decapsulation 774 775 776 777 Or in case of RAW MPDUs, it indicates the length of the 778 entire MPDU (without FCS field) 779 780 <legal all> 781 */ 782 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 783 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 784 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 785 786 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 787 788 Parsed from RX_MSDU_END TLV . In the case MSDU spans 789 over multiple buffers, this field will be valid in the Last 790 buffer used by the MSDU 791 792 793 794 The ID of the REO exit ring where the MSDU frame shall 795 push after (MPDU level) reordering has finished. 796 797 798 799 <enum 0 reo_destination_tcl> Reo will push the frame 800 into the REO2TCL ring 801 802 <enum 1 reo_destination_sw1> Reo will push the frame 803 into the REO2SW1 ring 804 805 <enum 2 reo_destination_sw2> Reo will push the frame 806 into the REO2SW2 ring 807 808 <enum 3 reo_destination_sw3> Reo will push the frame 809 into the REO2SW3 ring 810 811 <enum 4 reo_destination_sw4> Reo will push the frame 812 into the REO2SW4 ring 813 814 <enum 5 reo_destination_release> Reo will push the frame 815 into the REO_release ring 816 817 <enum 6 reo_destination_fw> Reo will push the frame into 818 the REO2FW ring 819 820 <enum 7 reo_destination_sw5> Reo will push the frame 821 into the REO2SW5 ring 822 823 <enum 8 reo_destination_sw6> Reo will push the frame 824 into the REO2SW6 ring 825 826 <enum 9 reo_destination_9> REO remaps this <enum 10 827 reo_destination_10> REO remaps this 828 829 <enum 11 reo_destination_11> REO remaps this 830 831 <enum 12 reo_destination_12> REO remaps this <enum 13 832 reo_destination_13> REO remaps this 833 834 <enum 14 reo_destination_14> REO remaps this 835 836 <enum 15 reo_destination_15> REO remaps this 837 838 <enum 16 reo_destination_16> REO remaps this 839 840 <enum 17 reo_destination_17> REO remaps this 841 842 <enum 18 reo_destination_18> REO remaps this 843 844 <enum 19 reo_destination_19> REO remaps this 845 846 <enum 20 reo_destination_20> REO remaps this 847 848 <enum 21 reo_destination_21> REO remaps this 849 850 <enum 22 reo_destination_22> REO remaps this 851 852 <enum 23 reo_destination_23> REO remaps this 853 854 <enum 24 reo_destination_24> REO remaps this 855 856 <enum 25 reo_destination_25> REO remaps this 857 858 <enum 26 reo_destination_26> REO remaps this 859 860 <enum 27 reo_destination_27> REO remaps this 861 862 <enum 28 reo_destination_28> REO remaps this 863 864 <enum 29 reo_destination_29> REO remaps this 865 866 <enum 30 reo_destination_30> REO remaps this 867 868 <enum 31 reo_destination_31> REO remaps this 869 870 871 872 <legal all> 873 */ 874 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028 875 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 876 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 877 878 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 879 880 Parsed from RX_MSDU_END TLV . In the case MSDU spans 881 over multiple buffers, this field will be valid in the Last 882 buffer used by the MSDU 883 884 885 886 When set, REO shall drop this MSDU and not forward it to 887 any other ring... 888 889 <legal all> 890 */ 891 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 892 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 893 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 894 895 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 896 897 Parsed from RX_MSDU_END TLV . In the case MSDU spans 898 over multiple buffers, this field will be valid in the Last 899 buffer used by the MSDU 900 901 902 903 Indicates that OLE found a valid SA entry for this MSDU 904 905 <legal all> 906 */ 907 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 908 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 909 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 910 911 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 912 913 Parsed from RX_MSDU_END TLV . In the case MSDU spans 914 over multiple buffers, this field will be valid in the Last 915 buffer used by the MSDU 916 917 918 919 Indicates an unsuccessful MAC source address search due 920 to the expiring of the search timer for this MSDU 921 922 <legal all> 923 */ 924 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028 925 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 926 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 927 928 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 929 930 Parsed from RX_MSDU_END TLV . In the case MSDU spans 931 over multiple buffers, this field will be valid in the Last 932 buffer used by the MSDU 933 934 935 936 Indicates that OLE found a valid DA entry for this MSDU 937 938 <legal all> 939 */ 940 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 941 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 942 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 943 944 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 945 946 Field Only valid if da_is_valid is set 947 948 949 950 Indicates the DA address was a Multicast of Broadcast 951 address for this MSDU 952 953 <legal all> 954 */ 955 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 956 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 957 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 958 959 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 960 961 Parsed from RX_MSDU_END TLV . In the case MSDU spans 962 over multiple buffers, this field will be valid in the Last 963 buffer used by the MSDU 964 965 966 967 Indicates an unsuccessful MAC destination address search 968 due to the expiring of the search timer for this MSDU 969 970 <legal all> 971 */ 972 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028 973 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 974 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 975 976 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 977 978 <legal 0> 979 */ 980 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000028 981 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 982 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 983 984 /* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 985 986 <legal 0> 987 */ 988 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000002c 989 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 990 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 991 992 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_1 */ 993 994 995 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 996 997 998 /* Description RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 999 1000 Address (lower 32 bits) of the MSDU buffer OR 1001 MSDU_EXTENSION descriptor OR Link Descriptor 1002 1003 1004 1005 In case of 'NULL' pointer, this field is set to 0 1006 1007 <legal all> 1008 */ 1009 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 1010 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1011 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1012 1013 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1014 1015 Address (upper 8 bits) of the MSDU buffer OR 1016 MSDU_EXTENSION descriptor OR Link Descriptor 1017 1018 1019 1020 In case of 'NULL' pointer, this field is set to 0 1021 1022 <legal all> 1023 */ 1024 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 1025 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1026 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1027 1028 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1029 1030 Consumer: WBM 1031 1032 Producer: SW/FW 1033 1034 1035 1036 In case of 'NULL' pointer, this field is set to 0 1037 1038 1039 1040 Indicates to which buffer manager the buffer OR 1041 MSDU_EXTENSION descriptor OR link descriptor that is being 1042 pointed to shall be returned after the frame has been 1043 processed. It is used by WBM for routing purposes. 1044 1045 1046 1047 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1048 to the WMB buffer idle list 1049 1050 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1051 returned to the WMB idle link descriptor idle list 1052 1053 <enum 2 FW_BM> This buffer shall be returned to the FW 1054 1055 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1056 ring 0 1057 1058 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1059 ring 1 1060 1061 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1062 ring 2 1063 1064 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1065 ring 3 1066 1067 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1068 ring 4 1069 1070 1071 1072 <legal all> 1073 */ 1074 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1075 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1076 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 1077 1078 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 1079 1080 Cookie field exclusively used by SW. 1081 1082 1083 1084 In case of 'NULL' pointer, this field is set to 0 1085 1086 1087 1088 HW ignores the contents, accept that it passes the 1089 programmed value on to other descriptors together with the 1090 physical address 1091 1092 1093 1094 Field can be used by SW to for example associate the 1095 buffers physical address with the virtual address 1096 1097 The bit definitions as used by SW are within SW HLD 1098 specification 1099 1100 1101 1102 NOTE: 1103 1104 The three most significant bits can have a special 1105 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1106 STRUCT, and field transmit_bw_restriction is set 1107 1108 1109 1110 In case of NON punctured transmission: 1111 1112 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1113 1114 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1115 1116 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1117 1118 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1119 1120 1121 1122 In case of punctured transmission: 1123 1124 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1125 1126 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1127 1128 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1129 1130 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1131 1132 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1133 1134 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1135 1136 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1137 1138 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1139 1140 1141 1142 Note: a punctured transmission is indicated by the 1143 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1144 TLV 1145 1146 1147 1148 <legal all> 1149 */ 1150 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 1151 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 1152 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 1153 1154 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 1155 1156 1157 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 1158 1159 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1160 over multiple buffers, this field will be valid in the Last 1161 buffer used by the MSDU 1162 1163 1164 1165 <enum 0 Not_first_msdu> This is not the first MSDU in 1166 the MPDU. 1167 1168 <enum 1 first_msdu> This MSDU is the first one in the 1169 MPDU. 1170 1171 1172 1173 <legal all> 1174 */ 1175 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1176 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1177 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1178 1179 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 1180 1181 Consumer: WBM/REO/SW/FW 1182 1183 Producer: RXDMA 1184 1185 1186 1187 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1188 over multiple buffers, this field will be valid in the Last 1189 buffer used by the MSDU 1190 1191 1192 1193 <enum 0 Not_last_msdu> There are more MSDUs linked to 1194 this MSDU that belongs to this MPDU 1195 1196 <enum 1 Last_msdu> this MSDU is the last one in the 1197 MPDU. This setting is only allowed in combination with 1198 'Msdu_continuation' set to 0. This implies that when an msdu 1199 is spread out over multiple buffers and thus 1200 msdu_continuation is set, only for the very last buffer of 1201 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 1202 1203 1204 1205 When both first_msdu_in_mpdu_flag and 1206 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 1207 belongs to only contains a single MSDU. 1208 1209 1210 1211 1212 1213 <legal all> 1214 */ 1215 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1216 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1217 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1218 1219 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 1220 1221 When set, this MSDU buffer was not able to hold the 1222 entire MSDU. The next buffer will therefor contain 1223 additional information related to this MSDU. 1224 1225 1226 1227 <legal all> 1228 */ 1229 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 1230 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1231 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1232 1233 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 1234 1235 Parsed from RX_MSDU_START TLV . In the case MSDU spans 1236 over multiple buffers, this field will be valid in the First 1237 buffer used by MSDU. 1238 1239 1240 1241 Full MSDU length in bytes after decapsulation. 1242 1243 1244 1245 This field is still valid for MPDU frames without 1246 A-MSDU. It still represents MSDU length after decapsulation 1247 1248 1249 1250 Or in case of RAW MPDUs, it indicates the length of the 1251 entire MPDU (without FCS field) 1252 1253 <legal all> 1254 */ 1255 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 1256 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1257 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1258 1259 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 1260 1261 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1262 over multiple buffers, this field will be valid in the Last 1263 buffer used by the MSDU 1264 1265 1266 1267 The ID of the REO exit ring where the MSDU frame shall 1268 push after (MPDU level) reordering has finished. 1269 1270 1271 1272 <enum 0 reo_destination_tcl> Reo will push the frame 1273 into the REO2TCL ring 1274 1275 <enum 1 reo_destination_sw1> Reo will push the frame 1276 into the REO2SW1 ring 1277 1278 <enum 2 reo_destination_sw2> Reo will push the frame 1279 into the REO2SW2 ring 1280 1281 <enum 3 reo_destination_sw3> Reo will push the frame 1282 into the REO2SW3 ring 1283 1284 <enum 4 reo_destination_sw4> Reo will push the frame 1285 into the REO2SW4 ring 1286 1287 <enum 5 reo_destination_release> Reo will push the frame 1288 into the REO_release ring 1289 1290 <enum 6 reo_destination_fw> Reo will push the frame into 1291 the REO2FW ring 1292 1293 <enum 7 reo_destination_sw5> Reo will push the frame 1294 into the REO2SW5 ring 1295 1296 <enum 8 reo_destination_sw6> Reo will push the frame 1297 into the REO2SW6 ring 1298 1299 <enum 9 reo_destination_9> REO remaps this <enum 10 1300 reo_destination_10> REO remaps this 1301 1302 <enum 11 reo_destination_11> REO remaps this 1303 1304 <enum 12 reo_destination_12> REO remaps this <enum 13 1305 reo_destination_13> REO remaps this 1306 1307 <enum 14 reo_destination_14> REO remaps this 1308 1309 <enum 15 reo_destination_15> REO remaps this 1310 1311 <enum 16 reo_destination_16> REO remaps this 1312 1313 <enum 17 reo_destination_17> REO remaps this 1314 1315 <enum 18 reo_destination_18> REO remaps this 1316 1317 <enum 19 reo_destination_19> REO remaps this 1318 1319 <enum 20 reo_destination_20> REO remaps this 1320 1321 <enum 21 reo_destination_21> REO remaps this 1322 1323 <enum 22 reo_destination_22> REO remaps this 1324 1325 <enum 23 reo_destination_23> REO remaps this 1326 1327 <enum 24 reo_destination_24> REO remaps this 1328 1329 <enum 25 reo_destination_25> REO remaps this 1330 1331 <enum 26 reo_destination_26> REO remaps this 1332 1333 <enum 27 reo_destination_27> REO remaps this 1334 1335 <enum 28 reo_destination_28> REO remaps this 1336 1337 <enum 29 reo_destination_29> REO remaps this 1338 1339 <enum 30 reo_destination_30> REO remaps this 1340 1341 <enum 31 reo_destination_31> REO remaps this 1342 1343 1344 1345 <legal all> 1346 */ 1347 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038 1348 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1349 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1350 1351 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1352 1353 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1354 over multiple buffers, this field will be valid in the Last 1355 buffer used by the MSDU 1356 1357 1358 1359 When set, REO shall drop this MSDU and not forward it to 1360 any other ring... 1361 1362 <legal all> 1363 */ 1364 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 1365 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1366 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1367 1368 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1369 1370 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1371 over multiple buffers, this field will be valid in the Last 1372 buffer used by the MSDU 1373 1374 1375 1376 Indicates that OLE found a valid SA entry for this MSDU 1377 1378 <legal all> 1379 */ 1380 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 1381 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1382 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1383 1384 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1385 1386 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1387 over multiple buffers, this field will be valid in the Last 1388 buffer used by the MSDU 1389 1390 1391 1392 Indicates an unsuccessful MAC source address search due 1393 to the expiring of the search timer for this MSDU 1394 1395 <legal all> 1396 */ 1397 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038 1398 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1399 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1400 1401 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1402 1403 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1404 over multiple buffers, this field will be valid in the Last 1405 buffer used by the MSDU 1406 1407 1408 1409 Indicates that OLE found a valid DA entry for this MSDU 1410 1411 <legal all> 1412 */ 1413 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 1414 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1415 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1416 1417 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1418 1419 Field Only valid if da_is_valid is set 1420 1421 1422 1423 Indicates the DA address was a Multicast of Broadcast 1424 address for this MSDU 1425 1426 <legal all> 1427 */ 1428 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 1429 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1430 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1431 1432 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1433 1434 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1435 over multiple buffers, this field will be valid in the Last 1436 buffer used by the MSDU 1437 1438 1439 1440 Indicates an unsuccessful MAC destination address search 1441 due to the expiring of the search timer for this MSDU 1442 1443 <legal all> 1444 */ 1445 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038 1446 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1447 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1448 1449 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1450 1451 <legal 0> 1452 */ 1453 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000038 1454 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1455 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1456 1457 /* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1458 1459 <legal 0> 1460 */ 1461 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000003c 1462 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1463 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1464 1465 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_2 */ 1466 1467 1468 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 1469 1470 1471 /* Description RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1472 1473 Address (lower 32 bits) of the MSDU buffer OR 1474 MSDU_EXTENSION descriptor OR Link Descriptor 1475 1476 1477 1478 In case of 'NULL' pointer, this field is set to 0 1479 1480 <legal all> 1481 */ 1482 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 1483 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1484 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1485 1486 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1487 1488 Address (upper 8 bits) of the MSDU buffer OR 1489 MSDU_EXTENSION descriptor OR Link Descriptor 1490 1491 1492 1493 In case of 'NULL' pointer, this field is set to 0 1494 1495 <legal all> 1496 */ 1497 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 1498 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1499 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1500 1501 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1502 1503 Consumer: WBM 1504 1505 Producer: SW/FW 1506 1507 1508 1509 In case of 'NULL' pointer, this field is set to 0 1510 1511 1512 1513 Indicates to which buffer manager the buffer OR 1514 MSDU_EXTENSION descriptor OR link descriptor that is being 1515 pointed to shall be returned after the frame has been 1516 processed. It is used by WBM for routing purposes. 1517 1518 1519 1520 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1521 to the WMB buffer idle list 1522 1523 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1524 returned to the WMB idle link descriptor idle list 1525 1526 <enum 2 FW_BM> This buffer shall be returned to the FW 1527 1528 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1529 ring 0 1530 1531 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1532 ring 1 1533 1534 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1535 ring 2 1536 1537 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1538 ring 3 1539 1540 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1541 ring 4 1542 1543 1544 1545 <legal all> 1546 */ 1547 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1548 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1549 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 1550 1551 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 1552 1553 Cookie field exclusively used by SW. 1554 1555 1556 1557 In case of 'NULL' pointer, this field is set to 0 1558 1559 1560 1561 HW ignores the contents, accept that it passes the 1562 programmed value on to other descriptors together with the 1563 physical address 1564 1565 1566 1567 Field can be used by SW to for example associate the 1568 buffers physical address with the virtual address 1569 1570 The bit definitions as used by SW are within SW HLD 1571 specification 1572 1573 1574 1575 NOTE: 1576 1577 The three most significant bits can have a special 1578 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1579 STRUCT, and field transmit_bw_restriction is set 1580 1581 1582 1583 In case of NON punctured transmission: 1584 1585 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1586 1587 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1588 1589 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1590 1591 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1592 1593 1594 1595 In case of punctured transmission: 1596 1597 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1598 1599 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1600 1601 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1602 1603 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1604 1605 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1606 1607 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1608 1609 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1610 1611 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1612 1613 1614 1615 Note: a punctured transmission is indicated by the 1616 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1617 TLV 1618 1619 1620 1621 <legal all> 1622 */ 1623 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 1624 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 1625 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 1626 1627 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 1628 1629 1630 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 1631 1632 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1633 over multiple buffers, this field will be valid in the Last 1634 buffer used by the MSDU 1635 1636 1637 1638 <enum 0 Not_first_msdu> This is not the first MSDU in 1639 the MPDU. 1640 1641 <enum 1 first_msdu> This MSDU is the first one in the 1642 MPDU. 1643 1644 1645 1646 <legal all> 1647 */ 1648 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1649 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1650 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1651 1652 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 1653 1654 Consumer: WBM/REO/SW/FW 1655 1656 Producer: RXDMA 1657 1658 1659 1660 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1661 over multiple buffers, this field will be valid in the Last 1662 buffer used by the MSDU 1663 1664 1665 1666 <enum 0 Not_last_msdu> There are more MSDUs linked to 1667 this MSDU that belongs to this MPDU 1668 1669 <enum 1 Last_msdu> this MSDU is the last one in the 1670 MPDU. This setting is only allowed in combination with 1671 'Msdu_continuation' set to 0. This implies that when an msdu 1672 is spread out over multiple buffers and thus 1673 msdu_continuation is set, only for the very last buffer of 1674 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 1675 1676 1677 1678 When both first_msdu_in_mpdu_flag and 1679 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 1680 belongs to only contains a single MSDU. 1681 1682 1683 1684 1685 1686 <legal all> 1687 */ 1688 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1689 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1690 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1691 1692 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 1693 1694 When set, this MSDU buffer was not able to hold the 1695 entire MSDU. The next buffer will therefor contain 1696 additional information related to this MSDU. 1697 1698 1699 1700 <legal all> 1701 */ 1702 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 1703 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1704 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1705 1706 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 1707 1708 Parsed from RX_MSDU_START TLV . In the case MSDU spans 1709 over multiple buffers, this field will be valid in the First 1710 buffer used by MSDU. 1711 1712 1713 1714 Full MSDU length in bytes after decapsulation. 1715 1716 1717 1718 This field is still valid for MPDU frames without 1719 A-MSDU. It still represents MSDU length after decapsulation 1720 1721 1722 1723 Or in case of RAW MPDUs, it indicates the length of the 1724 entire MPDU (without FCS field) 1725 1726 <legal all> 1727 */ 1728 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 1729 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1730 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1731 1732 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 1733 1734 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1735 over multiple buffers, this field will be valid in the Last 1736 buffer used by the MSDU 1737 1738 1739 1740 The ID of the REO exit ring where the MSDU frame shall 1741 push after (MPDU level) reordering has finished. 1742 1743 1744 1745 <enum 0 reo_destination_tcl> Reo will push the frame 1746 into the REO2TCL ring 1747 1748 <enum 1 reo_destination_sw1> Reo will push the frame 1749 into the REO2SW1 ring 1750 1751 <enum 2 reo_destination_sw2> Reo will push the frame 1752 into the REO2SW2 ring 1753 1754 <enum 3 reo_destination_sw3> Reo will push the frame 1755 into the REO2SW3 ring 1756 1757 <enum 4 reo_destination_sw4> Reo will push the frame 1758 into the REO2SW4 ring 1759 1760 <enum 5 reo_destination_release> Reo will push the frame 1761 into the REO_release ring 1762 1763 <enum 6 reo_destination_fw> Reo will push the frame into 1764 the REO2FW ring 1765 1766 <enum 7 reo_destination_sw5> Reo will push the frame 1767 into the REO2SW5 ring 1768 1769 <enum 8 reo_destination_sw6> Reo will push the frame 1770 into the REO2SW6 ring 1771 1772 <enum 9 reo_destination_9> REO remaps this <enum 10 1773 reo_destination_10> REO remaps this 1774 1775 <enum 11 reo_destination_11> REO remaps this 1776 1777 <enum 12 reo_destination_12> REO remaps this <enum 13 1778 reo_destination_13> REO remaps this 1779 1780 <enum 14 reo_destination_14> REO remaps this 1781 1782 <enum 15 reo_destination_15> REO remaps this 1783 1784 <enum 16 reo_destination_16> REO remaps this 1785 1786 <enum 17 reo_destination_17> REO remaps this 1787 1788 <enum 18 reo_destination_18> REO remaps this 1789 1790 <enum 19 reo_destination_19> REO remaps this 1791 1792 <enum 20 reo_destination_20> REO remaps this 1793 1794 <enum 21 reo_destination_21> REO remaps this 1795 1796 <enum 22 reo_destination_22> REO remaps this 1797 1798 <enum 23 reo_destination_23> REO remaps this 1799 1800 <enum 24 reo_destination_24> REO remaps this 1801 1802 <enum 25 reo_destination_25> REO remaps this 1803 1804 <enum 26 reo_destination_26> REO remaps this 1805 1806 <enum 27 reo_destination_27> REO remaps this 1807 1808 <enum 28 reo_destination_28> REO remaps this 1809 1810 <enum 29 reo_destination_29> REO remaps this 1811 1812 <enum 30 reo_destination_30> REO remaps this 1813 1814 <enum 31 reo_destination_31> REO remaps this 1815 1816 1817 1818 <legal all> 1819 */ 1820 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048 1821 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1822 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1823 1824 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1825 1826 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1827 over multiple buffers, this field will be valid in the Last 1828 buffer used by the MSDU 1829 1830 1831 1832 When set, REO shall drop this MSDU and not forward it to 1833 any other ring... 1834 1835 <legal all> 1836 */ 1837 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 1838 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1839 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1840 1841 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1842 1843 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1844 over multiple buffers, this field will be valid in the Last 1845 buffer used by the MSDU 1846 1847 1848 1849 Indicates that OLE found a valid SA entry for this MSDU 1850 1851 <legal all> 1852 */ 1853 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 1854 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1855 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1856 1857 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1858 1859 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1860 over multiple buffers, this field will be valid in the Last 1861 buffer used by the MSDU 1862 1863 1864 1865 Indicates an unsuccessful MAC source address search due 1866 to the expiring of the search timer for this MSDU 1867 1868 <legal all> 1869 */ 1870 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048 1871 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1872 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1873 1874 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1875 1876 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1877 over multiple buffers, this field will be valid in the Last 1878 buffer used by the MSDU 1879 1880 1881 1882 Indicates that OLE found a valid DA entry for this MSDU 1883 1884 <legal all> 1885 */ 1886 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 1887 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1888 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1889 1890 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1891 1892 Field Only valid if da_is_valid is set 1893 1894 1895 1896 Indicates the DA address was a Multicast of Broadcast 1897 address for this MSDU 1898 1899 <legal all> 1900 */ 1901 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 1902 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1903 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1904 1905 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1906 1907 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1908 over multiple buffers, this field will be valid in the Last 1909 buffer used by the MSDU 1910 1911 1912 1913 Indicates an unsuccessful MAC destination address search 1914 due to the expiring of the search timer for this MSDU 1915 1916 <legal all> 1917 */ 1918 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048 1919 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1920 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1921 1922 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1923 1924 <legal 0> 1925 */ 1926 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000048 1927 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1928 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1929 1930 /* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1931 1932 <legal 0> 1933 */ 1934 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000004c 1935 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1936 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1937 1938 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_3 */ 1939 1940 1941 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 1942 1943 1944 /* Description RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1945 1946 Address (lower 32 bits) of the MSDU buffer OR 1947 MSDU_EXTENSION descriptor OR Link Descriptor 1948 1949 1950 1951 In case of 'NULL' pointer, this field is set to 0 1952 1953 <legal all> 1954 */ 1955 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 1956 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1957 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1958 1959 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1960 1961 Address (upper 8 bits) of the MSDU buffer OR 1962 MSDU_EXTENSION descriptor OR Link Descriptor 1963 1964 1965 1966 In case of 'NULL' pointer, this field is set to 0 1967 1968 <legal all> 1969 */ 1970 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 1971 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1972 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1973 1974 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1975 1976 Consumer: WBM 1977 1978 Producer: SW/FW 1979 1980 1981 1982 In case of 'NULL' pointer, this field is set to 0 1983 1984 1985 1986 Indicates to which buffer manager the buffer OR 1987 MSDU_EXTENSION descriptor OR link descriptor that is being 1988 pointed to shall be returned after the frame has been 1989 processed. It is used by WBM for routing purposes. 1990 1991 1992 1993 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1994 to the WMB buffer idle list 1995 1996 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1997 returned to the WMB idle link descriptor idle list 1998 1999 <enum 2 FW_BM> This buffer shall be returned to the FW 2000 2001 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2002 ring 0 2003 2004 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2005 ring 1 2006 2007 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2008 ring 2 2009 2010 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2011 ring 3 2012 2013 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2014 ring 4 2015 2016 2017 2018 <legal all> 2019 */ 2020 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 2021 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2022 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2023 2024 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2025 2026 Cookie field exclusively used by SW. 2027 2028 2029 2030 In case of 'NULL' pointer, this field is set to 0 2031 2032 2033 2034 HW ignores the contents, accept that it passes the 2035 programmed value on to other descriptors together with the 2036 physical address 2037 2038 2039 2040 Field can be used by SW to for example associate the 2041 buffers physical address with the virtual address 2042 2043 The bit definitions as used by SW are within SW HLD 2044 specification 2045 2046 2047 2048 NOTE: 2049 2050 The three most significant bits can have a special 2051 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2052 STRUCT, and field transmit_bw_restriction is set 2053 2054 2055 2056 In case of NON punctured transmission: 2057 2058 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2059 2060 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2061 2062 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2063 2064 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2065 2066 2067 2068 In case of punctured transmission: 2069 2070 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2071 2072 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2073 2074 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2075 2076 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2077 2078 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2079 2080 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2081 2082 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2083 2084 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2085 2086 2087 2088 Note: a punctured transmission is indicated by the 2089 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2090 TLV 2091 2092 2093 2094 <legal all> 2095 */ 2096 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 2097 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 2098 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 2099 2100 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 2101 2102 2103 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 2104 2105 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2106 over multiple buffers, this field will be valid in the Last 2107 buffer used by the MSDU 2108 2109 2110 2111 <enum 0 Not_first_msdu> This is not the first MSDU in 2112 the MPDU. 2113 2114 <enum 1 first_msdu> This MSDU is the first one in the 2115 MPDU. 2116 2117 2118 2119 <legal all> 2120 */ 2121 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2122 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2123 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2124 2125 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 2126 2127 Consumer: WBM/REO/SW/FW 2128 2129 Producer: RXDMA 2130 2131 2132 2133 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2134 over multiple buffers, this field will be valid in the Last 2135 buffer used by the MSDU 2136 2137 2138 2139 <enum 0 Not_last_msdu> There are more MSDUs linked to 2140 this MSDU that belongs to this MPDU 2141 2142 <enum 1 Last_msdu> this MSDU is the last one in the 2143 MPDU. This setting is only allowed in combination with 2144 'Msdu_continuation' set to 0. This implies that when an msdu 2145 is spread out over multiple buffers and thus 2146 msdu_continuation is set, only for the very last buffer of 2147 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 2148 2149 2150 2151 When both first_msdu_in_mpdu_flag and 2152 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 2153 belongs to only contains a single MSDU. 2154 2155 2156 2157 2158 2159 <legal all> 2160 */ 2161 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2162 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2163 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2164 2165 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 2166 2167 When set, this MSDU buffer was not able to hold the 2168 entire MSDU. The next buffer will therefor contain 2169 additional information related to this MSDU. 2170 2171 2172 2173 <legal all> 2174 */ 2175 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 2176 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2177 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2178 2179 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 2180 2181 Parsed from RX_MSDU_START TLV . In the case MSDU spans 2182 over multiple buffers, this field will be valid in the First 2183 buffer used by MSDU. 2184 2185 2186 2187 Full MSDU length in bytes after decapsulation. 2188 2189 2190 2191 This field is still valid for MPDU frames without 2192 A-MSDU. It still represents MSDU length after decapsulation 2193 2194 2195 2196 Or in case of RAW MPDUs, it indicates the length of the 2197 entire MPDU (without FCS field) 2198 2199 <legal all> 2200 */ 2201 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 2202 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2203 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2204 2205 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 2206 2207 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2208 over multiple buffers, this field will be valid in the Last 2209 buffer used by the MSDU 2210 2211 2212 2213 The ID of the REO exit ring where the MSDU frame shall 2214 push after (MPDU level) reordering has finished. 2215 2216 2217 2218 <enum 0 reo_destination_tcl> Reo will push the frame 2219 into the REO2TCL ring 2220 2221 <enum 1 reo_destination_sw1> Reo will push the frame 2222 into the REO2SW1 ring 2223 2224 <enum 2 reo_destination_sw2> Reo will push the frame 2225 into the REO2SW2 ring 2226 2227 <enum 3 reo_destination_sw3> Reo will push the frame 2228 into the REO2SW3 ring 2229 2230 <enum 4 reo_destination_sw4> Reo will push the frame 2231 into the REO2SW4 ring 2232 2233 <enum 5 reo_destination_release> Reo will push the frame 2234 into the REO_release ring 2235 2236 <enum 6 reo_destination_fw> Reo will push the frame into 2237 the REO2FW ring 2238 2239 <enum 7 reo_destination_sw5> Reo will push the frame 2240 into the REO2SW5 ring 2241 2242 <enum 8 reo_destination_sw6> Reo will push the frame 2243 into the REO2SW6 ring 2244 2245 <enum 9 reo_destination_9> REO remaps this <enum 10 2246 reo_destination_10> REO remaps this 2247 2248 <enum 11 reo_destination_11> REO remaps this 2249 2250 <enum 12 reo_destination_12> REO remaps this <enum 13 2251 reo_destination_13> REO remaps this 2252 2253 <enum 14 reo_destination_14> REO remaps this 2254 2255 <enum 15 reo_destination_15> REO remaps this 2256 2257 <enum 16 reo_destination_16> REO remaps this 2258 2259 <enum 17 reo_destination_17> REO remaps this 2260 2261 <enum 18 reo_destination_18> REO remaps this 2262 2263 <enum 19 reo_destination_19> REO remaps this 2264 2265 <enum 20 reo_destination_20> REO remaps this 2266 2267 <enum 21 reo_destination_21> REO remaps this 2268 2269 <enum 22 reo_destination_22> REO remaps this 2270 2271 <enum 23 reo_destination_23> REO remaps this 2272 2273 <enum 24 reo_destination_24> REO remaps this 2274 2275 <enum 25 reo_destination_25> REO remaps this 2276 2277 <enum 26 reo_destination_26> REO remaps this 2278 2279 <enum 27 reo_destination_27> REO remaps this 2280 2281 <enum 28 reo_destination_28> REO remaps this 2282 2283 <enum 29 reo_destination_29> REO remaps this 2284 2285 <enum 30 reo_destination_30> REO remaps this 2286 2287 <enum 31 reo_destination_31> REO remaps this 2288 2289 2290 2291 <legal all> 2292 */ 2293 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058 2294 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 2295 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 2296 2297 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 2298 2299 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2300 over multiple buffers, this field will be valid in the Last 2301 buffer used by the MSDU 2302 2303 2304 2305 When set, REO shall drop this MSDU and not forward it to 2306 any other ring... 2307 2308 <legal all> 2309 */ 2310 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 2311 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 2312 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 2313 2314 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 2315 2316 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2317 over multiple buffers, this field will be valid in the Last 2318 buffer used by the MSDU 2319 2320 2321 2322 Indicates that OLE found a valid SA entry for this MSDU 2323 2324 <legal all> 2325 */ 2326 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 2327 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 2328 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 2329 2330 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 2331 2332 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2333 over multiple buffers, this field will be valid in the Last 2334 buffer used by the MSDU 2335 2336 2337 2338 Indicates an unsuccessful MAC source address search due 2339 to the expiring of the search timer for this MSDU 2340 2341 <legal all> 2342 */ 2343 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058 2344 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 2345 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 2346 2347 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 2348 2349 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2350 over multiple buffers, this field will be valid in the Last 2351 buffer used by the MSDU 2352 2353 2354 2355 Indicates that OLE found a valid DA entry for this MSDU 2356 2357 <legal all> 2358 */ 2359 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 2360 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 2361 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 2362 2363 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 2364 2365 Field Only valid if da_is_valid is set 2366 2367 2368 2369 Indicates the DA address was a Multicast of Broadcast 2370 address for this MSDU 2371 2372 <legal all> 2373 */ 2374 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 2375 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 2376 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 2377 2378 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 2379 2380 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2381 over multiple buffers, this field will be valid in the Last 2382 buffer used by the MSDU 2383 2384 2385 2386 Indicates an unsuccessful MAC destination address search 2387 due to the expiring of the search timer for this MSDU 2388 2389 <legal all> 2390 */ 2391 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058 2392 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 2393 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 2394 2395 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 2396 2397 <legal 0> 2398 */ 2399 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000058 2400 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 2401 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 2402 2403 /* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 2404 2405 <legal 0> 2406 */ 2407 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000005c 2408 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 2409 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 2410 2411 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_4 */ 2412 2413 2414 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 2415 2416 2417 /* Description RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 2418 2419 Address (lower 32 bits) of the MSDU buffer OR 2420 MSDU_EXTENSION descriptor OR Link Descriptor 2421 2422 2423 2424 In case of 'NULL' pointer, this field is set to 0 2425 2426 <legal all> 2427 */ 2428 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 2429 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2430 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2431 2432 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 2433 2434 Address (upper 8 bits) of the MSDU buffer OR 2435 MSDU_EXTENSION descriptor OR Link Descriptor 2436 2437 2438 2439 In case of 'NULL' pointer, this field is set to 0 2440 2441 <legal all> 2442 */ 2443 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 2444 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2445 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2446 2447 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 2448 2449 Consumer: WBM 2450 2451 Producer: SW/FW 2452 2453 2454 2455 In case of 'NULL' pointer, this field is set to 0 2456 2457 2458 2459 Indicates to which buffer manager the buffer OR 2460 MSDU_EXTENSION descriptor OR link descriptor that is being 2461 pointed to shall be returned after the frame has been 2462 processed. It is used by WBM for routing purposes. 2463 2464 2465 2466 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2467 to the WMB buffer idle list 2468 2469 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2470 returned to the WMB idle link descriptor idle list 2471 2472 <enum 2 FW_BM> This buffer shall be returned to the FW 2473 2474 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2475 ring 0 2476 2477 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2478 ring 1 2479 2480 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2481 ring 2 2482 2483 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2484 ring 3 2485 2486 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2487 ring 4 2488 2489 2490 2491 <legal all> 2492 */ 2493 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2494 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2495 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2496 2497 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2498 2499 Cookie field exclusively used by SW. 2500 2501 2502 2503 In case of 'NULL' pointer, this field is set to 0 2504 2505 2506 2507 HW ignores the contents, accept that it passes the 2508 programmed value on to other descriptors together with the 2509 physical address 2510 2511 2512 2513 Field can be used by SW to for example associate the 2514 buffers physical address with the virtual address 2515 2516 The bit definitions as used by SW are within SW HLD 2517 specification 2518 2519 2520 2521 NOTE: 2522 2523 The three most significant bits can have a special 2524 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2525 STRUCT, and field transmit_bw_restriction is set 2526 2527 2528 2529 In case of NON punctured transmission: 2530 2531 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2532 2533 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2534 2535 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2536 2537 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2538 2539 2540 2541 In case of punctured transmission: 2542 2543 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2544 2545 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2546 2547 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2548 2549 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2550 2551 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2552 2553 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2554 2555 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2556 2557 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2558 2559 2560 2561 Note: a punctured transmission is indicated by the 2562 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2563 TLV 2564 2565 2566 2567 <legal all> 2568 */ 2569 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 2570 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 2571 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 2572 2573 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 2574 2575 2576 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 2577 2578 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2579 over multiple buffers, this field will be valid in the Last 2580 buffer used by the MSDU 2581 2582 2583 2584 <enum 0 Not_first_msdu> This is not the first MSDU in 2585 the MPDU. 2586 2587 <enum 1 first_msdu> This MSDU is the first one in the 2588 MPDU. 2589 2590 2591 2592 <legal all> 2593 */ 2594 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 2595 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2596 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2597 2598 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 2599 2600 Consumer: WBM/REO/SW/FW 2601 2602 Producer: RXDMA 2603 2604 2605 2606 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2607 over multiple buffers, this field will be valid in the Last 2608 buffer used by the MSDU 2609 2610 2611 2612 <enum 0 Not_last_msdu> There are more MSDUs linked to 2613 this MSDU that belongs to this MPDU 2614 2615 <enum 1 Last_msdu> this MSDU is the last one in the 2616 MPDU. This setting is only allowed in combination with 2617 'Msdu_continuation' set to 0. This implies that when an msdu 2618 is spread out over multiple buffers and thus 2619 msdu_continuation is set, only for the very last buffer of 2620 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 2621 2622 2623 2624 When both first_msdu_in_mpdu_flag and 2625 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 2626 belongs to only contains a single MSDU. 2627 2628 2629 2630 2631 2632 <legal all> 2633 */ 2634 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 2635 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2636 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2637 2638 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 2639 2640 When set, this MSDU buffer was not able to hold the 2641 entire MSDU. The next buffer will therefor contain 2642 additional information related to this MSDU. 2643 2644 2645 2646 <legal all> 2647 */ 2648 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 2649 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2650 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2651 2652 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 2653 2654 Parsed from RX_MSDU_START TLV . In the case MSDU spans 2655 over multiple buffers, this field will be valid in the First 2656 buffer used by MSDU. 2657 2658 2659 2660 Full MSDU length in bytes after decapsulation. 2661 2662 2663 2664 This field is still valid for MPDU frames without 2665 A-MSDU. It still represents MSDU length after decapsulation 2666 2667 2668 2669 Or in case of RAW MPDUs, it indicates the length of the 2670 entire MPDU (without FCS field) 2671 2672 <legal all> 2673 */ 2674 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 2675 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2676 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2677 2678 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 2679 2680 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2681 over multiple buffers, this field will be valid in the Last 2682 buffer used by the MSDU 2683 2684 2685 2686 The ID of the REO exit ring where the MSDU frame shall 2687 push after (MPDU level) reordering has finished. 2688 2689 2690 2691 <enum 0 reo_destination_tcl> Reo will push the frame 2692 into the REO2TCL ring 2693 2694 <enum 1 reo_destination_sw1> Reo will push the frame 2695 into the REO2SW1 ring 2696 2697 <enum 2 reo_destination_sw2> Reo will push the frame 2698 into the REO2SW2 ring 2699 2700 <enum 3 reo_destination_sw3> Reo will push the frame 2701 into the REO2SW3 ring 2702 2703 <enum 4 reo_destination_sw4> Reo will push the frame 2704 into the REO2SW4 ring 2705 2706 <enum 5 reo_destination_release> Reo will push the frame 2707 into the REO_release ring 2708 2709 <enum 6 reo_destination_fw> Reo will push the frame into 2710 the REO2FW ring 2711 2712 <enum 7 reo_destination_sw5> Reo will push the frame 2713 into the REO2SW5 ring 2714 2715 <enum 8 reo_destination_sw6> Reo will push the frame 2716 into the REO2SW6 ring 2717 2718 <enum 9 reo_destination_9> REO remaps this <enum 10 2719 reo_destination_10> REO remaps this 2720 2721 <enum 11 reo_destination_11> REO remaps this 2722 2723 <enum 12 reo_destination_12> REO remaps this <enum 13 2724 reo_destination_13> REO remaps this 2725 2726 <enum 14 reo_destination_14> REO remaps this 2727 2728 <enum 15 reo_destination_15> REO remaps this 2729 2730 <enum 16 reo_destination_16> REO remaps this 2731 2732 <enum 17 reo_destination_17> REO remaps this 2733 2734 <enum 18 reo_destination_18> REO remaps this 2735 2736 <enum 19 reo_destination_19> REO remaps this 2737 2738 <enum 20 reo_destination_20> REO remaps this 2739 2740 <enum 21 reo_destination_21> REO remaps this 2741 2742 <enum 22 reo_destination_22> REO remaps this 2743 2744 <enum 23 reo_destination_23> REO remaps this 2745 2746 <enum 24 reo_destination_24> REO remaps this 2747 2748 <enum 25 reo_destination_25> REO remaps this 2749 2750 <enum 26 reo_destination_26> REO remaps this 2751 2752 <enum 27 reo_destination_27> REO remaps this 2753 2754 <enum 28 reo_destination_28> REO remaps this 2755 2756 <enum 29 reo_destination_29> REO remaps this 2757 2758 <enum 30 reo_destination_30> REO remaps this 2759 2760 <enum 31 reo_destination_31> REO remaps this 2761 2762 2763 2764 <legal all> 2765 */ 2766 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068 2767 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 2768 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 2769 2770 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 2771 2772 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2773 over multiple buffers, this field will be valid in the Last 2774 buffer used by the MSDU 2775 2776 2777 2778 When set, REO shall drop this MSDU and not forward it to 2779 any other ring... 2780 2781 <legal all> 2782 */ 2783 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 2784 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 2785 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 2786 2787 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 2788 2789 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2790 over multiple buffers, this field will be valid in the Last 2791 buffer used by the MSDU 2792 2793 2794 2795 Indicates that OLE found a valid SA entry for this MSDU 2796 2797 <legal all> 2798 */ 2799 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 2800 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 2801 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 2802 2803 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 2804 2805 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2806 over multiple buffers, this field will be valid in the Last 2807 buffer used by the MSDU 2808 2809 2810 2811 Indicates an unsuccessful MAC source address search due 2812 to the expiring of the search timer for this MSDU 2813 2814 <legal all> 2815 */ 2816 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068 2817 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 2818 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 2819 2820 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 2821 2822 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2823 over multiple buffers, this field will be valid in the Last 2824 buffer used by the MSDU 2825 2826 2827 2828 Indicates that OLE found a valid DA entry for this MSDU 2829 2830 <legal all> 2831 */ 2832 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 2833 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 2834 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 2835 2836 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 2837 2838 Field Only valid if da_is_valid is set 2839 2840 2841 2842 Indicates the DA address was a Multicast of Broadcast 2843 address for this MSDU 2844 2845 <legal all> 2846 */ 2847 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 2848 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 2849 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 2850 2851 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 2852 2853 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2854 over multiple buffers, this field will be valid in the Last 2855 buffer used by the MSDU 2856 2857 2858 2859 Indicates an unsuccessful MAC destination address search 2860 due to the expiring of the search timer for this MSDU 2861 2862 <legal all> 2863 */ 2864 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068 2865 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 2866 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 2867 2868 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 2869 2870 <legal 0> 2871 */ 2872 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000068 2873 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 2874 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 2875 2876 /* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 2877 2878 <legal 0> 2879 */ 2880 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000006c 2881 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 2882 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 2883 2884 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_5 */ 2885 2886 2887 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 2888 2889 2890 /* Description RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 2891 2892 Address (lower 32 bits) of the MSDU buffer OR 2893 MSDU_EXTENSION descriptor OR Link Descriptor 2894 2895 2896 2897 In case of 'NULL' pointer, this field is set to 0 2898 2899 <legal all> 2900 */ 2901 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 2902 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2903 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2904 2905 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 2906 2907 Address (upper 8 bits) of the MSDU buffer OR 2908 MSDU_EXTENSION descriptor OR Link Descriptor 2909 2910 2911 2912 In case of 'NULL' pointer, this field is set to 0 2913 2914 <legal all> 2915 */ 2916 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 2917 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2918 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2919 2920 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 2921 2922 Consumer: WBM 2923 2924 Producer: SW/FW 2925 2926 2927 2928 In case of 'NULL' pointer, this field is set to 0 2929 2930 2931 2932 Indicates to which buffer manager the buffer OR 2933 MSDU_EXTENSION descriptor OR link descriptor that is being 2934 pointed to shall be returned after the frame has been 2935 processed. It is used by WBM for routing purposes. 2936 2937 2938 2939 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2940 to the WMB buffer idle list 2941 2942 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2943 returned to the WMB idle link descriptor idle list 2944 2945 <enum 2 FW_BM> This buffer shall be returned to the FW 2946 2947 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2948 ring 0 2949 2950 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2951 ring 1 2952 2953 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2954 ring 2 2955 2956 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2957 ring 3 2958 2959 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2960 ring 4 2961 2962 2963 2964 <legal all> 2965 */ 2966 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2967 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2968 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2969 2970 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2971 2972 Cookie field exclusively used by SW. 2973 2974 2975 2976 In case of 'NULL' pointer, this field is set to 0 2977 2978 2979 2980 HW ignores the contents, accept that it passes the 2981 programmed value on to other descriptors together with the 2982 physical address 2983 2984 2985 2986 Field can be used by SW to for example associate the 2987 buffers physical address with the virtual address 2988 2989 The bit definitions as used by SW are within SW HLD 2990 specification 2991 2992 2993 2994 NOTE: 2995 2996 The three most significant bits can have a special 2997 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2998 STRUCT, and field transmit_bw_restriction is set 2999 3000 3001 3002 In case of NON punctured transmission: 3003 3004 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 3005 3006 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 3007 3008 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 3009 3010 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 3011 3012 3013 3014 In case of punctured transmission: 3015 3016 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 3017 3018 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 3019 3020 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 3021 3022 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 3023 3024 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 3025 3026 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 3027 3028 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 3029 3030 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 3031 3032 3033 3034 Note: a punctured transmission is indicated by the 3035 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 3036 TLV 3037 3038 3039 3040 <legal all> 3041 */ 3042 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 3043 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 3044 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 3045 3046 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 3047 3048 3049 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 3050 3051 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3052 over multiple buffers, this field will be valid in the Last 3053 buffer used by the MSDU 3054 3055 3056 3057 <enum 0 Not_first_msdu> This is not the first MSDU in 3058 the MPDU. 3059 3060 <enum 1 first_msdu> This MSDU is the first one in the 3061 MPDU. 3062 3063 3064 3065 <legal all> 3066 */ 3067 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3068 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3069 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3070 3071 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 3072 3073 Consumer: WBM/REO/SW/FW 3074 3075 Producer: RXDMA 3076 3077 3078 3079 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3080 over multiple buffers, this field will be valid in the Last 3081 buffer used by the MSDU 3082 3083 3084 3085 <enum 0 Not_last_msdu> There are more MSDUs linked to 3086 this MSDU that belongs to this MPDU 3087 3088 <enum 1 Last_msdu> this MSDU is the last one in the 3089 MPDU. This setting is only allowed in combination with 3090 'Msdu_continuation' set to 0. This implies that when an msdu 3091 is spread out over multiple buffers and thus 3092 msdu_continuation is set, only for the very last buffer of 3093 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 3094 3095 3096 3097 When both first_msdu_in_mpdu_flag and 3098 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 3099 belongs to only contains a single MSDU. 3100 3101 3102 3103 3104 3105 <legal all> 3106 */ 3107 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3108 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3109 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3110 3111 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 3112 3113 When set, this MSDU buffer was not able to hold the 3114 entire MSDU. The next buffer will therefor contain 3115 additional information related to this MSDU. 3116 3117 3118 3119 <legal all> 3120 */ 3121 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 3122 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3123 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3124 3125 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 3126 3127 Parsed from RX_MSDU_START TLV . In the case MSDU spans 3128 over multiple buffers, this field will be valid in the First 3129 buffer used by MSDU. 3130 3131 3132 3133 Full MSDU length in bytes after decapsulation. 3134 3135 3136 3137 This field is still valid for MPDU frames without 3138 A-MSDU. It still represents MSDU length after decapsulation 3139 3140 3141 3142 Or in case of RAW MPDUs, it indicates the length of the 3143 entire MPDU (without FCS field) 3144 3145 <legal all> 3146 */ 3147 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 3148 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3149 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3150 3151 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 3152 3153 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3154 over multiple buffers, this field will be valid in the Last 3155 buffer used by the MSDU 3156 3157 3158 3159 The ID of the REO exit ring where the MSDU frame shall 3160 push after (MPDU level) reordering has finished. 3161 3162 3163 3164 <enum 0 reo_destination_tcl> Reo will push the frame 3165 into the REO2TCL ring 3166 3167 <enum 1 reo_destination_sw1> Reo will push the frame 3168 into the REO2SW1 ring 3169 3170 <enum 2 reo_destination_sw2> Reo will push the frame 3171 into the REO2SW2 ring 3172 3173 <enum 3 reo_destination_sw3> Reo will push the frame 3174 into the REO2SW3 ring 3175 3176 <enum 4 reo_destination_sw4> Reo will push the frame 3177 into the REO2SW4 ring 3178 3179 <enum 5 reo_destination_release> Reo will push the frame 3180 into the REO_release ring 3181 3182 <enum 6 reo_destination_fw> Reo will push the frame into 3183 the REO2FW ring 3184 3185 <enum 7 reo_destination_sw5> Reo will push the frame 3186 into the REO2SW5 ring 3187 3188 <enum 8 reo_destination_sw6> Reo will push the frame 3189 into the REO2SW6 ring 3190 3191 <enum 9 reo_destination_9> REO remaps this <enum 10 3192 reo_destination_10> REO remaps this 3193 3194 <enum 11 reo_destination_11> REO remaps this 3195 3196 <enum 12 reo_destination_12> REO remaps this <enum 13 3197 reo_destination_13> REO remaps this 3198 3199 <enum 14 reo_destination_14> REO remaps this 3200 3201 <enum 15 reo_destination_15> REO remaps this 3202 3203 <enum 16 reo_destination_16> REO remaps this 3204 3205 <enum 17 reo_destination_17> REO remaps this 3206 3207 <enum 18 reo_destination_18> REO remaps this 3208 3209 <enum 19 reo_destination_19> REO remaps this 3210 3211 <enum 20 reo_destination_20> REO remaps this 3212 3213 <enum 21 reo_destination_21> REO remaps this 3214 3215 <enum 22 reo_destination_22> REO remaps this 3216 3217 <enum 23 reo_destination_23> REO remaps this 3218 3219 <enum 24 reo_destination_24> REO remaps this 3220 3221 <enum 25 reo_destination_25> REO remaps this 3222 3223 <enum 26 reo_destination_26> REO remaps this 3224 3225 <enum 27 reo_destination_27> REO remaps this 3226 3227 <enum 28 reo_destination_28> REO remaps this 3228 3229 <enum 29 reo_destination_29> REO remaps this 3230 3231 <enum 30 reo_destination_30> REO remaps this 3232 3233 <enum 31 reo_destination_31> REO remaps this 3234 3235 3236 3237 <legal all> 3238 */ 3239 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078 3240 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 3241 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 3242 3243 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 3244 3245 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3246 over multiple buffers, this field will be valid in the Last 3247 buffer used by the MSDU 3248 3249 3250 3251 When set, REO shall drop this MSDU and not forward it to 3252 any other ring... 3253 3254 <legal all> 3255 */ 3256 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 3257 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 3258 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 3259 3260 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 3261 3262 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3263 over multiple buffers, this field will be valid in the Last 3264 buffer used by the MSDU 3265 3266 3267 3268 Indicates that OLE found a valid SA entry for this MSDU 3269 3270 <legal all> 3271 */ 3272 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 3273 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 3274 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 3275 3276 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 3277 3278 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3279 over multiple buffers, this field will be valid in the Last 3280 buffer used by the MSDU 3281 3282 3283 3284 Indicates an unsuccessful MAC source address search due 3285 to the expiring of the search timer for this MSDU 3286 3287 <legal all> 3288 */ 3289 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078 3290 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 3291 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 3292 3293 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 3294 3295 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3296 over multiple buffers, this field will be valid in the Last 3297 buffer used by the MSDU 3298 3299 3300 3301 Indicates that OLE found a valid DA entry for this MSDU 3302 3303 <legal all> 3304 */ 3305 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 3306 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 3307 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 3308 3309 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 3310 3311 Field Only valid if da_is_valid is set 3312 3313 3314 3315 Indicates the DA address was a Multicast of Broadcast 3316 address for this MSDU 3317 3318 <legal all> 3319 */ 3320 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 3321 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 3322 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 3323 3324 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 3325 3326 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3327 over multiple buffers, this field will be valid in the Last 3328 buffer used by the MSDU 3329 3330 3331 3332 Indicates an unsuccessful MAC destination address search 3333 due to the expiring of the search timer for this MSDU 3334 3335 <legal all> 3336 */ 3337 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078 3338 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 3339 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 3340 3341 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 3342 3343 <legal 0> 3344 */ 3345 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000078 3346 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 3347 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 3348 3349 /* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 3350 3351 <legal 0> 3352 */ 3353 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000007c 3354 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 3355 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 3356 3357 3358 #endif // _RX_MSDU_LINK_H_ 3359