1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _TCL_GSE_CMD_H_ 25 #define _TCL_GSE_CMD_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 control_buffer_addr_31_0[31:0] 34 // 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], index_search_en[15], cache_set_num[19:16], reserved_1a[31:20] 35 // 2 cmd_meta_data_31_0[31:0] 36 // 3 cmd_meta_data_63_32[31:0] 37 // 4 reserved_4a[31:0] 38 // 5 reserved_5a[31:0] 39 // 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] 40 // 41 // ################ END SUMMARY ################# 42 43 #define NUM_OF_DWORDS_TCL_GSE_CMD 7 44 45 struct tcl_gse_cmd { 46 uint32_t control_buffer_addr_31_0 : 32; //[31:0] 47 uint32_t control_buffer_addr_39_32 : 8, //[7:0] 48 gse_ctrl : 4, //[11:8] 49 gse_sel : 1, //[12] 50 status_destination_ring_id : 1, //[13] 51 swap : 1, //[14] 52 index_search_en : 1, //[15] 53 cache_set_num : 4, //[19:16] 54 reserved_1a : 12; //[31:20] 55 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 56 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 57 uint32_t reserved_4a : 32; //[31:0] 58 uint32_t reserved_5a : 32; //[31:0] 59 uint32_t reserved_6a : 20, //[19:0] 60 ring_id : 8, //[27:20] 61 looping_count : 4; //[31:28] 62 }; 63 64 /* 65 66 control_buffer_addr_31_0 67 68 Address (lower 32 bits) of a control buffer containing 69 additional info needed for this command execution. 70 71 <legal all> 72 73 control_buffer_addr_39_32 74 75 Address (upper 8 bits) of a control buffer containing 76 additional info needed for this command execution. 77 78 <legal all> 79 80 gse_ctrl 81 82 GSE control operations. This includes cache operations 83 and table entry statistics read/clear operation. 84 85 <enum 0 rd_stat> Report or Read statistics 86 87 <enum 1 srch_dis> Search disable. Report only Hash 88 89 <enum 2 Wr_bk_single> Write Back single entry 90 91 <enum 3 wr_bk_all> Write Back entire cache entry 92 93 <enum 4 inval_single> Invalidate single cache entry 94 95 <enum 5 inval_all> Invalidate entire cache 96 97 <enum 6 wr_bk_inval_single> Write back and Invalidate 98 single entry in cache 99 100 <enum 7 wr_bk_inval_all> write back and invalidate 101 entire cache 102 103 <enum 8 clr_stat_single> Clear statistics for single 104 entry 105 106 <legal 0-8> 107 108 Rest of the values reserved. 109 110 For all single entry control operations (write back, 111 Invalidate or both)Statistics will be reported 112 113 gse_sel 114 115 Bit to select the ASE or FSE to do the operation mention 116 by GSE_ctrl bit 117 118 0: FSE select 119 120 1: ASE select 121 122 status_destination_ring_id 123 124 The TCL status ring to which the GSE status needs to be 125 send. 126 127 128 129 <enum 0 tcl_status_0_ring> 130 131 <enum 1 tcl_status_1_ring> 132 133 134 135 <legal all> 136 137 swap 138 139 Bit to enable byte swapping of contents of buffer 140 141 <enum 0 Byte_swap_disable > 142 143 <enum 1 byte_swap_enable > 144 145 <legal all> 146 147 index_search_en 148 149 When this bit is set to 1 control_buffer_addr[19:0] will 150 be considered as index of the AST or Flow table and GSE 151 commands will be executed accordingly on the entry pointed 152 by the index. 153 154 This feature is disabled by setting this bit to 0. 155 156 <enum 0 index_based_cmd_disable> 157 158 <enum 1 index_based_cmd_enable> 159 160 161 162 <legal all> 163 164 cache_set_num 165 166 Cache set number that should be used to cache the index 167 based search results, for address and flow search. This 168 value should be equal to value of cache_set_num for the 169 index that is issued in TCL_DATA_CMD during search index 170 based ASE or FSE. This field is valid for index based GSE 171 commands 172 173 <legal all> 174 175 reserved_1a 176 177 <legal 0> 178 179 cmd_meta_data_31_0 180 181 Meta data to be returned in the status descriptor 182 183 <legal all> 184 185 cmd_meta_data_63_32 186 187 Meta data to be returned in the status descriptor 188 189 <legal all> 190 191 reserved_4a 192 193 <legal 0> 194 195 reserved_5a 196 197 <legal 0> 198 199 reserved_6a 200 201 <legal 0> 202 203 ring_id 204 205 Helps with debugging when dumping ring contents. 206 207 <legal all> 208 209 looping_count 210 211 A count value that indicates the number of times the 212 producer of entries into the Ring has looped around the 213 ring. 214 215 At initialization time, this value is set to 0. On the 216 first loop, this value is set to 1. After the max value is 217 reached allowed by the number of bits for this field, the 218 count value continues with 0 again. 219 220 221 222 In case SW is the consumer of the ring entries, it can 223 use this field to figure out up to where the producer of 224 entries has created new entries. This eliminates the need to 225 check where the head pointer' of the ring is located once 226 the SW starts processing an interrupt indicating that new 227 entries have been put into this ring... 228 229 230 231 Also note that SW if it wants only needs to look at the 232 LSB bit of this count value. 233 234 <legal all> 235 */ 236 237 238 /* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 239 240 Address (lower 32 bits) of a control buffer containing 241 additional info needed for this command execution. 242 243 <legal all> 244 */ 245 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 246 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 247 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 248 249 /* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 250 251 Address (upper 8 bits) of a control buffer containing 252 additional info needed for this command execution. 253 254 <legal all> 255 */ 256 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 257 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 258 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 259 260 /* Description TCL_GSE_CMD_1_GSE_CTRL 261 262 GSE control operations. This includes cache operations 263 and table entry statistics read/clear operation. 264 265 <enum 0 rd_stat> Report or Read statistics 266 267 <enum 1 srch_dis> Search disable. Report only Hash 268 269 <enum 2 Wr_bk_single> Write Back single entry 270 271 <enum 3 wr_bk_all> Write Back entire cache entry 272 273 <enum 4 inval_single> Invalidate single cache entry 274 275 <enum 5 inval_all> Invalidate entire cache 276 277 <enum 6 wr_bk_inval_single> Write back and Invalidate 278 single entry in cache 279 280 <enum 7 wr_bk_inval_all> write back and invalidate 281 entire cache 282 283 <enum 8 clr_stat_single> Clear statistics for single 284 entry 285 286 <legal 0-8> 287 288 Rest of the values reserved. 289 290 For all single entry control operations (write back, 291 Invalidate or both)Statistics will be reported 292 */ 293 #define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 294 #define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 295 #define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 296 297 /* Description TCL_GSE_CMD_1_GSE_SEL 298 299 Bit to select the ASE or FSE to do the operation mention 300 by GSE_ctrl bit 301 302 0: FSE select 303 304 1: ASE select 305 */ 306 #define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 307 #define TCL_GSE_CMD_1_GSE_SEL_LSB 12 308 #define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 309 310 /* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID 311 312 The TCL status ring to which the GSE status needs to be 313 send. 314 315 316 317 <enum 0 tcl_status_0_ring> 318 319 <enum 1 tcl_status_1_ring> 320 321 322 323 <legal all> 324 */ 325 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 326 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 327 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 328 329 /* Description TCL_GSE_CMD_1_SWAP 330 331 Bit to enable byte swapping of contents of buffer 332 333 <enum 0 Byte_swap_disable > 334 335 <enum 1 byte_swap_enable > 336 337 <legal all> 338 */ 339 #define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 340 #define TCL_GSE_CMD_1_SWAP_LSB 14 341 #define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 342 343 /* Description TCL_GSE_CMD_1_INDEX_SEARCH_EN 344 345 When this bit is set to 1 control_buffer_addr[19:0] will 346 be considered as index of the AST or Flow table and GSE 347 commands will be executed accordingly on the entry pointed 348 by the index. 349 350 This feature is disabled by setting this bit to 0. 351 352 <enum 0 index_based_cmd_disable> 353 354 <enum 1 index_based_cmd_enable> 355 356 357 358 <legal all> 359 */ 360 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 361 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 362 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 363 364 /* Description TCL_GSE_CMD_1_CACHE_SET_NUM 365 366 Cache set number that should be used to cache the index 367 based search results, for address and flow search. This 368 value should be equal to value of cache_set_num for the 369 index that is issued in TCL_DATA_CMD during search index 370 based ASE or FSE. This field is valid for index based GSE 371 commands 372 373 <legal all> 374 */ 375 #define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 376 #define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 377 #define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 378 379 /* Description TCL_GSE_CMD_1_RESERVED_1A 380 381 <legal 0> 382 */ 383 #define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 384 #define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 385 #define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 386 387 /* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 388 389 Meta data to be returned in the status descriptor 390 391 <legal all> 392 */ 393 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 394 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 395 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff 396 397 /* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 398 399 Meta data to be returned in the status descriptor 400 401 <legal all> 402 */ 403 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c 404 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 405 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff 406 407 /* Description TCL_GSE_CMD_4_RESERVED_4A 408 409 <legal 0> 410 */ 411 #define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 412 #define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 413 #define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff 414 415 /* Description TCL_GSE_CMD_5_RESERVED_5A 416 417 <legal 0> 418 */ 419 #define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 420 #define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 421 #define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff 422 423 /* Description TCL_GSE_CMD_6_RESERVED_6A 424 425 <legal 0> 426 */ 427 #define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 428 #define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 429 #define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff 430 431 /* Description TCL_GSE_CMD_6_RING_ID 432 433 Helps with debugging when dumping ring contents. 434 435 <legal all> 436 */ 437 #define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 438 #define TCL_GSE_CMD_6_RING_ID_LSB 20 439 #define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 440 441 /* Description TCL_GSE_CMD_6_LOOPING_COUNT 442 443 A count value that indicates the number of times the 444 producer of entries into the Ring has looped around the 445 ring. 446 447 At initialization time, this value is set to 0. On the 448 first loop, this value is set to 1. After the max value is 449 reached allowed by the number of bits for this field, the 450 count value continues with 0 again. 451 452 453 454 In case SW is the consumer of the ring entries, it can 455 use this field to figure out up to where the producer of 456 entries has created new entries. This eliminates the need to 457 check where the head pointer' of the ring is located once 458 the SW starts processing an interrupt indicating that new 459 entries have been put into this ring... 460 461 462 463 Also note that SW if it wants only needs to look at the 464 LSB bit of this count value. 465 466 <legal all> 467 */ 468 #define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 469 #define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 470 #define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 471 472 473 #endif // _TCL_GSE_CMD_H_ 474