1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _BUFFER_ADDR_INFO_H_ 25 #define _BUFFER_ADDR_INFO_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 buffer_addr_31_0[31:0] 34 // 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11] 35 // 36 // ################ END SUMMARY ################# 37 38 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 39 40 struct buffer_addr_info { 41 uint32_t buffer_addr_31_0 : 32; //[31:0] 42 uint32_t buffer_addr_39_32 : 8, //[7:0] 43 return_buffer_manager : 3, //[10:8] 44 sw_buffer_cookie : 21; //[31:11] 45 }; 46 47 /* 48 49 buffer_addr_31_0 50 51 Address (lower 32 bits) of the MSDU buffer OR 52 MSDU_EXTENSION descriptor OR Link Descriptor 53 54 55 56 In case of 'NULL' pointer, this field is set to 0 57 58 <legal all> 59 60 buffer_addr_39_32 61 62 Address (upper 8 bits) of the MSDU buffer OR 63 MSDU_EXTENSION descriptor OR Link Descriptor 64 65 66 67 In case of 'NULL' pointer, this field is set to 0 68 69 <legal all> 70 71 return_buffer_manager 72 73 Consumer: WBM 74 75 Producer: SW/FW 76 77 78 79 In case of 'NULL' pointer, this field is set to 0 80 81 82 83 Indicates to which buffer manager the buffer OR 84 MSDU_EXTENSION descriptor OR link descriptor that is being 85 pointed to shall be returned after the frame has been 86 processed. It is used by WBM for routing purposes. 87 88 89 90 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 91 to the WMB buffer idle list 92 93 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 94 returned to the WMB idle link descriptor idle list 95 96 <enum 2 FW_BM> This buffer shall be returned to the FW 97 98 <enum 3 SW0_BM> This buffer shall be returned to the SW, 99 ring 0 100 101 <enum 4 SW1_BM> This buffer shall be returned to the SW, 102 ring 1 103 104 <enum 5 SW2_BM> This buffer shall be returned to the SW, 105 ring 2 106 107 <enum 6 SW3_BM> This buffer shall be returned to the SW, 108 ring 3 109 110 <enum 7 SW4_BM> This buffer shall be returned to the SW, 111 ring 4 112 113 114 115 <legal all> 116 117 sw_buffer_cookie 118 119 Cookie field exclusively used by SW. 120 121 122 123 In case of 'NULL' pointer, this field is set to 0 124 125 126 127 HW ignores the contents, accept that it passes the 128 programmed value on to other descriptors together with the 129 physical address 130 131 132 133 Field can be used by SW to for example associate the 134 buffers physical address with the virtual address 135 136 The bit definitions as used by SW are within SW HLD 137 specification 138 139 140 141 NOTE: 142 143 The three most significant bits can have a special 144 meaning in case this struct is embedded in a TX_MPDU_DETAILS 145 STRUCT, and field transmit_bw_restriction is set 146 147 148 149 In case of NON punctured transmission: 150 151 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 152 153 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 154 155 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 156 157 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 158 159 160 161 In case of punctured transmission: 162 163 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 164 165 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 166 167 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 168 169 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 170 171 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 172 173 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 174 175 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 176 177 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 178 179 180 181 Note: a punctured transmission is indicated by the 182 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 183 TLV 184 185 186 187 <legal all> 188 */ 189 190 191 /* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0 192 193 Address (lower 32 bits) of the MSDU buffer OR 194 MSDU_EXTENSION descriptor OR Link Descriptor 195 196 197 198 In case of 'NULL' pointer, this field is set to 0 199 200 <legal all> 201 */ 202 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 203 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 204 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff 205 206 /* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32 207 208 Address (upper 8 bits) of the MSDU buffer OR 209 MSDU_EXTENSION descriptor OR Link Descriptor 210 211 212 213 In case of 'NULL' pointer, this field is set to 0 214 215 <legal all> 216 */ 217 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 218 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 219 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff 220 221 /* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER 222 223 Consumer: WBM 224 225 Producer: SW/FW 226 227 228 229 In case of 'NULL' pointer, this field is set to 0 230 231 232 233 Indicates to which buffer manager the buffer OR 234 MSDU_EXTENSION descriptor OR link descriptor that is being 235 pointed to shall be returned after the frame has been 236 processed. It is used by WBM for routing purposes. 237 238 239 240 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 241 to the WMB buffer idle list 242 243 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 244 returned to the WMB idle link descriptor idle list 245 246 <enum 2 FW_BM> This buffer shall be returned to the FW 247 248 <enum 3 SW0_BM> This buffer shall be returned to the SW, 249 ring 0 250 251 <enum 4 SW1_BM> This buffer shall be returned to the SW, 252 ring 1 253 254 <enum 5 SW2_BM> This buffer shall be returned to the SW, 255 ring 2 256 257 <enum 6 SW3_BM> This buffer shall be returned to the SW, 258 ring 3 259 260 <enum 7 SW4_BM> This buffer shall be returned to the SW, 261 ring 4 262 263 264 265 <legal all> 266 */ 267 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 268 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8 269 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700 270 271 /* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE 272 273 Cookie field exclusively used by SW. 274 275 276 277 In case of 'NULL' pointer, this field is set to 0 278 279 280 281 HW ignores the contents, accept that it passes the 282 programmed value on to other descriptors together with the 283 physical address 284 285 286 287 Field can be used by SW to for example associate the 288 buffers physical address with the virtual address 289 290 The bit definitions as used by SW are within SW HLD 291 specification 292 293 294 295 NOTE: 296 297 The three most significant bits can have a special 298 meaning in case this struct is embedded in a TX_MPDU_DETAILS 299 STRUCT, and field transmit_bw_restriction is set 300 301 302 303 In case of NON punctured transmission: 304 305 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 306 307 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 308 309 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 310 311 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 312 313 314 315 In case of punctured transmission: 316 317 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 318 319 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 320 321 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 322 323 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 324 325 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 326 327 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 328 329 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 330 331 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 332 333 334 335 Note: a punctured transmission is indicated by the 336 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 337 TLV 338 339 340 341 <legal all> 342 */ 343 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004 344 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11 345 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800 346 347 348 #endif // _BUFFER_ADDR_INFO_H_ 349