1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _PHYRX_PKT_END_INFO_H_ 25 #define _PHYRX_PKT_END_INFO_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rx_location_info.h" 30 #include "rx_timing_offset_info.h" 31 #include "receive_rssi_info.h" 32 33 // ################ START SUMMARY ################# 34 // 35 // Dword Fields 36 // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27] 37 // 1 phy_timestamp_1_lower_32[31:0] 38 // 2 phy_timestamp_1_upper_32[31:0] 39 // 3 phy_timestamp_2_lower_32[31:0] 40 // 4 phy_timestamp_2_upper_32[31:0] 41 // 5-13 struct rx_location_info rx_location_info_details; 42 // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 43 // 15-30 struct receive_rssi_info post_rssi_info_details; 44 // 31 phy_sw_status_31_0[31:0] 45 // 32 phy_sw_status_63_32[31:0] 46 // 47 // ################ END SUMMARY ################# 48 49 #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 50 51 struct phyrx_pkt_end_info { 52 uint32_t phy_internal_nap : 1, //[0] 53 location_info_valid : 1, //[1] 54 timing_info_valid : 1, //[2] 55 rssi_info_valid : 1, //[3] 56 rx_frame_correction_needed : 1, //[4] 57 frameless_frame_received : 1, //[5] 58 reserved_0a : 6, //[11:6] 59 dl_ofdma_info_valid : 1, //[12] 60 dl_ofdma_ru_start_index : 7, //[19:13] 61 dl_ofdma_ru_width : 7, //[26:20] 62 reserved_0b : 5; //[31:27] 63 uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 64 uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 65 uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 66 uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 67 struct rx_location_info rx_location_info_details; 68 struct rx_timing_offset_info rx_timing_offset_info_details; 69 struct receive_rssi_info post_rssi_info_details; 70 uint32_t phy_sw_status_31_0 : 32; //[31:0] 71 uint32_t phy_sw_status_63_32 : 32; //[31:0] 72 }; 73 74 /* 75 76 phy_internal_nap 77 78 When set, PHY RX entered an internal NAP state, as PHY 79 determined that this reception was not destined to this 80 device 81 82 location_info_valid 83 84 Indicates that the RX_LOCATION_INFO structure later on 85 in the TLV contains valid info 86 87 timing_info_valid 88 89 Indicates that the RX_TIMING_OFFSET_INFO structure later 90 on in the TLV contains valid info 91 92 rssi_info_valid 93 94 Indicates that the RECEIVE_RSSI_INFO structure later on 95 in the TLV contains valid info 96 97 rx_frame_correction_needed 98 99 When clear, no action is needed in the MAC. 100 101 102 103 When set, the falling edge of the rx_frame happened 4us 104 too late. MAC will need to compensate for this delay in 105 order to maintain proper SIFS timing and/or not to get 106 de-slotted. 107 108 109 110 PHY uses this for very short 11a frames. 111 112 113 114 When set, PHY will have passed this TLV to the MAC up to 115 8 us into the 'real SIFS' time, and thus within 4us from the 116 falling edge of the rx_frame. 117 118 119 120 <legal all> 121 122 frameless_frame_received 123 124 When set, PHY has received the 'frameless frame' . Can 125 be used in the 'MU-RTS -CTS exchange where CTS reception can 126 be problematic. 127 128 <legal all> 129 130 reserved_0a 131 132 <legal 0> 133 134 dl_ofdma_info_valid 135 136 When set, the following DL_ofdma_... fields are valid. 137 138 It provides the MAC insight into which RU was allocated 139 to this device. 140 141 <legal all> 142 143 dl_ofdma_ru_start_index 144 145 RU index number to which User is assigned 146 147 RU numbering is over the entire BW, starting from 0 and 148 in increasing frequency order and not primary-secondary 149 order 150 151 <legal 0-73> 152 153 dl_ofdma_ru_width 154 155 The size of the RU for this user. 156 157 In units of 1 (26 tone) RU 158 159 <legal 1-74> 160 161 reserved_0b 162 163 <legal 0> 164 165 phy_timestamp_1_lower_32 166 167 TODO PHY: cleanup descriptionThe PHY timestamp in the 168 AMPI of the first rising edge of rx_clear_pri after 169 TX_PHY_DESC. . This field should set to 0 by the PHY and 170 should be updated by the AMPI before being forwarded to the 171 rest of the MAC. This field indicates the lower 32 bits of 172 the timestamp 173 174 phy_timestamp_1_upper_32 175 176 TODO PHY: cleanup description 177 178 The PHY timestamp in the AMPI of the first rising edge 179 of rx_clear_pri after TX_PHY_DESC. This field should set to 180 0 by the PHY and should be updated by the AMPI before being 181 forwarded to the rest of the MAC. This field indicates the 182 upper 32 bits of the timestamp 183 184 phy_timestamp_2_lower_32 185 186 TODO PHY: cleanup description 187 188 The PHY timestamp in the AMPI of the rising edge of 189 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 190 0 by the PHY and should be updated by the AMPI before being 191 forwarded to the rest of the MAC. This field indicates the 192 lower 32 bits of the timestamp 193 194 phy_timestamp_2_upper_32 195 196 TODO PHY: cleanup description 197 198 The PHY timestamp in the AMPI of the rising edge of 199 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 200 0 by the PHY and should be updated by the AMPI before being 201 forwarded to the rest of the MAC. This field indicates the 202 upper 32 bits of the timestamp 203 204 struct rx_location_info rx_location_info_details 205 206 Overview of location related info 207 208 struct rx_timing_offset_info rx_timing_offset_info_details 209 210 Overview of timing offset related info 211 212 struct receive_rssi_info post_rssi_info_details 213 214 Overview of the post-RSSI values. 215 216 phy_sw_status_31_0 217 218 Some PHY micro code status that can be put in here. 219 Details of definition within SW specification 220 221 This field can be used for debugging, FW - SW message 222 exchange, etc. 223 224 It could for example be a pointer to a DDR memory 225 location where PHY FW put some debug info. 226 227 <legal all> 228 229 phy_sw_status_63_32 230 231 Some PHY micro code status that can be put in here. 232 Details of definition within SW specification 233 234 This field can be used for debugging, FW - SW message 235 exchange, etc. 236 237 It could for example be a pointer to a DDR memory 238 location where PHY FW put some debug info. 239 240 <legal all> 241 */ 242 243 244 /* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP 245 246 When set, PHY RX entered an internal NAP state, as PHY 247 determined that this reception was not destined to this 248 device 249 */ 250 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 251 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 252 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 253 254 /* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID 255 256 Indicates that the RX_LOCATION_INFO structure later on 257 in the TLV contains valid info 258 */ 259 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 260 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 261 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 262 263 /* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID 264 265 Indicates that the RX_TIMING_OFFSET_INFO structure later 266 on in the TLV contains valid info 267 */ 268 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 269 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 270 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 271 272 /* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID 273 274 Indicates that the RECEIVE_RSSI_INFO structure later on 275 in the TLV contains valid info 276 */ 277 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 278 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 279 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 280 281 /* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED 282 283 When clear, no action is needed in the MAC. 284 285 286 287 When set, the falling edge of the rx_frame happened 4us 288 too late. MAC will need to compensate for this delay in 289 order to maintain proper SIFS timing and/or not to get 290 de-slotted. 291 292 293 294 PHY uses this for very short 11a frames. 295 296 297 298 When set, PHY will have passed this TLV to the MAC up to 299 8 us into the 'real SIFS' time, and thus within 4us from the 300 falling edge of the rx_frame. 301 302 303 304 <legal all> 305 */ 306 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 307 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 308 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 309 310 /* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED 311 312 When set, PHY has received the 'frameless frame' . Can 313 be used in the 'MU-RTS -CTS exchange where CTS reception can 314 be problematic. 315 316 <legal all> 317 */ 318 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 319 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 320 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 321 322 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0A 323 324 <legal 0> 325 */ 326 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 327 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 328 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 329 330 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID 331 332 When set, the following DL_ofdma_... fields are valid. 333 334 It provides the MAC insight into which RU was allocated 335 to this device. 336 337 <legal all> 338 */ 339 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 340 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 341 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 342 343 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX 344 345 RU index number to which User is assigned 346 347 RU numbering is over the entire BW, starting from 0 and 348 in increasing frequency order and not primary-secondary 349 order 350 351 <legal 0-73> 352 */ 353 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 354 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 355 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 356 357 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH 358 359 The size of the RU for this user. 360 361 In units of 1 (26 tone) RU 362 363 <legal 1-74> 364 */ 365 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 366 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 367 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 368 369 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0B 370 371 <legal 0> 372 */ 373 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 374 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 375 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 376 377 /* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 378 379 TODO PHY: cleanup descriptionThe PHY timestamp in the 380 AMPI of the first rising edge of rx_clear_pri after 381 TX_PHY_DESC. . This field should set to 0 by the PHY and 382 should be updated by the AMPI before being forwarded to the 383 rest of the MAC. This field indicates the lower 32 bits of 384 the timestamp 385 */ 386 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 387 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 388 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 389 390 /* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 391 392 TODO PHY: cleanup description 393 394 The PHY timestamp in the AMPI of the first rising edge 395 of rx_clear_pri after TX_PHY_DESC. This field should set to 396 0 by the PHY and should be updated by the AMPI before being 397 forwarded to the rest of the MAC. This field indicates the 398 upper 32 bits of the timestamp 399 */ 400 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 401 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 402 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 403 404 /* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 405 406 TODO PHY: cleanup description 407 408 The PHY timestamp in the AMPI of the rising edge of 409 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 410 0 by the PHY and should be updated by the AMPI before being 411 forwarded to the rest of the MAC. This field indicates the 412 lower 32 bits of the timestamp 413 */ 414 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 415 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 416 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 417 418 /* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 419 420 TODO PHY: cleanup description 421 422 The PHY timestamp in the AMPI of the rising edge of 423 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 424 0 by the PHY and should be updated by the AMPI before being 425 forwarded to the rest of the MAC. This field indicates the 426 upper 32 bits of the timestamp 427 */ 428 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 429 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 430 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 431 432 /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */ 433 434 435 /* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY 436 437 For 20/40/80, this field shows the RTT first arrival 438 correction value computed from L-LTF on the first selected 439 Rx chain 440 441 442 443 For 80+80, this field shows the RTT first arrival 444 correction value computed from L-LTF on pri80 on the 445 selected pri80 Rx chain 446 447 448 449 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 450 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 451 interpolation 452 453 454 455 clock unit is 320MHz 456 457 <legal all> 458 */ 459 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 460 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 461 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff 462 463 /* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80 464 465 For 20/40/80, this field shows the RTT first arrival 466 correction value computed from L-LTF on the second selected 467 Rx chain 468 469 470 471 For 80+80, this field shows the RTT first arrival 472 correction value computed from L-LTF on ext80 on the 473 selected ext80 Rx chain 474 475 476 477 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 478 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 479 interpolation 480 481 482 483 clock unit is 320MHz 484 485 <legal all> 486 */ 487 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 488 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 489 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 490 491 /* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT 492 493 For 20/40/80, this field shows the RTT first arrival 494 correction value computed from (V)HT/HE-LTF on the first 495 selected Rx chain 496 497 498 499 For 80+80, this field shows the RTT first arrival 500 correction value computed from (V)HT/HE-LTF on pri80 on the 501 selected pri80 Rx chain 502 503 504 505 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 506 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 507 interpolation 508 509 510 511 clock unit is 320MHz 512 513 <legal all> 514 */ 515 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 516 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 517 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff 518 519 /* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80 520 521 For 20/40/80, this field shows the RTT first arrival 522 correction value computed from (V)HT/HE-LTF on the second 523 selected Rx chain 524 525 526 527 For 80+80, this field shows the RTT first arrival 528 correction value computed from (V)HT/HE-LTF on ext80 on the 529 selected ext80 Rx chain 530 531 532 533 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 534 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 535 interpolation 536 537 538 539 clock unit is 320MHz 540 541 <legal all> 542 */ 543 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 544 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 545 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 546 547 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS 548 549 Status of rtt_fac_legacy 550 551 552 553 <enum 0 location_fac_legacy_status_not_valid> 554 555 <enum 1 location_fac_legacy_status_valid> 556 557 <legal all> 558 */ 559 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c 560 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 561 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 562 563 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS 564 565 Status of rtt_fac_legacy_ext80 566 567 568 569 <enum 0 location_fac_legacy_ext80_status_not_valid> 570 571 <enum 1 location_fac_legacy_ext80_status_valid> 572 573 <legal all> 574 */ 575 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c 576 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 577 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 578 579 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS 580 581 Status of rtt_fac_vht 582 583 584 585 <enum 0 location_fac_vht_status_not_valid> 586 587 <enum 1 location_fac_vht_status_valid> 588 589 <legal all> 590 */ 591 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c 592 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 593 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 594 595 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS 596 597 Status of rtt_fac_vht_ext80 598 599 600 601 <enum 0 location_fac_vht_ext80_status_not_valid> 602 603 <enum 1 location_fac_vht_ext80_status_valid> 604 605 <legal all> 606 */ 607 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c 608 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 609 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 610 611 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS 612 613 To support fine SIFS adjustment, need to provide FAC 614 value @ integer number of 320 MHz clock cycles to MAC. It 615 is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF 616 if it is a (V)HT/HE packet 617 618 619 620 12 bits, signed, no fractional part 621 622 <legal all> 623 */ 624 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c 625 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 626 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 627 628 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS 629 630 Status of rtt_fac_sifs 631 632 0: not valid 633 634 1: valid and from L-LTF 635 636 2: valid and from (V)HT/HE-LTF 637 638 3: reserved 639 640 <legal 0-2> 641 */ 642 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c 643 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 644 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 645 646 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS 647 648 Status of channel frequency response dump 649 650 651 652 <enum 0 location_CFR_dump_not_valid> 653 654 <enum 1 location_CFR_dump_valid> 655 656 <legal all> 657 */ 658 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c 659 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 660 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 661 662 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS 663 664 Status of channel impulse response dump 665 666 667 668 <enum 0 location_CIR_dump_not_valid> 669 670 <enum 1 location_CIR_dump_valid> 671 672 <legal all> 673 */ 674 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c 675 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 676 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 677 678 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE 679 680 Channel dump size. It shows how many tones in CFR in 681 one chain, for example, it will show 52 for Legacy20 and 484 682 for VHT160 683 684 685 686 <legal all> 687 */ 688 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c 689 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 690 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 691 692 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE 693 694 Indicator showing if HW IFFT mode or SW IFFT mode 695 696 697 698 <enum 0 location_sw_ifft_mode> 699 700 <enum 1 location_hw_ifft_mode> 701 702 <legal all> 703 */ 704 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c 705 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 706 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 707 708 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS 709 710 Indicate if BTCF is used to capture the timestamps 711 712 713 714 <enum 0 location_not_BTCF_based_ts> 715 716 <enum 1 location_BTCF_based_ts> 717 718 <legal all> 719 */ 720 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 721 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 722 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 723 724 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE 725 726 Indicate preamble type 727 728 729 730 <enum 0 location_preamble_type_legacy> 731 732 <enum 1 location_preamble_type_ht> 733 734 <enum 2 location_preamble_type_vht> 735 736 <enum 3 location_preamble_type_he_su_4xltf> 737 738 <enum 4 location_preamble_type_he_su_2xltf> 739 740 <enum 5 location_preamble_type_he_su_1xltf> 741 742 <enum 6 743 location_preamble_type_he_trigger_based_ul_4xltf> 744 745 <enum 7 746 location_preamble_type_he_trigger_based_ul_2xltf> 747 748 <enum 8 749 location_preamble_type_he_trigger_based_ul_1xltf> 750 751 <enum 9 location_preamble_type_he_mu_4xltf> 752 753 <enum 10 location_preamble_type_he_mu_2xltf> 754 755 <enum 11 location_preamble_type_he_mu_1xltf> 756 757 <enum 12 758 location_preamble_type_he_extended_range_su_4xltf> 759 760 <enum 13 761 location_preamble_type_he_extended_range_su_2xltf> 762 763 <enum 14 764 location_preamble_type_he_extended_range_su_1xltf> 765 766 <legal 0-14> 767 */ 768 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 769 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 770 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e 771 772 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG 773 774 Indicate the bandwidth of L-LTF 775 776 777 778 <enum 0 location_pkt_bw_20MHz> 779 780 <enum 1 location_pkt_bw_40MHz> 781 782 <enum 2 location_pkt_bw_80MHz> 783 784 <enum 3 location_pkt_bw_160MHz> 785 786 <legal all> 787 */ 788 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 789 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 790 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 791 792 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT 793 794 Indicate the bandwidth of (V)HT/HE-LTF 795 796 797 798 <enum 0 location_pkt_bw_20MHz> 799 800 <enum 1 location_pkt_bw_40MHz> 801 802 <enum 2 location_pkt_bw_80MHz> 803 804 <enum 3 location_pkt_bw_160MHz> 805 806 <legal all> 807 */ 808 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 809 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 810 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 811 812 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE 813 814 Indicate GI (guard interval) type 815 816 817 818 <enum 0 gi_0_8_us > HE related GI. Can also be used 819 for HE 820 821 <enum 1 gi_0_4_us > HE related GI. Can also be used 822 for HE 823 824 <enum 2 gi_1_6_us > HE related GI 825 826 <enum 3 gi_3_2_us > HE related GI 827 828 <legal 0 - 3> 829 */ 830 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 831 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 832 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 833 834 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE 835 836 Bits 0~4 indicate MCS rate, if Legacy, 837 838 0: 48 Mbps, 839 840 1: 24 Mbps, 841 842 2: 12 Mbps, 843 844 3: 6 Mbps, 845 846 4: 54 Mbps, 847 848 5: 36 Mbps, 849 850 6: 18 Mbps, 851 852 7: 9 Mbps, 853 854 855 856 if HT, 0-7: MCS0-MCS7, 857 858 if VHT, 0-9: MCS0-MCS9, 859 860 861 <legal all> 862 */ 863 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 864 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 865 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 866 867 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN 868 869 For 20/40/80, this field shows the first selected Rx 870 chain that is used in HW IFFT mode 871 872 873 874 For 80+80, this field shows the selected pri80 Rx chain 875 that is used in HW IFFT mode 876 877 878 879 <enum 0 location_strongest_chain_is_0> 880 881 <enum 1 location_strongest_chain_is_1> 882 883 <enum 2 location_strongest_chain_is_2> 884 885 <enum 3 location_strongest_chain_is_3> 886 887 <enum 4 location_strongest_chain_is_4> 888 889 <enum 5 location_strongest_chain_is_5> 890 891 <enum 6 location_strongest_chain_is_6> 892 893 <enum 7 location_strongest_chain_is_7> 894 895 <legal all> 896 */ 897 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 898 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 899 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 900 901 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80 902 903 For 20/40/80, this field shows the second selected Rx 904 chain that is used in HW IFFT mode 905 906 907 908 For 80+80, this field shows the selected ext80 Rx chain 909 that is used in HW IFFT mode 910 911 912 913 <enum 0 location_strongest_chain_is_0> 914 915 <enum 1 location_strongest_chain_is_1> 916 917 <enum 2 location_strongest_chain_is_2> 918 919 <enum 3 location_strongest_chain_is_3> 920 921 <enum 4 location_strongest_chain_is_4> 922 923 <enum 5 location_strongest_chain_is_5> 924 925 <enum 6 location_strongest_chain_is_6> 926 927 <enum 7 location_strongest_chain_is_7> 928 929 <legal all> 930 */ 931 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 932 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 933 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 934 935 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK 936 937 Rx chain mask, each bit is a Rx chain 938 939 0: the Rx chain is not used 940 941 1: the Rx chain is used 942 943 Support up to 8 Rx chains 944 945 <legal all> 946 */ 947 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 948 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 949 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 950 951 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3 952 953 <legal 0> 954 */ 955 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 956 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 957 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 958 959 /* Description PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS 960 961 RX packet start timestamp 962 963 964 965 It reports the time the first L-STF ADC sample arrived 966 at RX antenna 967 968 969 970 clock unit is 480MHz 971 972 <legal all> 973 */ 974 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 975 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 976 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff 977 978 /* Description PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS 979 980 RX packet end timestamp 981 982 983 984 It reports the time the last symbol's last ADC sample 985 arrived at RX antenna 986 987 988 989 clock unit is 480MHz 990 991 <legal all> 992 */ 993 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 994 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 995 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff 996 997 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START 998 999 The phase of the SFO of the first symbol's first FFT 1000 input sample 1001 1002 1003 1004 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 1005 66.7ns, and 6 bits fraction to provide a resolution of 1006 0.03ns 1007 1008 1009 1010 clock unit is 480MHz 1011 1012 <legal all> 1013 */ 1014 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c 1015 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 1016 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff 1017 1018 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END 1019 1020 The phase of the SFO of the last symbol's last FFT input 1021 sample 1022 1023 1024 1025 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 1026 66.7ns, and 6 bits fraction to provide a resolution of 1027 0.03ns 1028 1029 1030 1031 clock unit is 480MHz 1032 1033 <legal all> 1034 */ 1035 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c 1036 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 1037 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 1038 1039 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8 1040 1041 The high 8 bits of the 40 bits pointer pointed to the 1042 external RTT channel information buffer 1043 1044 1045 1046 8 bits 1047 1048 <legal all> 1049 */ 1050 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c 1051 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 1052 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 1053 1054 /* Description PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32 1055 1056 The low 32 bits of the 40 bits pointer pointed to the 1057 external RTT channel information buffer 1058 1059 1060 1061 32 bits 1062 1063 <legal all> 1064 */ 1065 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 1066 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 1067 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff 1068 1069 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT 1070 1071 CFO measurement. Needed for passive locationing 1072 1073 1074 1075 14 bits, signed 1.13. 13 bits fraction to provide a 1076 resolution of 153 Hz 1077 1078 1079 1080 In units of cycles/800 ns 1081 1082 <legal all> 1083 */ 1084 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 1085 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 1086 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff 1087 1088 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD 1089 1090 Channel delay spread measurement. Needed for selecting 1091 GI length 1092 1093 1094 1095 8 bits, unsigned. At 25 ns step. Can represent up to 1096 6375 ns 1097 1098 1099 1100 In units of cycles @ 40 MHz 1101 1102 <legal all> 1103 */ 1104 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 1105 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 1106 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 1107 1108 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL 1109 1110 Indicate which timing backoff value is used 1111 1112 1113 1114 <enum 0 timing_backoff_low_rssi> 1115 1116 <enum 1 timing_backoff_mid_rssi> 1117 1118 <enum 2 timing_backoff_high_rssi> 1119 1120 <enum 3 reserved> 1121 1122 <legal all> 1123 */ 1124 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 1125 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 1126 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 1127 1128 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8 1129 1130 <legal 0> 1131 */ 1132 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 1133 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 1134 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 1135 1136 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID 1137 1138 <enum 0 rx_location_info_is_not_valid> 1139 1140 <enum 1 rx_location_info_is_valid> 1141 1142 <legal all> 1143 */ 1144 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 1145 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 1146 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 1147 1148 /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */ 1149 1150 1151 /* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET 1152 1153 Cumulative reference frequency error at end of RX 1154 1155 <legal all> 1156 */ 1157 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 1158 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 1159 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff 1160 1161 /* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED 1162 1163 <legal 0> 1164 */ 1165 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 1166 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 1167 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 1168 1169 /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */ 1170 1171 1172 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 1173 1174 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1175 1176 Value of 0x80 indicates invalid. 1177 */ 1178 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c 1179 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 1180 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 1181 1182 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 1183 1184 RSSI of RX PPDU on chain 0 of extension 20 MHz 1185 bandwidth. 1186 1187 Value of 0x80 indicates invalid. 1188 */ 1189 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c 1190 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 1191 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 1192 1193 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 1194 1195 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz 1196 bandwidth. 1197 1198 Value of 0x80 indicates invalid. 1199 */ 1200 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c 1201 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 1202 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 1203 1204 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 1205 1206 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 1207 bandwidth. 1208 1209 Value of 0x80 indicates invalid. 1210 */ 1211 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c 1212 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 1213 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 1214 1215 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 1216 1217 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz 1218 bandwidth. 1219 1220 Value of 0x80 indicates invalid. 1221 */ 1222 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 1223 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 1224 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 1225 1226 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 1227 1228 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 1229 MHz bandwidth. 1230 1231 Value of 0x80 indicates invalid. 1232 */ 1233 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 1234 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 1235 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 1236 1237 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 1238 1239 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 1240 MHz bandwidth. 1241 1242 Value of 0x80 indicates invalid. 1243 */ 1244 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 1245 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 1246 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 1247 1248 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 1249 1250 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 1251 bandwidth. 1252 1253 Value of 0x80 indicates invalid. 1254 */ 1255 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 1256 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 1257 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 1258 1259 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 1260 1261 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 1262 1263 Value of 0x80 indicates invalid. 1264 */ 1265 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 1266 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 1267 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 1268 1269 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 1270 1271 RSSI of RX PPDU on chain 1 of extension 20 MHz 1272 bandwidth. 1273 1274 Value of 0x80 indicates invalid. 1275 */ 1276 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 1277 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 1278 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 1279 1280 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 1281 1282 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz 1283 bandwidth. 1284 1285 Value of 0x80 indicates invalid. 1286 */ 1287 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 1288 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 1289 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 1290 1291 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 1292 1293 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 1294 bandwidth. 1295 1296 Value of 0x80 indicates invalid. 1297 */ 1298 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 1299 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 1300 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 1301 1302 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 1303 1304 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz 1305 bandwidth. 1306 1307 Value of 0x80 indicates invalid. 1308 */ 1309 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 1310 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 1311 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 1312 1313 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 1314 1315 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 1316 MHz bandwidth. 1317 1318 Value of 0x80 indicates invalid. 1319 */ 1320 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 1321 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 1322 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 1323 1324 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 1325 1326 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 1327 MHz bandwidth. 1328 1329 Value of 0x80 indicates invalid. 1330 */ 1331 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 1332 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 1333 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 1334 1335 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 1336 1337 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 1338 bandwidth. 1339 1340 Value of 0x80 indicates invalid. 1341 */ 1342 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 1343 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 1344 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 1345 1346 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 1347 1348 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 1349 1350 Value of 0x80 indicates invalid. 1351 */ 1352 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c 1353 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 1354 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 1355 1356 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 1357 1358 RSSI of RX PPDU on chain 2 of extension 20 MHz 1359 bandwidth. 1360 1361 Value of 0x80 indicates invalid. 1362 */ 1363 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c 1364 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 1365 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 1366 1367 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 1368 1369 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz 1370 bandwidth. 1371 1372 Value of 0x80 indicates invalid. 1373 */ 1374 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c 1375 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 1376 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 1377 1378 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 1379 1380 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 1381 bandwidth. 1382 1383 Value of 0x80 indicates invalid. 1384 */ 1385 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c 1386 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 1387 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 1388 1389 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 1390 1391 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz 1392 bandwidth. 1393 1394 Value of 0x80 indicates invalid. 1395 */ 1396 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 1397 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 1398 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 1399 1400 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 1401 1402 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 1403 MHz bandwidth. 1404 1405 Value of 0x80 indicates invalid. 1406 */ 1407 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 1408 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 1409 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 1410 1411 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 1412 1413 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 1414 MHz bandwidth. 1415 1416 Value of 0x80 indicates invalid. 1417 */ 1418 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 1419 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 1420 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 1421 1422 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 1423 1424 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 1425 bandwidth. 1426 1427 Value of 0x80 indicates invalid. 1428 */ 1429 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 1430 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 1431 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 1432 1433 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 1434 1435 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 1436 1437 Value of 0x80 indicates invalid. 1438 */ 1439 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 1440 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 1441 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 1442 1443 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 1444 1445 RSSI of RX PPDU on chain 3 of extension 20 MHz 1446 bandwidth. 1447 1448 Value of 0x80 indicates invalid. 1449 */ 1450 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 1451 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 1452 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 1453 1454 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 1455 1456 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz 1457 bandwidth. 1458 1459 Value of 0x80 indicates invalid. 1460 */ 1461 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 1462 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1463 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 1464 1465 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 1466 1467 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1468 bandwidth. 1469 1470 Value of 0x80 indicates invalid. 1471 */ 1472 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 1473 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1474 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 1475 1476 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 1477 1478 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz 1479 bandwidth. 1480 1481 Value of 0x80 indicates invalid. 1482 */ 1483 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 1484 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 1485 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 1486 1487 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 1488 1489 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1490 MHz bandwidth. 1491 1492 Value of 0x80 indicates invalid. 1493 */ 1494 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 1495 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 1496 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 1497 1498 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 1499 1500 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1501 MHz bandwidth. 1502 1503 Value of 0x80 indicates invalid. 1504 */ 1505 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 1506 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1507 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1508 1509 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 1510 1511 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1512 bandwidth. 1513 1514 Value of 0x80 indicates invalid. 1515 */ 1516 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 1517 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1518 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1519 1520 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 1521 1522 RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. 1523 1524 Value of 0x80 indicates invalid. 1525 */ 1526 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c 1527 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 1528 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff 1529 1530 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 1531 1532 RSSI of RX PPDU on chain 4 of extension 20 MHz 1533 bandwidth. 1534 1535 Value of 0x80 indicates invalid. 1536 */ 1537 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c 1538 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 1539 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 1540 1541 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 1542 1543 RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz 1544 bandwidth. 1545 1546 Value of 0x80 indicates invalid. 1547 */ 1548 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c 1549 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 1550 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 1551 1552 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 1553 1554 RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz 1555 bandwidth. 1556 1557 Value of 0x80 indicates invalid. 1558 */ 1559 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c 1560 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 1561 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 1562 1563 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 1564 1565 RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz 1566 bandwidth. 1567 1568 Value of 0x80 indicates invalid. 1569 */ 1570 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 1571 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 1572 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff 1573 1574 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 1575 1576 RSSI of RX PPDU on chain 4 of extension 80, low-high 20 1577 MHz bandwidth. 1578 1579 Value of 0x80 indicates invalid. 1580 */ 1581 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 1582 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 1583 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 1584 1585 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 1586 1587 RSSI of RX PPDU on chain 4 of extension 80, high-low 20 1588 MHz bandwidth. 1589 1590 Value of 0x80 indicates invalid. 1591 */ 1592 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 1593 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 1594 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 1595 1596 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 1597 1598 RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz 1599 bandwidth. 1600 1601 Value of 0x80 indicates invalid. 1602 */ 1603 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 1604 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 1605 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 1606 1607 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 1608 1609 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1610 1611 Value of 0x80 indicates invalid. 1612 */ 1613 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 1614 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 1615 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff 1616 1617 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 1618 1619 RSSI of RX PPDU on chain 5 of extension 20 MHz 1620 bandwidth. 1621 1622 Value of 0x80 indicates invalid. 1623 */ 1624 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 1625 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 1626 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 1627 1628 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 1629 1630 RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz 1631 bandwidth. 1632 1633 Value of 0x80 indicates invalid. 1634 */ 1635 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 1636 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 1637 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 1638 1639 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 1640 1641 RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz 1642 bandwidth. 1643 1644 Value of 0x80 indicates invalid. 1645 */ 1646 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 1647 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 1648 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 1649 1650 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 1651 1652 RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz 1653 bandwidth. 1654 1655 Value of 0x80 indicates invalid. 1656 */ 1657 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 1658 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 1659 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff 1660 1661 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 1662 1663 RSSI of RX PPDU on chain 5 of extension 80, low-high 20 1664 MHz bandwidth. 1665 1666 Value of 0x80 indicates invalid. 1667 */ 1668 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 1669 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 1670 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 1671 1672 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 1673 1674 RSSI of RX PPDU on chain 5 of extension 80, high-low 20 1675 MHz bandwidth. 1676 1677 Value of 0x80 indicates invalid. 1678 */ 1679 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 1680 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 1681 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 1682 1683 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 1684 1685 RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz 1686 bandwidth. 1687 1688 Value of 0x80 indicates invalid. 1689 */ 1690 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 1691 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 1692 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 1693 1694 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 1695 1696 RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. 1697 1698 Value of 0x80 indicates invalid. 1699 */ 1700 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c 1701 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 1702 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff 1703 1704 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 1705 1706 RSSI of RX PPDU on chain 6 of extension 20 MHz 1707 bandwidth. 1708 1709 Value of 0x80 indicates invalid. 1710 */ 1711 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c 1712 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 1713 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 1714 1715 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 1716 1717 RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz 1718 bandwidth. 1719 1720 Value of 0x80 indicates invalid. 1721 */ 1722 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c 1723 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 1724 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 1725 1726 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 1727 1728 RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz 1729 bandwidth. 1730 1731 Value of 0x80 indicates invalid. 1732 */ 1733 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c 1734 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 1735 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 1736 1737 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 1738 1739 RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz 1740 bandwidth. 1741 1742 Value of 0x80 indicates invalid. 1743 */ 1744 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 1745 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 1746 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff 1747 1748 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 1749 1750 RSSI of RX PPDU on chain 6 of extension 80, low-high 20 1751 MHz bandwidth. 1752 1753 Value of 0x80 indicates invalid. 1754 */ 1755 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 1756 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 1757 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 1758 1759 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 1760 1761 RSSI of RX PPDU on chain 6 of extension 80, high-low 20 1762 MHz bandwidth. 1763 1764 Value of 0x80 indicates invalid. 1765 */ 1766 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 1767 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 1768 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 1769 1770 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 1771 1772 RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz 1773 bandwidth. 1774 1775 Value of 0x80 indicates invalid. 1776 */ 1777 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 1778 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 1779 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 1780 1781 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 1782 1783 RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. 1784 1785 Value of 0x80 indicates invalid. 1786 */ 1787 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 1788 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 1789 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff 1790 1791 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 1792 1793 RSSI of RX PPDU on chain 7 of extension 20 MHz 1794 bandwidth. 1795 1796 Value of 0x80 indicates invalid. 1797 */ 1798 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 1799 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 1800 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 1801 1802 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 1803 1804 RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz 1805 bandwidth. 1806 1807 Value of 0x80 indicates invalid. 1808 */ 1809 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 1810 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 1811 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 1812 1813 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 1814 1815 RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz 1816 bandwidth. 1817 1818 Value of 0x80 indicates invalid. 1819 */ 1820 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 1821 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 1822 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 1823 1824 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 1825 1826 RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz 1827 bandwidth. 1828 1829 Value of 0x80 indicates invalid. 1830 */ 1831 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 1832 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 1833 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff 1834 1835 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 1836 1837 RSSI of RX PPDU on chain 7 of extension 80, low-high 20 1838 MHz bandwidth. 1839 1840 Value of 0x80 indicates invalid. 1841 */ 1842 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 1843 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 1844 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 1845 1846 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 1847 1848 RSSI of RX PPDU on chain 7 of extension 80, high-low 20 1849 MHz bandwidth. 1850 1851 Value of 0x80 indicates invalid. 1852 */ 1853 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 1854 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 1855 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 1856 1857 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 1858 1859 RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz 1860 bandwidth. 1861 1862 Value of 0x80 indicates invalid. 1863 */ 1864 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 1865 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 1866 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 1867 1868 /* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 1869 1870 Some PHY micro code status that can be put in here. 1871 Details of definition within SW specification 1872 1873 This field can be used for debugging, FW - SW message 1874 exchange, etc. 1875 1876 It could for example be a pointer to a DDR memory 1877 location where PHY FW put some debug info. 1878 1879 <legal all> 1880 */ 1881 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 1882 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 1883 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 1884 1885 /* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 1886 1887 Some PHY micro code status that can be put in here. 1888 Details of definition within SW specification 1889 1890 This field can be used for debugging, FW - SW message 1891 exchange, etc. 1892 1893 It could for example be a pointer to a DDR memory 1894 location where PHY FW put some debug info. 1895 1896 <legal all> 1897 */ 1898 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 1899 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 1900 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 1901 1902 1903 #endif // _PHYRX_PKT_END_INFO_H_ 1904