1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_ENTRANCE_RING_H_ 25 #define _REO_ENTRANCE_RING_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rx_mpdu_details.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; 35 // 4 rx_reo_queue_desc_addr_31_0[31:0] 36 // 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] 37 // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], sw_exception[11], sw_exception_mpdu_delink[12], sw_exception_destination_ring_valid[13], sw_exception_destination_ring[18:14], reserved_6a[31:19] 38 // 7 phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28] 39 // 40 // ################ END SUMMARY ################# 41 42 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 43 44 struct reo_entrance_ring { 45 struct rx_mpdu_details reo_level_mpdu_frame_info; 46 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 47 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 48 rounded_mpdu_byte_count : 14, //[21:8] 49 reo_destination_indication : 5, //[26:22] 50 frameless_bar : 1, //[27] 51 reserved_5a : 4; //[31:28] 52 uint32_t rxdma_push_reason : 2, //[1:0] 53 rxdma_error_code : 5, //[6:2] 54 mpdu_fragment_number : 4, //[10:7] 55 sw_exception : 1, //[11] 56 sw_exception_mpdu_delink : 1, //[12] 57 sw_exception_destination_ring_valid: 1, //[13] 58 sw_exception_destination_ring : 5, //[18:14] 59 reserved_6a : 13; //[31:19] 60 uint32_t phy_ppdu_id : 16, //[15:0] 61 reserved_7a : 4, //[19:16] 62 ring_id : 8, //[27:20] 63 looping_count : 4; //[31:28] 64 }; 65 66 /* 67 68 struct rx_mpdu_details reo_level_mpdu_frame_info 69 70 Consumer: REO 71 72 Producer: RXDMA 73 74 75 76 Details related to the MPDU being pushed into the REO 77 78 rx_reo_queue_desc_addr_31_0 79 80 Consumer: REO 81 82 Producer: RXDMA 83 84 85 86 Address (lower 32 bits) of the REO queue descriptor. 87 88 <legal all> 89 90 rx_reo_queue_desc_addr_39_32 91 92 Consumer: REO 93 94 Producer: RXDMA 95 96 97 98 Address (upper 8 bits) of the REO queue descriptor. 99 100 <legal all> 101 102 rounded_mpdu_byte_count 103 104 An approximation of the number of bytes received in this 105 MPDU. 106 107 Used to keeps stats on the amount of data flowing 108 through a queue. 109 110 <legal all> 111 112 reo_destination_indication 113 114 RXDMA copy the MPDU's first MSDU's destination 115 indication field here. This is used for REO to be able to 116 re-route the packet to a different SW destination ring if 117 the packet is detected as error in REO. 118 119 120 121 The ID of the REO exit ring where the MSDU frame shall 122 push after (MPDU level) reordering has finished. 123 124 125 126 <enum 0 reo_destination_tcl> Reo will push the frame 127 into the REO2TCL ring 128 129 <enum 1 reo_destination_sw1> Reo will push the frame 130 into the REO2SW1 ring 131 132 <enum 2 reo_destination_sw2> Reo will push the frame 133 into the REO2SW2 ring 134 135 <enum 3 reo_destination_sw3> Reo will push the frame 136 into the REO2SW3 ring 137 138 <enum 4 reo_destination_sw4> Reo will push the frame 139 into the REO2SW4 ring 140 141 <enum 5 reo_destination_release> Reo will push the frame 142 into the REO_release ring 143 144 <enum 6 reo_destination_fw> Reo will push the frame into 145 the REO2FW ring 146 147 <enum 7 reo_destination_sw5> Reo will push the frame 148 into the REO2SW5 ring (REO remaps this in chips without 149 REO2SW5 ring, e.g. Pine) 150 151 <enum 8 reo_destination_sw6> Reo will push the frame 152 into the REO2SW6 ring (REO remaps this in chips without 153 REO2SW6 ring, e.g. Pine) 154 155 <enum 9 reo_destination_9> REO remaps this <enum 10 156 reo_destination_10> REO remaps this 157 158 <enum 11 reo_destination_11> REO remaps this 159 160 <enum 12 reo_destination_12> REO remaps this <enum 13 161 reo_destination_13> REO remaps this 162 163 <enum 14 reo_destination_14> REO remaps this 164 165 <enum 15 reo_destination_15> REO remaps this 166 167 <enum 16 reo_destination_16> REO remaps this 168 169 <enum 17 reo_destination_17> REO remaps this 170 171 <enum 18 reo_destination_18> REO remaps this 172 173 <enum 19 reo_destination_19> REO remaps this 174 175 <enum 20 reo_destination_20> REO remaps this 176 177 <enum 21 reo_destination_21> REO remaps this 178 179 <enum 22 reo_destination_22> REO remaps this 180 181 <enum 23 reo_destination_23> REO remaps this 182 183 <enum 24 reo_destination_24> REO remaps this 184 185 <enum 25 reo_destination_25> REO remaps this 186 187 <enum 26 reo_destination_26> REO remaps this 188 189 <enum 27 reo_destination_27> REO remaps this 190 191 <enum 28 reo_destination_28> REO remaps this 192 193 <enum 29 reo_destination_29> REO remaps this 194 195 <enum 30 reo_destination_30> REO remaps this 196 197 <enum 31 reo_destination_31> REO remaps this 198 199 200 201 <legal all> 202 203 frameless_bar 204 205 When set, this REO entrance ring struct contains BAR 206 info from a multi TID BAR frame. The original multi TID BAR 207 frame itself contained all the REO info for the first TID, 208 but all the subsequent TID info and their linkage to the REO 209 descriptors is passed down as 'frameless' BAR info. 210 211 212 213 The only fields valid in this descriptor when this bit 214 is set are: 215 216 Rx_reo_queue_desc_addr_31_0 217 218 RX_reo_queue_desc_addr_39_32 219 220 221 222 And within the 223 224 Reo_level_mpdu_frame_info: 225 226 Within Rx_mpdu_desc_info_details: 227 228 Mpdu_Sequence_number 229 230 BAR_frame 231 232 Peer_meta_data 233 234 All other fields shall be set to 0 235 236 237 238 <legal all> 239 240 reserved_5a 241 242 <legal 0> 243 244 rxdma_push_reason 245 246 Indicates why rxdma pushed the frame to this ring 247 248 249 250 This field is ignored by REO. 251 252 253 254 <enum 0 rxdma_error_detected> RXDMA detected an error an 255 pushed this frame to this queue 256 257 <enum 1 rxdma_routing_instruction> RXDMA pushed the 258 frame to this queue per received routing instructions. No 259 error within RXDMA was detected 260 261 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 262 result the MSDU link descriptor might not have the 263 last_msdu_in_mpdu_flag set, but instead WBM might just see a 264 NULL pointer in the MSDU link descriptor. This is to be 265 considered a normal condition for this scenario. 266 267 268 269 <legal 0 - 2> 270 271 rxdma_error_code 272 273 Field only valid when 'rxdma_push_reason' set to 274 'rxdma_error_detected'. 275 276 277 278 This field is ignored by REO. 279 280 281 282 <enum 0 rxdma_overflow_err>MPDU frame is not complete 283 due to a FIFO overflow error in RXPCU. 284 285 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 286 due to receiving incomplete MPDU from the PHY 287 288 289 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 290 error or CRYPTO received an encrypted frame, but did not get 291 a valid corresponding key id in the peer entry. 292 293 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 294 error 295 296 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 297 unencrypted frame error when encrypted was expected 298 299 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 300 length error 301 302 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 303 number of MSDUs allowed in an MPDU got exceeded 304 305 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 306 error 307 308 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 309 parsing error 310 311 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 312 during SA search 313 314 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 315 during DA search 316 317 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 318 timeout during flow search 319 320 <enum 13 rxdma_flush_request>RXDMA received a flush 321 request 322 323 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 324 present as well as a fragmented MPDU. A-MSDU defragmentation 325 is not supported in Lithium SW so this is treated as an 326 error. 327 328 mpdu_fragment_number 329 330 Field only valid when Reo_level_mpdu_frame_info. 331 Rx_mpdu_desc_info_details.Fragment_flag is set. 332 333 334 335 The fragment number from the 802.11 header. 336 337 338 339 Note that the sequence number is embedded in the field: 340 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 341 Mpdu_sequence_number 342 343 344 345 <legal all> 346 347 sw_exception 348 349 When not set, REO is performing all its default MPDU 350 processing operations, 351 352 When set, this REO entrance descriptor is generated by 353 FW, and should be processed as an exception. This implies: 354 355 NO re-order function is needed. 356 357 MPDU delinking is determined by the setting of field 358 SW_excection_mpdu_delink 359 360 Destination ring selection is based on the setting of 361 the field SW_exception_destination_ring_valid 362 363 In the destination ring descriptor set bit: 364 SW_exception_entry 365 366 Feature supported only in HastingsPrime 367 368 <legal all> 369 370 sw_exception_mpdu_delink 371 372 Field only valid when SW_exception is set. 373 374 1'b0: REO should NOT delink the MPDU, and thus pass this 375 MPDU on to the destination ring as is. This implies that in 376 the REO_DESTINATION_RING struct field 377 Buf_or_link_desc_addr_info should point to an MSDU link 378 descriptor 379 380 1'b1: REO should perform the normal MPDU delink into 381 MSDU operations. 382 383 Feature supported only in HastingsPrime 384 385 <legal all> 386 387 sw_exception_destination_ring_valid 388 389 Field only valid when SW_exception is set. 390 391 1'b0: REO shall push the MPDU (or delinked MPDU based on 392 the setting of SW_exception_mpdu_delink) to the destination 393 ring according to field reo_destination_indication. 394 395 1'b1: REO shall push the MPDU (or delinked MPDU based on 396 the setting of SW_exception_mpdu_delink) to the destination 397 ring according to field SW_exception_destination_ring. 398 399 Feature supported only in HastingsPrime 400 401 <legal all> 402 403 sw_exception_destination_ring 404 405 Field only valid when fields SW_exception and 406 SW_exception_destination_ring_valid are set. 407 408 The ID of the ring where REO shall push this frame. 409 410 <enum 0 reo_destination_tcl> Reo will push the frame 411 into the REO2TCL ring 412 413 <enum 1 reo_destination_sw1> Reo will push the frame 414 into the REO2SW1 ring 415 416 <enum 2 reo_destination_sw2> Reo will push the frame 417 into the REO2SW1 ring 418 419 <enum 3 reo_destination_sw3> Reo will push the frame 420 into the REO2SW1 ring 421 422 <enum 4 reo_destination_sw4> Reo will push the frame 423 into the REO2SW1 ring 424 425 <enum 5 reo_destination_release> Reo will push the frame 426 into the REO_release ring 427 428 <enum 6 reo_destination_fw> Reo will push the frame into 429 the REO2FW ring 430 431 <enum 7 reo_destination_sw5> REO remaps this 432 433 <enum 8 reo_destination_sw6> REO remaps this 434 435 <enum 9 reo_destination_9> REO remaps this 436 437 <enum 10 reo_destination_10> REO remaps this 438 439 <enum 11 reo_destination_11> REO remaps this 440 441 <enum 12 reo_destination_12> REO remaps this <enum 13 442 reo_destination_13> REO remaps this 443 444 <enum 14 reo_destination_14> REO remaps this 445 446 <enum 15 reo_destination_15> REO remaps this 447 448 <enum 16 reo_destination_16> REO remaps this 449 450 <enum 17 reo_destination_17> REO remaps this 451 452 <enum 18 reo_destination_18> REO remaps this 453 454 <enum 19 reo_destination_19> REO remaps this 455 456 <enum 20 reo_destination_20> REO remaps this 457 458 <enum 21 reo_destination_21> REO remaps this 459 460 <enum 22 reo_destination_22> REO remaps this 461 462 <enum 23 reo_destination_23> REO remaps this 463 464 <enum 24 reo_destination_24> REO remaps this 465 466 <enum 25 reo_destination_25> REO remaps this 467 468 <enum 26 reo_destination_26> REO remaps this 469 470 <enum 27 reo_destination_27> REO remaps this 471 472 <enum 28 reo_destination_28> REO remaps this 473 474 <enum 29 reo_destination_29> REO remaps this 475 476 <enum 30 reo_destination_30> REO remaps this 477 478 <enum 31 reo_destination_31> REO remaps this 479 480 481 482 Feature supported only in HastingsPrime 483 484 <legal all> 485 486 reserved_6a 487 488 <legal 0> 489 490 phy_ppdu_id 491 492 A PPDU counter value that PHY increments for every PPDU 493 received 494 495 The counter value wraps around. Pine RXDMA can be 496 configured to copy this from the RX_PPDU_START TLV for every 497 output descriptor. 498 499 500 501 This field is ignored by REO. 502 503 504 505 Feature supported only in Pine 506 507 <legal all> 508 509 reserved_7a 510 511 <legal 0> 512 513 ring_id 514 515 Consumer: SW/REO/DEBUG 516 517 Producer: SRNG (of RXDMA) 518 519 520 521 For debugging. 522 523 This field is filled in by the SRNG module. 524 525 It help to identify the ring that is being looked <legal 526 all> 527 528 looping_count 529 530 Consumer: SW/REO/DEBUG 531 532 Producer: SRNG (of RXDMA) 533 534 535 536 For debugging. 537 538 This field is filled in by the SRNG module. 539 540 541 542 A count value that indicates the number of times the 543 producer of entries into this Ring has looped around the 544 ring. 545 546 At initialization time, this value is set to 0. On the 547 first loop, this value is set to 1. After the max value is 548 reached allowed by the number of bits for this field, the 549 count value continues with 0 again. 550 551 552 553 In case SW is the consumer of the ring entries, it can 554 use this field to figure out up to where the producer of 555 entries has created new entries. This eliminates the need to 556 check where the head pointer' of the ring is located once 557 the SW starts processing an interrupt indicating that new 558 entries have been put into this ring... 559 560 561 562 Also note that SW if it wants only needs to look at the 563 LSB bit of this count value. 564 565 <legal all> 566 */ 567 568 569 /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ 570 571 572 /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 573 574 575 /* Description REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 576 577 Address (lower 32 bits) of the MSDU buffer OR 578 MSDU_EXTENSION descriptor OR Link Descriptor 579 580 581 582 In case of 'NULL' pointer, this field is set to 0 583 584 <legal all> 585 */ 586 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 587 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 588 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 589 590 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 591 592 Address (upper 8 bits) of the MSDU buffer OR 593 MSDU_EXTENSION descriptor OR Link Descriptor 594 595 596 597 In case of 'NULL' pointer, this field is set to 0 598 599 <legal all> 600 */ 601 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 602 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 603 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 604 605 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 606 607 Consumer: WBM 608 609 Producer: SW/FW 610 611 612 613 In case of 'NULL' pointer, this field is set to 0 614 615 616 617 Indicates to which buffer manager the buffer OR 618 MSDU_EXTENSION descriptor OR link descriptor that is being 619 pointed to shall be returned after the frame has been 620 processed. It is used by WBM for routing purposes. 621 622 623 624 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 625 to the WMB buffer idle list 626 627 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 628 returned to the WMB idle link descriptor idle list 629 630 <enum 2 FW_BM> This buffer shall be returned to the FW 631 632 <enum 3 SW0_BM> This buffer shall be returned to the SW, 633 ring 0 634 635 <enum 4 SW1_BM> This buffer shall be returned to the SW, 636 ring 1 637 638 <enum 5 SW2_BM> This buffer shall be returned to the SW, 639 ring 2 640 641 <enum 6 SW3_BM> This buffer shall be returned to the SW, 642 ring 3 643 644 <enum 7 SW4_BM> This buffer shall be returned to the SW, 645 ring 4 646 647 648 649 <legal all> 650 */ 651 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 652 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 653 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 654 655 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 656 657 Cookie field exclusively used by SW. 658 659 660 661 In case of 'NULL' pointer, this field is set to 0 662 663 664 665 HW ignores the contents, accept that it passes the 666 programmed value on to other descriptors together with the 667 physical address 668 669 670 671 Field can be used by SW to for example associate the 672 buffers physical address with the virtual address 673 674 The bit definitions as used by SW are within SW HLD 675 specification 676 677 678 679 NOTE: 680 681 The three most significant bits can have a special 682 meaning in case this struct is embedded in a TX_MPDU_DETAILS 683 STRUCT, and field transmit_bw_restriction is set 684 685 686 687 In case of NON punctured transmission: 688 689 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 690 691 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 692 693 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 694 695 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 696 697 698 699 In case of punctured transmission: 700 701 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 702 703 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 704 705 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 706 707 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 708 709 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 710 711 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 712 713 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 714 715 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 716 717 718 719 Note: a punctured transmission is indicated by the 720 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 721 TLV 722 723 724 725 <legal all> 726 */ 727 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 728 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 729 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 730 731 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 732 733 734 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 735 736 Consumer: REO/SW/FW 737 738 Producer: RXDMA 739 740 741 742 The number of MSDUs within the MPDU 743 744 <legal all> 745 */ 746 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 747 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 748 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 749 750 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 751 752 Consumer: REO/SW/FW 753 754 Producer: RXDMA 755 756 757 758 The field can have two different meanings based on the 759 setting of field 'BAR_frame': 760 761 762 763 'BAR_frame' is NOT set: 764 765 The MPDU sequence number of the received frame. 766 767 768 769 'BAR_frame' is set. 770 771 The MPDU Start sequence number from the BAR frame 772 773 <legal all> 774 */ 775 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 776 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 777 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 778 779 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 780 781 Consumer: REO/SW/FW 782 783 Producer: RXDMA 784 785 786 787 When set, this MPDU is a fragment and REO should forward 788 this fragment MPDU to the REO destination ring without any 789 reorder checks, pn checks or bitmap update. This implies 790 that REO is forwarding the pointer to the MSDU link 791 descriptor. The destination ring is coming from a 792 programmable register setting in REO 793 794 795 796 <legal all> 797 */ 798 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 799 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 800 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 801 802 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 803 804 Consumer: REO/SW/FW 805 806 Producer: RXDMA 807 808 809 810 The retry bit setting from the MPDU header of the 811 received frame 812 813 <legal all> 814 */ 815 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 816 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 817 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 818 819 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 820 821 Consumer: REO/SW/FW 822 823 Producer: RXDMA 824 825 826 827 When set, the MPDU was received as part of an A-MPDU. 828 829 <legal all> 830 */ 831 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 832 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 833 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 834 835 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 836 837 Consumer: REO/SW/FW 838 839 Producer: RXDMA 840 841 842 843 When set, the received frame is a BAR frame. After 844 processing, this frame shall be pushed to SW or deleted. 845 846 <legal all> 847 */ 848 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 849 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 850 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 851 852 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 853 854 Consumer: REO/SW/FW 855 856 Producer: RXDMA 857 858 859 860 Copied here by RXDMA from RX_MPDU_END 861 862 When not set, REO will Not perform a PN sequence number 863 check 864 */ 865 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 866 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 867 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 868 869 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 870 871 When set, OLE found a valid SA entry for all MSDUs in 872 this MPDU 873 874 <legal all> 875 */ 876 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 877 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 878 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 879 880 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 881 882 When set, at least 1 MSDU within the MPDU has an 883 unsuccessful MAC source address search due to the expiration 884 of the search timer. 885 886 <legal all> 887 */ 888 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 889 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 890 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 891 892 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 893 894 When set, OLE found a valid DA entry for all MSDUs in 895 this MPDU 896 897 <legal all> 898 */ 899 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 900 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 901 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 902 903 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 904 905 Field Only valid if da_is_valid is set 906 907 908 909 When set, at least one of the DA addresses is a 910 Multicast or Broadcast address. 911 912 <legal all> 913 */ 914 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 915 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 916 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 917 918 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 919 920 When set, at least 1 MSDU within the MPDU has an 921 unsuccessful MAC destination address search due to the 922 expiration of the search timer. 923 924 <legal all> 925 */ 926 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 927 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 928 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 929 930 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 931 932 Field only valid when first_msdu_in_mpdu_flag is set. 933 934 935 936 When set, the contents in the MSDU buffer contains a 937 'RAW' MPDU. This 'RAW' MPDU might be spread out over 938 multiple MSDU buffers. 939 940 <legal all> 941 */ 942 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 943 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 944 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 945 946 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 947 948 The More Fragment bit setting from the MPDU header of 949 the received frame 950 951 952 953 <legal all> 954 */ 955 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 956 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 957 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 958 959 /* Description REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 960 961 Meta data that SW has programmed in the Peer table entry 962 of the transmitting STA. 963 964 <legal all> 965 */ 966 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 967 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 968 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 969 970 /* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 971 972 Consumer: REO 973 974 Producer: RXDMA 975 976 977 978 Address (lower 32 bits) of the REO queue descriptor. 979 980 <legal all> 981 */ 982 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 983 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 984 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 985 986 /* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 987 988 Consumer: REO 989 990 Producer: RXDMA 991 992 993 994 Address (upper 8 bits) of the REO queue descriptor. 995 996 <legal all> 997 */ 998 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 999 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1000 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1001 1002 /* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT 1003 1004 An approximation of the number of bytes received in this 1005 MPDU. 1006 1007 Used to keeps stats on the amount of data flowing 1008 through a queue. 1009 1010 <legal all> 1011 */ 1012 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 1013 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 1014 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 1015 1016 /* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION 1017 1018 RXDMA copy the MPDU's first MSDU's destination 1019 indication field here. This is used for REO to be able to 1020 re-route the packet to a different SW destination ring if 1021 the packet is detected as error in REO. 1022 1023 1024 1025 The ID of the REO exit ring where the MSDU frame shall 1026 push after (MPDU level) reordering has finished. 1027 1028 1029 1030 <enum 0 reo_destination_tcl> Reo will push the frame 1031 into the REO2TCL ring 1032 1033 <enum 1 reo_destination_sw1> Reo will push the frame 1034 into the REO2SW1 ring 1035 1036 <enum 2 reo_destination_sw2> Reo will push the frame 1037 into the REO2SW2 ring 1038 1039 <enum 3 reo_destination_sw3> Reo will push the frame 1040 into the REO2SW3 ring 1041 1042 <enum 4 reo_destination_sw4> Reo will push the frame 1043 into the REO2SW4 ring 1044 1045 <enum 5 reo_destination_release> Reo will push the frame 1046 into the REO_release ring 1047 1048 <enum 6 reo_destination_fw> Reo will push the frame into 1049 the REO2FW ring 1050 1051 <enum 7 reo_destination_sw5> Reo will push the frame 1052 into the REO2SW5 ring (REO remaps this in chips without 1053 REO2SW5 ring, e.g. Pine) 1054 1055 <enum 8 reo_destination_sw6> Reo will push the frame 1056 into the REO2SW6 ring (REO remaps this in chips without 1057 REO2SW6 ring, e.g. Pine) 1058 1059 <enum 9 reo_destination_9> REO remaps this <enum 10 1060 reo_destination_10> REO remaps this 1061 1062 <enum 11 reo_destination_11> REO remaps this 1063 1064 <enum 12 reo_destination_12> REO remaps this <enum 13 1065 reo_destination_13> REO remaps this 1066 1067 <enum 14 reo_destination_14> REO remaps this 1068 1069 <enum 15 reo_destination_15> REO remaps this 1070 1071 <enum 16 reo_destination_16> REO remaps this 1072 1073 <enum 17 reo_destination_17> REO remaps this 1074 1075 <enum 18 reo_destination_18> REO remaps this 1076 1077 <enum 19 reo_destination_19> REO remaps this 1078 1079 <enum 20 reo_destination_20> REO remaps this 1080 1081 <enum 21 reo_destination_21> REO remaps this 1082 1083 <enum 22 reo_destination_22> REO remaps this 1084 1085 <enum 23 reo_destination_23> REO remaps this 1086 1087 <enum 24 reo_destination_24> REO remaps this 1088 1089 <enum 25 reo_destination_25> REO remaps this 1090 1091 <enum 26 reo_destination_26> REO remaps this 1092 1093 <enum 27 reo_destination_27> REO remaps this 1094 1095 <enum 28 reo_destination_28> REO remaps this 1096 1097 <enum 29 reo_destination_29> REO remaps this 1098 1099 <enum 30 reo_destination_30> REO remaps this 1100 1101 <enum 31 reo_destination_31> REO remaps this 1102 1103 1104 1105 <legal all> 1106 */ 1107 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 1108 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 1109 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 1110 1111 /* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR 1112 1113 When set, this REO entrance ring struct contains BAR 1114 info from a multi TID BAR frame. The original multi TID BAR 1115 frame itself contained all the REO info for the first TID, 1116 but all the subsequent TID info and their linkage to the REO 1117 descriptors is passed down as 'frameless' BAR info. 1118 1119 1120 1121 The only fields valid in this descriptor when this bit 1122 is set are: 1123 1124 Rx_reo_queue_desc_addr_31_0 1125 1126 RX_reo_queue_desc_addr_39_32 1127 1128 1129 1130 And within the 1131 1132 Reo_level_mpdu_frame_info: 1133 1134 Within Rx_mpdu_desc_info_details: 1135 1136 Mpdu_Sequence_number 1137 1138 BAR_frame 1139 1140 Peer_meta_data 1141 1142 All other fields shall be set to 0 1143 1144 1145 1146 <legal all> 1147 */ 1148 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 1149 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 1150 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 1151 1152 /* Description REO_ENTRANCE_RING_5_RESERVED_5A 1153 1154 <legal 0> 1155 */ 1156 #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 1157 #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 1158 #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 1159 1160 /* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON 1161 1162 Indicates why rxdma pushed the frame to this ring 1163 1164 1165 1166 This field is ignored by REO. 1167 1168 1169 1170 <enum 0 rxdma_error_detected> RXDMA detected an error an 1171 pushed this frame to this queue 1172 1173 <enum 1 rxdma_routing_instruction> RXDMA pushed the 1174 frame to this queue per received routing instructions. No 1175 error within RXDMA was detected 1176 1177 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 1178 result the MSDU link descriptor might not have the 1179 last_msdu_in_mpdu_flag set, but instead WBM might just see a 1180 NULL pointer in the MSDU link descriptor. This is to be 1181 considered a normal condition for this scenario. 1182 1183 1184 1185 <legal 0 - 2> 1186 */ 1187 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 1188 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 1189 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 1190 1191 /* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE 1192 1193 Field only valid when 'rxdma_push_reason' set to 1194 'rxdma_error_detected'. 1195 1196 1197 1198 This field is ignored by REO. 1199 1200 1201 1202 <enum 0 rxdma_overflow_err>MPDU frame is not complete 1203 due to a FIFO overflow error in RXPCU. 1204 1205 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 1206 due to receiving incomplete MPDU from the PHY 1207 1208 1209 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 1210 error or CRYPTO received an encrypted frame, but did not get 1211 a valid corresponding key id in the peer entry. 1212 1213 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 1214 error 1215 1216 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 1217 unencrypted frame error when encrypted was expected 1218 1219 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 1220 length error 1221 1222 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 1223 number of MSDUs allowed in an MPDU got exceeded 1224 1225 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 1226 error 1227 1228 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 1229 parsing error 1230 1231 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 1232 during SA search 1233 1234 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 1235 during DA search 1236 1237 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 1238 timeout during flow search 1239 1240 <enum 13 rxdma_flush_request>RXDMA received a flush 1241 request 1242 1243 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 1244 present as well as a fragmented MPDU. A-MSDU defragmentation 1245 is not supported in Lithium SW so this is treated as an 1246 error. 1247 */ 1248 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 1249 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 1250 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c 1251 1252 /* Description REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER 1253 1254 Field only valid when Reo_level_mpdu_frame_info. 1255 Rx_mpdu_desc_info_details.Fragment_flag is set. 1256 1257 1258 1259 The fragment number from the 802.11 header. 1260 1261 1262 1263 Note that the sequence number is embedded in the field: 1264 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 1265 Mpdu_sequence_number 1266 1267 1268 1269 <legal all> 1270 */ 1271 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 1272 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 1273 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 1274 1275 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION 1276 1277 When not set, REO is performing all its default MPDU 1278 processing operations, 1279 1280 When set, this REO entrance descriptor is generated by 1281 FW, and should be processed as an exception. This implies: 1282 1283 NO re-order function is needed. 1284 1285 MPDU delinking is determined by the setting of field 1286 SW_excection_mpdu_delink 1287 1288 Destination ring selection is based on the setting of 1289 the field SW_exception_destination_ring_valid 1290 1291 In the destination ring descriptor set bit: 1292 SW_exception_entry 1293 1294 Feature supported only in HastingsPrime 1295 1296 <legal all> 1297 */ 1298 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018 1299 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11 1300 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800 1301 1302 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK 1303 1304 Field only valid when SW_exception is set. 1305 1306 1'b0: REO should NOT delink the MPDU, and thus pass this 1307 MPDU on to the destination ring as is. This implies that in 1308 the REO_DESTINATION_RING struct field 1309 Buf_or_link_desc_addr_info should point to an MSDU link 1310 descriptor 1311 1312 1'b1: REO should perform the normal MPDU delink into 1313 MSDU operations. 1314 1315 Feature supported only in HastingsPrime 1316 1317 <legal all> 1318 */ 1319 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 1320 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12 1321 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 1322 1323 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID 1324 1325 Field only valid when SW_exception is set. 1326 1327 1'b0: REO shall push the MPDU (or delinked MPDU based on 1328 the setting of SW_exception_mpdu_delink) to the destination 1329 ring according to field reo_destination_indication. 1330 1331 1'b1: REO shall push the MPDU (or delinked MPDU based on 1332 the setting of SW_exception_mpdu_delink) to the destination 1333 ring according to field SW_exception_destination_ring. 1334 1335 Feature supported only in HastingsPrime 1336 1337 <legal all> 1338 */ 1339 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 1340 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 1341 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 1342 1343 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING 1344 1345 Field only valid when fields SW_exception and 1346 SW_exception_destination_ring_valid are set. 1347 1348 The ID of the ring where REO shall push this frame. 1349 1350 <enum 0 reo_destination_tcl> Reo will push the frame 1351 into the REO2TCL ring 1352 1353 <enum 1 reo_destination_sw1> Reo will push the frame 1354 into the REO2SW1 ring 1355 1356 <enum 2 reo_destination_sw2> Reo will push the frame 1357 into the REO2SW1 ring 1358 1359 <enum 3 reo_destination_sw3> Reo will push the frame 1360 into the REO2SW1 ring 1361 1362 <enum 4 reo_destination_sw4> Reo will push the frame 1363 into the REO2SW1 ring 1364 1365 <enum 5 reo_destination_release> Reo will push the frame 1366 into the REO_release ring 1367 1368 <enum 6 reo_destination_fw> Reo will push the frame into 1369 the REO2FW ring 1370 1371 <enum 7 reo_destination_sw5> REO remaps this 1372 1373 <enum 8 reo_destination_sw6> REO remaps this 1374 1375 <enum 9 reo_destination_9> REO remaps this 1376 1377 <enum 10 reo_destination_10> REO remaps this 1378 1379 <enum 11 reo_destination_11> REO remaps this 1380 1381 <enum 12 reo_destination_12> REO remaps this <enum 13 1382 reo_destination_13> REO remaps this 1383 1384 <enum 14 reo_destination_14> REO remaps this 1385 1386 <enum 15 reo_destination_15> REO remaps this 1387 1388 <enum 16 reo_destination_16> REO remaps this 1389 1390 <enum 17 reo_destination_17> REO remaps this 1391 1392 <enum 18 reo_destination_18> REO remaps this 1393 1394 <enum 19 reo_destination_19> REO remaps this 1395 1396 <enum 20 reo_destination_20> REO remaps this 1397 1398 <enum 21 reo_destination_21> REO remaps this 1399 1400 <enum 22 reo_destination_22> REO remaps this 1401 1402 <enum 23 reo_destination_23> REO remaps this 1403 1404 <enum 24 reo_destination_24> REO remaps this 1405 1406 <enum 25 reo_destination_25> REO remaps this 1407 1408 <enum 26 reo_destination_26> REO remaps this 1409 1410 <enum 27 reo_destination_27> REO remaps this 1411 1412 <enum 28 reo_destination_28> REO remaps this 1413 1414 <enum 29 reo_destination_29> REO remaps this 1415 1416 <enum 30 reo_destination_30> REO remaps this 1417 1418 <enum 31 reo_destination_31> REO remaps this 1419 1420 1421 1422 Feature supported only in HastingsPrime 1423 1424 <legal all> 1425 */ 1426 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 1427 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14 1428 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 1429 1430 /* Description REO_ENTRANCE_RING_6_RESERVED_6A 1431 1432 <legal 0> 1433 */ 1434 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 1435 #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19 1436 #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000 1437 1438 /* Description REO_ENTRANCE_RING_7_PHY_PPDU_ID 1439 1440 A PPDU counter value that PHY increments for every PPDU 1441 received 1442 1443 The counter value wraps around. Pine RXDMA can be 1444 configured to copy this from the RX_PPDU_START TLV for every 1445 output descriptor. 1446 1447 1448 1449 This field is ignored by REO. 1450 1451 1452 1453 Feature supported only in Pine 1454 1455 <legal all> 1456 */ 1457 #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c 1458 #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0 1459 #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff 1460 1461 /* Description REO_ENTRANCE_RING_7_RESERVED_7A 1462 1463 <legal 0> 1464 */ 1465 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c 1466 #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16 1467 #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000 1468 1469 /* Description REO_ENTRANCE_RING_7_RING_ID 1470 1471 Consumer: SW/REO/DEBUG 1472 1473 Producer: SRNG (of RXDMA) 1474 1475 1476 1477 For debugging. 1478 1479 This field is filled in by the SRNG module. 1480 1481 It help to identify the ring that is being looked <legal 1482 all> 1483 */ 1484 #define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c 1485 #define REO_ENTRANCE_RING_7_RING_ID_LSB 20 1486 #define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 1487 1488 /* Description REO_ENTRANCE_RING_7_LOOPING_COUNT 1489 1490 Consumer: SW/REO/DEBUG 1491 1492 Producer: SRNG (of RXDMA) 1493 1494 1495 1496 For debugging. 1497 1498 This field is filled in by the SRNG module. 1499 1500 1501 1502 A count value that indicates the number of times the 1503 producer of entries into this Ring has looped around the 1504 ring. 1505 1506 At initialization time, this value is set to 0. On the 1507 first loop, this value is set to 1. After the max value is 1508 reached allowed by the number of bits for this field, the 1509 count value continues with 0 again. 1510 1511 1512 1513 In case SW is the consumer of the ring entries, it can 1514 use this field to figure out up to where the producer of 1515 entries has created new entries. This eliminates the need to 1516 check where the head pointer' of the ring is located once 1517 the SW starts processing an interrupt indicating that new 1518 entries have been put into this ring... 1519 1520 1521 1522 Also note that SW if it wants only needs to look at the 1523 LSB bit of this count value. 1524 1525 <legal all> 1526 */ 1527 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 1528 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 1529 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 1530 1531 1532 #endif // _REO_ENTRANCE_RING_H_ 1533