1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_FLUSH_QUEUE_H_ 25 #define _REO_FLUSH_QUEUE_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_reo_cmd_header.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct uniform_reo_cmd_header cmd_header; 35 // 1 flush_desc_addr_31_0[31:0] 36 // 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], invalidate_queue_and_flush[11], reserved_2a[31:12] 37 // 3 reserved_3a[31:0] 38 // 4 reserved_4a[31:0] 39 // 5 reserved_5a[31:0] 40 // 6 reserved_6a[31:0] 41 // 7 reserved_7a[31:0] 42 // 8 reserved_8a[31:0] 43 // 44 // ################ END SUMMARY ################# 45 46 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 47 48 struct reo_flush_queue { 49 struct uniform_reo_cmd_header cmd_header; 50 uint32_t flush_desc_addr_31_0 : 32; //[31:0] 51 uint32_t flush_desc_addr_39_32 : 8, //[7:0] 52 block_desc_addr_usage_after_flush: 1, //[8] 53 block_resource_index : 2, //[10:9] 54 invalidate_queue_and_flush : 1, //[11] 55 reserved_2a : 20; //[31:12] 56 uint32_t reserved_3a : 32; //[31:0] 57 uint32_t reserved_4a : 32; //[31:0] 58 uint32_t reserved_5a : 32; //[31:0] 59 uint32_t reserved_6a : 32; //[31:0] 60 uint32_t reserved_7a : 32; //[31:0] 61 uint32_t reserved_8a : 32; //[31:0] 62 }; 63 64 /* 65 66 struct uniform_reo_cmd_header cmd_header 67 68 Consumer: REO 69 70 Producer: SW 71 72 73 74 Details for command execution tracking purposes. 75 76 flush_desc_addr_31_0 77 78 Consumer: REO 79 80 Producer: SW 81 82 83 84 Address (lower 32 bits) of the descriptor to flush 85 86 <legal all> 87 88 flush_desc_addr_39_32 89 90 Consumer: REO 91 92 Producer: SW 93 94 95 96 Address (upper 8 bits) of the descriptor to flush 97 98 <legal all> 99 100 block_desc_addr_usage_after_flush 101 102 When set, REO shall not re-fetch this address till SW 103 explicitly unblocked this address 104 105 106 107 If the blocking resource was already used, this command 108 shall fail and an error is reported 109 110 111 112 <legal all> 113 114 block_resource_index 115 116 Field only valid when 'Block_desc_addr_usage_after_flush 117 ' is set. 118 119 120 121 Indicates which of the four blocking resources in REO 122 will be assigned for managing the blocking of this address. 123 124 <legal all> 125 126 invalidate_queue_and_flush 127 128 When set, after the queue has been completely flushed, 129 invalidate the queue by clearing VLD and flush the queue 130 descriptor from the cache. 131 132 133 134 <legal all> 135 136 reserved_2a 137 138 <legal 0> 139 140 reserved_3a 141 142 <legal 0> 143 144 reserved_4a 145 146 <legal 0> 147 148 reserved_5a 149 150 <legal 0> 151 152 reserved_6a 153 154 <legal 0> 155 156 reserved_7a 157 158 <legal 0> 159 160 reserved_8a 161 162 <legal 0> 163 */ 164 165 166 /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ 167 168 169 /* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER 170 171 Consumer: REO/SW/DEBUG 172 173 Producer: SW 174 175 176 177 This number can be used by SW to track, identify and 178 link the created commands with the command statusses 179 180 181 182 183 184 <legal all> 185 */ 186 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 187 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 188 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 189 190 /* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED 191 192 Consumer: REO 193 194 Producer: SW 195 196 197 198 <enum 0 NoStatus> REO does not need to generate a status 199 TLV for the execution of this command 200 201 <enum 1 StatusRequired> REO shall generate a status TLV 202 for the execution of this command 203 204 205 206 <legal all> 207 */ 208 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 209 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 210 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 211 212 /* Description REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A 213 214 <legal 0> 215 */ 216 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 217 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 218 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 219 220 /* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0 221 222 Consumer: REO 223 224 Producer: SW 225 226 227 228 Address (lower 32 bits) of the descriptor to flush 229 230 <legal all> 231 */ 232 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 233 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0 234 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff 235 236 /* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32 237 238 Consumer: REO 239 240 Producer: SW 241 242 243 244 Address (upper 8 bits) of the descriptor to flush 245 246 <legal all> 247 */ 248 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 249 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0 250 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff 251 252 /* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH 253 254 When set, REO shall not re-fetch this address till SW 255 explicitly unblocked this address 256 257 258 259 If the blocking resource was already used, this command 260 shall fail and an error is reported 261 262 263 264 <legal all> 265 */ 266 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 267 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 268 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 269 270 /* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX 271 272 Field only valid when 'Block_desc_addr_usage_after_flush 273 ' is set. 274 275 276 277 Indicates which of the four blocking resources in REO 278 will be assigned for managing the blocking of this address. 279 280 <legal all> 281 */ 282 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 283 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9 284 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600 285 286 /* Description REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH 287 288 When set, after the queue has been completely flushed, 289 invalidate the queue by clearing VLD and flush the queue 290 descriptor from the cache. 291 292 293 294 <legal all> 295 */ 296 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008 297 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11 298 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800 299 300 /* Description REO_FLUSH_QUEUE_2_RESERVED_2A 301 302 <legal 0> 303 */ 304 #define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008 305 #define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12 306 #define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000 307 308 /* Description REO_FLUSH_QUEUE_3_RESERVED_3A 309 310 <legal 0> 311 */ 312 #define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 313 #define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0 314 #define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff 315 316 /* Description REO_FLUSH_QUEUE_4_RESERVED_4A 317 318 <legal 0> 319 */ 320 #define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 321 #define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0 322 #define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff 323 324 /* Description REO_FLUSH_QUEUE_5_RESERVED_5A 325 326 <legal 0> 327 */ 328 #define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014 329 #define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0 330 #define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff 331 332 /* Description REO_FLUSH_QUEUE_6_RESERVED_6A 333 334 <legal 0> 335 */ 336 #define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018 337 #define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0 338 #define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff 339 340 /* Description REO_FLUSH_QUEUE_7_RESERVED_7A 341 342 <legal 0> 343 */ 344 #define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c 345 #define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0 346 #define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff 347 348 /* Description REO_FLUSH_QUEUE_8_RESERVED_8A 349 350 <legal 0> 351 */ 352 #define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020 353 #define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0 354 #define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff 355 356 357 #endif // _REO_FLUSH_QUEUE_H_ 358