1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _REO_UPDATE_RX_REO_QUEUE_H_ 25 #define _REO_UPDATE_RX_REO_QUEUE_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_reo_cmd_header.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct uniform_reo_cmd_header cmd_header; 35 // 1 rx_reo_queue_desc_addr_31_0[31:0] 36 // 2 rx_reo_queue_desc_addr_39_32[7:0], update_receive_queue_number[8], update_vld[9], update_associated_link_descriptor_counter[10], update_disable_duplicate_detection[11], update_soft_reorder_enable[12], update_ac[13], update_bar[14], update_rty[15], update_chk_2k_mode[16], update_oor_mode[17], update_ba_window_size[18], update_pn_check_needed[19], update_pn_shall_be_even[20], update_pn_shall_be_uneven[21], update_pn_handling_enable[22], update_pn_size[23], update_ignore_ampdu_flag[24], update_svld[25], update_ssn[26], update_seq_2k_error_detected_flag[27], update_pn_error_detected_flag[28], update_pn_valid[29], update_pn[30], clear_stat_counters[31] 37 // 3 receive_queue_number[15:0], vld[16], associated_link_descriptor_counter[18:17], disable_duplicate_detection[19], soft_reorder_enable[20], ac[22:21], bar[23], rty[24], chk_2k_mode[25], oor_mode[26], pn_check_needed[27], pn_shall_be_even[28], pn_shall_be_uneven[29], pn_handling_enable[30], ignore_ampdu_flag[31] 38 // 4 ba_window_size[7:0], pn_size[9:8], svld[10], ssn[22:11], seq_2k_error_detected_flag[23], pn_error_detected_flag[24], pn_valid[25], flush_from_cache[26], reserved_4a[31:27] 39 // 5 pn_31_0[31:0] 40 // 6 pn_63_32[31:0] 41 // 7 pn_95_64[31:0] 42 // 8 pn_127_96[31:0] 43 // 44 // ################ END SUMMARY ################# 45 46 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 47 48 struct reo_update_rx_reo_queue { 49 struct uniform_reo_cmd_header cmd_header; 50 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 51 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 52 update_receive_queue_number : 1, //[8] 53 update_vld : 1, //[9] 54 update_associated_link_descriptor_counter: 1, //[10] 55 update_disable_duplicate_detection: 1, //[11] 56 update_soft_reorder_enable : 1, //[12] 57 update_ac : 1, //[13] 58 update_bar : 1, //[14] 59 update_rty : 1, //[15] 60 update_chk_2k_mode : 1, //[16] 61 update_oor_mode : 1, //[17] 62 update_ba_window_size : 1, //[18] 63 update_pn_check_needed : 1, //[19] 64 update_pn_shall_be_even : 1, //[20] 65 update_pn_shall_be_uneven : 1, //[21] 66 update_pn_handling_enable : 1, //[22] 67 update_pn_size : 1, //[23] 68 update_ignore_ampdu_flag : 1, //[24] 69 update_svld : 1, //[25] 70 update_ssn : 1, //[26] 71 update_seq_2k_error_detected_flag: 1, //[27] 72 update_pn_error_detected_flag : 1, //[28] 73 update_pn_valid : 1, //[29] 74 update_pn : 1, //[30] 75 clear_stat_counters : 1; //[31] 76 uint32_t receive_queue_number : 16, //[15:0] 77 vld : 1, //[16] 78 associated_link_descriptor_counter: 2, //[18:17] 79 disable_duplicate_detection : 1, //[19] 80 soft_reorder_enable : 1, //[20] 81 ac : 2, //[22:21] 82 bar : 1, //[23] 83 rty : 1, //[24] 84 chk_2k_mode : 1, //[25] 85 oor_mode : 1, //[26] 86 pn_check_needed : 1, //[27] 87 pn_shall_be_even : 1, //[28] 88 pn_shall_be_uneven : 1, //[29] 89 pn_handling_enable : 1, //[30] 90 ignore_ampdu_flag : 1; //[31] 91 uint32_t ba_window_size : 8, //[7:0] 92 pn_size : 2, //[9:8] 93 svld : 1, //[10] 94 ssn : 12, //[22:11] 95 seq_2k_error_detected_flag : 1, //[23] 96 pn_error_detected_flag : 1, //[24] 97 pn_valid : 1, //[25] 98 flush_from_cache : 1, //[26] 99 reserved_4a : 5; //[31:27] 100 uint32_t pn_31_0 : 32; //[31:0] 101 uint32_t pn_63_32 : 32; //[31:0] 102 uint32_t pn_95_64 : 32; //[31:0] 103 uint32_t pn_127_96 : 32; //[31:0] 104 }; 105 106 /* 107 108 struct uniform_reo_cmd_header cmd_header 109 110 Consumer: REO 111 112 Producer: SW 113 114 115 116 Details for command execution tracking purposes. 117 118 rx_reo_queue_desc_addr_31_0 119 120 Consumer: REO 121 122 Producer: SW 123 124 125 126 Address (lower 32 bits) of the REO queue descriptor 127 128 <legal all> 129 130 rx_reo_queue_desc_addr_39_32 131 132 Consumer: REO 133 134 Producer: SW 135 136 137 138 Address (upper 8 bits) of the REO queue descriptor 139 140 <legal all> 141 142 update_receive_queue_number 143 144 Consumer: REO 145 146 Producer: SW 147 148 When set, receive_queue_number from this command will be 149 updated in the descriptor. 150 151 <legal all> 152 153 update_vld 154 155 Consumer: REO 156 157 Producer: SW 158 159 160 161 When clear, REO will NOT update the VLD bit setting. For 162 this setting, SW MUST set the Flush_from_cache bit in this 163 command. 164 165 166 167 When set, VLD from this command will be updated in the 168 descriptor. 169 170 <legal all> 171 172 update_associated_link_descriptor_counter 173 174 Consumer: REO 175 176 Producer: SW 177 178 When set, Associated_link_descriptor_counter from this 179 command will be updated in the descriptor. 180 181 <legal all> 182 183 update_disable_duplicate_detection 184 185 Consumer: REO 186 187 Producer: SW 188 189 When set, Disable_duplicate_detection from this command 190 will be updated in the descriptor. 191 192 <legal all> 193 194 update_soft_reorder_enable 195 196 Consumer: REO 197 198 Producer: SW 199 200 When set, Soft_reorder_enable from this command will be 201 updated in the descriptor. 202 203 <legal all> 204 205 update_ac 206 207 Consumer: REO 208 209 Producer: SW 210 211 When set, AC from this command will be updated in the 212 descriptor. 213 214 <legal all> 215 216 update_bar 217 218 Consumer: REO 219 220 Producer: SW 221 222 When set, BAR from this command will be updated in the 223 descriptor. 224 225 <legal all> 226 227 update_rty 228 229 Consumer: REO 230 231 Producer: SW 232 233 When set, RTY from this command will be updated in the 234 descriptor. 235 236 <legal all> 237 238 update_chk_2k_mode 239 240 Consumer: REO 241 242 Producer: SW 243 244 When set, Chk_2k_mode from this command will be updated 245 in the descriptor. 246 247 <legal all> 248 249 update_oor_mode 250 251 Consumer: REO 252 253 Producer: SW 254 255 When set, OOR_Mode from this command will be updated in 256 the descriptor. 257 258 <legal all> 259 260 update_ba_window_size 261 262 Consumer: REO 263 264 Producer: SW 265 266 When set, BA_window_size from this command will be 267 updated in the descriptor. 268 269 <legal all> 270 271 update_pn_check_needed 272 273 Consumer: REO 274 275 Producer: SW 276 277 When set, Pn_check_needed from this command will be 278 updated in the descriptor. 279 280 <legal all> 281 282 update_pn_shall_be_even 283 284 Consumer: REO 285 286 Producer: SW 287 288 When set, Pn_shall_be_even from this command will be 289 updated in the descriptor. 290 291 <legal all> 292 293 update_pn_shall_be_uneven 294 295 Consumer: REO 296 297 Producer: SW 298 299 When set, Pn_shall_be_uneven from this command will be 300 updated in the descriptor. 301 302 <legal all> 303 304 update_pn_handling_enable 305 306 Consumer: REO 307 308 Producer: SW 309 310 When set, Pn_handling_enable from this command will be 311 updated in the descriptor. 312 313 <legal all> 314 315 update_pn_size 316 317 Consumer: REO 318 319 Producer: SW 320 321 When set, Pn_size from this command will be updated in 322 the descriptor. 323 324 <legal all> 325 326 update_ignore_ampdu_flag 327 328 Consumer: REO 329 330 Producer: SW 331 332 When set, Ignore_ampdu_flag from this command will be 333 updated in the descriptor. 334 335 <legal all> 336 337 update_svld 338 339 Consumer: REO 340 341 Producer: SW 342 343 When set, Svld from this command will be updated in the 344 descriptor. 345 346 <legal all> 347 348 update_ssn 349 350 Consumer: REO 351 352 Producer: SW 353 354 When set, SSN from this command will be updated in the 355 descriptor. 356 357 <legal all> 358 359 update_seq_2k_error_detected_flag 360 361 Consumer: REO 362 363 Producer: SW 364 365 When set, Seq_2k_error_detected_flag from this command 366 will be updated in the descriptor. 367 368 <legal all> 369 370 update_pn_error_detected_flag 371 372 Consumer: REO 373 374 Producer: SW 375 376 When set, pn_error_detected_flag from this command will 377 be updated in the descriptor. 378 379 <legal all> 380 381 update_pn_valid 382 383 Consumer: REO 384 385 Producer: SW 386 387 When set, pn_valid from this command will be updated in 388 the descriptor. 389 390 <legal all> 391 392 update_pn 393 394 Consumer: REO 395 396 Producer: SW 397 398 When set, all pn_... fields from this command will be 399 updated in the descriptor. 400 401 <legal all> 402 403 clear_stat_counters 404 405 Consumer: REO 406 407 Producer: SW 408 409 When set, REO will clear (=> set to 0) the following 410 stat counters in the REO_QUEUE_STRUCT 411 412 413 414 Last_rx_enqueue_TimeStamp 415 416 Last_rx_dequeue_Timestamp 417 418 Rx_bitmap (not a counter, but bitmap is cleared) 419 420 Timeout_count 421 422 Forward_due_to_bar_count 423 424 Duplicate_count 425 426 Frames_in_order_count 427 428 BAR_received_count 429 430 MPDU_Frames_processed_count 431 432 MSDU_Frames_processed_count 433 434 Total_processed_byte_count 435 436 Late_receive_MPDU_count 437 438 window_jump_2k 439 440 Hole_count 441 442 443 444 <legal all> 445 446 receive_queue_number 447 448 449 450 451 Field value to be copied over into the RX_REO_QUEUE 452 descriptor. 453 454 <legal all> 455 456 vld 457 458 Field only valid when Update_VLD is set 459 460 461 462 For Update_VLD set and VLD clear, SW MUST set the 463 Flush_from_cache bit in this command. 464 465 466 467 Field value to be copied over into the RX_REO_QUEUE 468 descriptor. 469 470 <legal all> 471 472 associated_link_descriptor_counter 473 474 Field only valid when 475 Update_Associated_link_descriptor_counter is set 476 477 478 479 Field value to be copied over into the RX_REO_QUEUE 480 descriptor. 481 482 <legal all> 483 484 disable_duplicate_detection 485 486 Field only valid when Update_Disable_duplicate_detection 487 is set 488 489 490 491 Field value to be copied over into the RX_REO_QUEUE 492 descriptor. 493 494 <legal all> 495 496 soft_reorder_enable 497 498 Field only valid when Update_Soft_reorder_enable is set 499 500 501 502 Field value to be copied over into the RX_REO_QUEUE 503 descriptor. 504 505 <legal all> 506 507 ac 508 509 Field only valid when Update_AC is set 510 511 512 513 Field value to be copied over into the RX_REO_QUEUE 514 descriptor. 515 516 <legal all> 517 518 bar 519 520 Field only valid when Update_BAR is set 521 522 523 524 Field value to be copied over into the RX_REO_QUEUE 525 descriptor. 526 527 <legal all> 528 529 rty 530 531 Field only valid when Update_RTY is set 532 533 534 535 Field value to be copied over into the RX_REO_QUEUE 536 descriptor. 537 538 <legal all> 539 540 chk_2k_mode 541 542 Field only valid when Update_Chk_2k_Mode is set 543 544 545 546 Field value to be copied over into the RX_REO_QUEUE 547 descriptor. 548 549 <legal all> 550 551 oor_mode 552 553 Field only valid when Update_OOR_Mode is set 554 555 556 557 Field value to be copied over into the RX_REO_QUEUE 558 descriptor. 559 560 <legal all> 561 562 pn_check_needed 563 564 Field only valid when Update_Pn_check_needed is set 565 566 567 568 Field value to be copied over into the RX_REO_QUEUE 569 descriptor. 570 571 <legal all> 572 573 pn_shall_be_even 574 575 Field only valid when Update_Pn_shall_be_even is set 576 577 578 579 Field value to be copied over into the RX_REO_QUEUE 580 descriptor. 581 582 <legal all> 583 584 pn_shall_be_uneven 585 586 Field only valid when Update_Pn_shall_be_uneven is set 587 588 589 590 Field value to be copied over into the RX_REO_QUEUE 591 descriptor. 592 593 <legal all> 594 595 pn_handling_enable 596 597 Field only valid when Update_Pn_handling_enable is set 598 599 600 601 Field value to be copied over into the RX_REO_QUEUE 602 descriptor. 603 604 <legal all> 605 606 ignore_ampdu_flag 607 608 Field only valid when Update_Ignore_ampdu_flag is set 609 610 611 612 Field value to be copied over into the RX_REO_QUEUE 613 descriptor. 614 615 <legal all> 616 617 ba_window_size 618 619 Field only valid when Update_BA_window_size is set 620 621 622 623 Field value to be copied over into the RX_REO_QUEUE 624 descriptor. 625 626 <legal all> 627 628 pn_size 629 630 Field only valid when Update_Pn_size is set 631 632 633 634 Field value to be copied over into the RX_REO_QUEUE 635 descriptor. 636 637 638 639 <enum 0 pn_size_24> 640 641 <enum 1 pn_size_48> 642 643 <enum 2 pn_size_128> 644 645 646 647 <legal 0-2> 648 649 svld 650 651 Field only valid when Update_Svld is set 652 653 654 655 Field value to be copied over into the RX_REO_QUEUE 656 descriptor. 657 658 <legal all> 659 660 ssn 661 662 Field only valid when Update_SSN is set 663 664 665 666 Field value to be copied over into the RX_REO_QUEUE 667 descriptor. 668 669 <legal all> 670 671 seq_2k_error_detected_flag 672 673 Field only valid when Update_Seq_2k_error_detected_flag 674 is set 675 676 677 678 Field value to be copied over into the RX_REO_QUEUE 679 descriptor. 680 681 <legal all> 682 683 pn_error_detected_flag 684 685 Field only valid when Update_pn_error_detected_flag is 686 set 687 688 689 690 Field value to be copied over into the RX_REO_QUEUE 691 descriptor. 692 693 <legal all> 694 695 pn_valid 696 697 Field only valid when Update_pn_valid is set 698 699 700 701 Field value to be copied over into the RX_REO_QUEUE 702 descriptor. 703 704 <legal all> 705 706 flush_from_cache 707 708 When set, REO shall, after finishing the execution of 709 this command, flush the related descriptor from the cache. 710 711 <legal all> 712 713 reserved_4a 714 715 <legal 0> 716 717 pn_31_0 718 719 Field only valid when Update_Pn is set 720 721 722 723 Field value to be copied over into the RX_REO_QUEUE 724 descriptor. 725 726 <legal all> 727 728 pn_63_32 729 730 Field only valid when Update_pn is set 731 732 733 734 Field value to be copied over into the RX_REO_QUEUE 735 descriptor. 736 737 <legal all> 738 739 pn_95_64 740 741 Field only valid when Update_pn is set 742 743 744 745 Field value to be copied over into the RX_REO_QUEUE 746 descriptor. 747 748 <legal all> 749 750 pn_127_96 751 752 Field only valid when Update_pn is set 753 754 755 756 Field value to be copied over into the RX_REO_QUEUE 757 descriptor. 758 759 <legal all> 760 */ 761 762 763 /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ 764 765 766 /* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER 767 768 Consumer: REO/SW/DEBUG 769 770 Producer: SW 771 772 773 774 This number can be used by SW to track, identify and 775 link the created commands with the command statusses 776 777 778 779 780 781 <legal all> 782 */ 783 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 784 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 785 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 786 787 /* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED 788 789 Consumer: REO 790 791 Producer: SW 792 793 794 795 <enum 0 NoStatus> REO does not need to generate a status 796 TLV for the execution of this command 797 798 <enum 1 StatusRequired> REO shall generate a status TLV 799 for the execution of this command 800 801 802 803 <legal all> 804 */ 805 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 806 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 807 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 808 809 /* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A 810 811 <legal 0> 812 */ 813 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 814 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 815 #define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 816 817 /* Description REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0 818 819 Consumer: REO 820 821 Producer: SW 822 823 824 825 Address (lower 32 bits) of the REO queue descriptor 826 827 <legal all> 828 */ 829 #define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 830 #define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 831 #define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 832 833 /* Description REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32 834 835 Consumer: REO 836 837 Producer: SW 838 839 840 841 Address (upper 8 bits) of the REO queue descriptor 842 843 <legal all> 844 */ 845 #define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 846 #define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 847 #define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 848 849 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER 850 851 Consumer: REO 852 853 Producer: SW 854 855 When set, receive_queue_number from this command will be 856 updated in the descriptor. 857 858 <legal all> 859 */ 860 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 861 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 862 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 863 864 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD 865 866 Consumer: REO 867 868 Producer: SW 869 870 871 872 When clear, REO will NOT update the VLD bit setting. For 873 this setting, SW MUST set the Flush_from_cache bit in this 874 command. 875 876 877 878 When set, VLD from this command will be updated in the 879 descriptor. 880 881 <legal all> 882 */ 883 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET 0x00000008 884 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB 9 885 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK 0x00000200 886 887 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 888 889 Consumer: REO 890 891 Producer: SW 892 893 When set, Associated_link_descriptor_counter from this 894 command will be updated in the descriptor. 895 896 <legal all> 897 */ 898 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 899 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 900 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 901 902 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION 903 904 Consumer: REO 905 906 Producer: SW 907 908 When set, Disable_duplicate_detection from this command 909 will be updated in the descriptor. 910 911 <legal all> 912 */ 913 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 914 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 915 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 916 917 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE 918 919 Consumer: REO 920 921 Producer: SW 922 923 When set, Soft_reorder_enable from this command will be 924 updated in the descriptor. 925 926 <legal all> 927 */ 928 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 929 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB 12 930 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 931 932 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC 933 934 Consumer: REO 935 936 Producer: SW 937 938 When set, AC from this command will be updated in the 939 descriptor. 940 941 <legal all> 942 */ 943 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET 0x00000008 944 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB 13 945 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK 0x00002000 946 947 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR 948 949 Consumer: REO 950 951 Producer: SW 952 953 When set, BAR from this command will be updated in the 954 descriptor. 955 956 <legal all> 957 */ 958 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET 0x00000008 959 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB 14 960 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK 0x00004000 961 962 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY 963 964 Consumer: REO 965 966 Producer: SW 967 968 When set, RTY from this command will be updated in the 969 descriptor. 970 971 <legal all> 972 */ 973 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET 0x00000008 974 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB 15 975 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK 0x00008000 976 977 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE 978 979 Consumer: REO 980 981 Producer: SW 982 983 When set, Chk_2k_mode from this command will be updated 984 in the descriptor. 985 986 <legal all> 987 */ 988 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 989 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB 16 990 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK 0x00010000 991 992 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE 993 994 Consumer: REO 995 996 Producer: SW 997 998 When set, OOR_Mode from this command will be updated in 999 the descriptor. 1000 1001 <legal all> 1002 */ 1003 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET 0x00000008 1004 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB 17 1005 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK 0x00020000 1006 1007 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE 1008 1009 Consumer: REO 1010 1011 Producer: SW 1012 1013 When set, BA_window_size from this command will be 1014 updated in the descriptor. 1015 1016 <legal all> 1017 */ 1018 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 1019 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB 18 1020 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 1021 1022 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED 1023 1024 Consumer: REO 1025 1026 Producer: SW 1027 1028 When set, Pn_check_needed from this command will be 1029 updated in the descriptor. 1030 1031 <legal all> 1032 */ 1033 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 1034 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB 19 1035 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 1036 1037 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN 1038 1039 Consumer: REO 1040 1041 Producer: SW 1042 1043 When set, Pn_shall_be_even from this command will be 1044 updated in the descriptor. 1045 1046 <legal all> 1047 */ 1048 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 1049 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB 20 1050 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 1051 1052 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN 1053 1054 Consumer: REO 1055 1056 Producer: SW 1057 1058 When set, Pn_shall_be_uneven from this command will be 1059 updated in the descriptor. 1060 1061 <legal all> 1062 */ 1063 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 1064 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 1065 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 1066 1067 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE 1068 1069 Consumer: REO 1070 1071 Producer: SW 1072 1073 When set, Pn_handling_enable from this command will be 1074 updated in the descriptor. 1075 1076 <legal all> 1077 */ 1078 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 1079 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB 22 1080 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 1081 1082 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE 1083 1084 Consumer: REO 1085 1086 Producer: SW 1087 1088 When set, Pn_size from this command will be updated in 1089 the descriptor. 1090 1091 <legal all> 1092 */ 1093 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET 0x00000008 1094 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB 23 1095 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK 0x00800000 1096 1097 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG 1098 1099 Consumer: REO 1100 1101 Producer: SW 1102 1103 When set, Ignore_ampdu_flag from this command will be 1104 updated in the descriptor. 1105 1106 <legal all> 1107 */ 1108 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 1109 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 1110 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 1111 1112 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD 1113 1114 Consumer: REO 1115 1116 Producer: SW 1117 1118 When set, Svld from this command will be updated in the 1119 descriptor. 1120 1121 <legal all> 1122 */ 1123 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET 0x00000008 1124 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB 25 1125 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK 0x02000000 1126 1127 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN 1128 1129 Consumer: REO 1130 1131 Producer: SW 1132 1133 When set, SSN from this command will be updated in the 1134 descriptor. 1135 1136 <legal all> 1137 */ 1138 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET 0x00000008 1139 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB 26 1140 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK 0x04000000 1141 1142 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG 1143 1144 Consumer: REO 1145 1146 Producer: SW 1147 1148 When set, Seq_2k_error_detected_flag from this command 1149 will be updated in the descriptor. 1150 1151 <legal all> 1152 */ 1153 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 1154 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 1155 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 1156 1157 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG 1158 1159 Consumer: REO 1160 1161 Producer: SW 1162 1163 When set, pn_error_detected_flag from this command will 1164 be updated in the descriptor. 1165 1166 <legal all> 1167 */ 1168 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 1169 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 1170 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 1171 1172 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID 1173 1174 Consumer: REO 1175 1176 Producer: SW 1177 1178 When set, pn_valid from this command will be updated in 1179 the descriptor. 1180 1181 <legal all> 1182 */ 1183 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET 0x00000008 1184 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB 29 1185 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK 0x20000000 1186 1187 /* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN 1188 1189 Consumer: REO 1190 1191 Producer: SW 1192 1193 When set, all pn_... fields from this command will be 1194 updated in the descriptor. 1195 1196 <legal all> 1197 */ 1198 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET 0x00000008 1199 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB 30 1200 #define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK 0x40000000 1201 1202 /* Description REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS 1203 1204 Consumer: REO 1205 1206 Producer: SW 1207 1208 When set, REO will clear (=> set to 0) the following 1209 stat counters in the REO_QUEUE_STRUCT 1210 1211 1212 1213 Last_rx_enqueue_TimeStamp 1214 1215 Last_rx_dequeue_Timestamp 1216 1217 Rx_bitmap (not a counter, but bitmap is cleared) 1218 1219 Timeout_count 1220 1221 Forward_due_to_bar_count 1222 1223 Duplicate_count 1224 1225 Frames_in_order_count 1226 1227 BAR_received_count 1228 1229 MPDU_Frames_processed_count 1230 1231 MSDU_Frames_processed_count 1232 1233 Total_processed_byte_count 1234 1235 Late_receive_MPDU_count 1236 1237 window_jump_2k 1238 1239 Hole_count 1240 1241 1242 1243 <legal all> 1244 */ 1245 #define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 1246 #define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_LSB 31 1247 #define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_MASK 0x80000000 1248 1249 /* Description REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER 1250 1251 1252 1253 1254 Field value to be copied over into the RX_REO_QUEUE 1255 descriptor. 1256 1257 <legal all> 1258 */ 1259 #define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 1260 #define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB 0 1261 #define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 1262 1263 /* Description REO_UPDATE_RX_REO_QUEUE_3_VLD 1264 1265 Field only valid when Update_VLD is set 1266 1267 1268 1269 For Update_VLD set and VLD clear, SW MUST set the 1270 Flush_from_cache bit in this command. 1271 1272 1273 1274 Field value to be copied over into the RX_REO_QUEUE 1275 descriptor. 1276 1277 <legal all> 1278 */ 1279 #define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET 0x0000000c 1280 #define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB 16 1281 #define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK 0x00010000 1282 1283 /* Description REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 1284 1285 Field only valid when 1286 Update_Associated_link_descriptor_counter is set 1287 1288 1289 1290 Field value to be copied over into the RX_REO_QUEUE 1291 descriptor. 1292 1293 <legal all> 1294 */ 1295 #define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c 1296 #define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 1297 #define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 1298 1299 /* Description REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION 1300 1301 Field only valid when Update_Disable_duplicate_detection 1302 is set 1303 1304 1305 1306 Field value to be copied over into the RX_REO_QUEUE 1307 descriptor. 1308 1309 <legal all> 1310 */ 1311 #define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c 1312 #define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB 19 1313 #define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 1314 1315 /* Description REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE 1316 1317 Field only valid when Update_Soft_reorder_enable is set 1318 1319 1320 1321 Field value to be copied over into the RX_REO_QUEUE 1322 descriptor. 1323 1324 <legal all> 1325 */ 1326 #define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET 0x0000000c 1327 #define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB 20 1328 #define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK 0x00100000 1329 1330 /* Description REO_UPDATE_RX_REO_QUEUE_3_AC 1331 1332 Field only valid when Update_AC is set 1333 1334 1335 1336 Field value to be copied over into the RX_REO_QUEUE 1337 descriptor. 1338 1339 <legal all> 1340 */ 1341 #define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET 0x0000000c 1342 #define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB 21 1343 #define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK 0x00600000 1344 1345 /* Description REO_UPDATE_RX_REO_QUEUE_3_BAR 1346 1347 Field only valid when Update_BAR is set 1348 1349 1350 1351 Field value to be copied over into the RX_REO_QUEUE 1352 descriptor. 1353 1354 <legal all> 1355 */ 1356 #define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET 0x0000000c 1357 #define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB 23 1358 #define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK 0x00800000 1359 1360 /* Description REO_UPDATE_RX_REO_QUEUE_3_RTY 1361 1362 Field only valid when Update_RTY is set 1363 1364 1365 1366 Field value to be copied over into the RX_REO_QUEUE 1367 descriptor. 1368 1369 <legal all> 1370 */ 1371 #define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET 0x0000000c 1372 #define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB 24 1373 #define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK 0x01000000 1374 1375 /* Description REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE 1376 1377 Field only valid when Update_Chk_2k_Mode is set 1378 1379 1380 1381 Field value to be copied over into the RX_REO_QUEUE 1382 descriptor. 1383 1384 <legal all> 1385 */ 1386 #define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET 0x0000000c 1387 #define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB 25 1388 #define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK 0x02000000 1389 1390 /* Description REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE 1391 1392 Field only valid when Update_OOR_Mode is set 1393 1394 1395 1396 Field value to be copied over into the RX_REO_QUEUE 1397 descriptor. 1398 1399 <legal all> 1400 */ 1401 #define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET 0x0000000c 1402 #define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB 26 1403 #define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK 0x04000000 1404 1405 /* Description REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED 1406 1407 Field only valid when Update_Pn_check_needed is set 1408 1409 1410 1411 Field value to be copied over into the RX_REO_QUEUE 1412 descriptor. 1413 1414 <legal all> 1415 */ 1416 #define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET 0x0000000c 1417 #define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB 27 1418 #define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK 0x08000000 1419 1420 /* Description REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN 1421 1422 Field only valid when Update_Pn_shall_be_even is set 1423 1424 1425 1426 Field value to be copied over into the RX_REO_QUEUE 1427 descriptor. 1428 1429 <legal all> 1430 */ 1431 #define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET 0x0000000c 1432 #define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB 28 1433 #define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK 0x10000000 1434 1435 /* Description REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN 1436 1437 Field only valid when Update_Pn_shall_be_uneven is set 1438 1439 1440 1441 Field value to be copied over into the RX_REO_QUEUE 1442 descriptor. 1443 1444 <legal all> 1445 */ 1446 #define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c 1447 #define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB 29 1448 #define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK 0x20000000 1449 1450 /* Description REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE 1451 1452 Field only valid when Update_Pn_handling_enable is set 1453 1454 1455 1456 Field value to be copied over into the RX_REO_QUEUE 1457 descriptor. 1458 1459 <legal all> 1460 */ 1461 #define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET 0x0000000c 1462 #define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB 30 1463 #define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK 0x40000000 1464 1465 /* Description REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG 1466 1467 Field only valid when Update_Ignore_ampdu_flag is set 1468 1469 1470 1471 Field value to be copied over into the RX_REO_QUEUE 1472 descriptor. 1473 1474 <legal all> 1475 */ 1476 #define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c 1477 #define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB 31 1478 #define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK 0x80000000 1479 1480 /* Description REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE 1481 1482 Field only valid when Update_BA_window_size is set 1483 1484 1485 1486 Field value to be copied over into the RX_REO_QUEUE 1487 descriptor. 1488 1489 <legal all> 1490 */ 1491 #define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET 0x00000010 1492 #define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB 0 1493 #define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK 0x000000ff 1494 1495 /* Description REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE 1496 1497 Field only valid when Update_Pn_size is set 1498 1499 1500 1501 Field value to be copied over into the RX_REO_QUEUE 1502 descriptor. 1503 1504 1505 1506 <enum 0 pn_size_24> 1507 1508 <enum 1 pn_size_48> 1509 1510 <enum 2 pn_size_128> 1511 1512 1513 1514 <legal 0-2> 1515 */ 1516 #define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET 0x00000010 1517 #define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB 8 1518 #define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK 0x00000300 1519 1520 /* Description REO_UPDATE_RX_REO_QUEUE_4_SVLD 1521 1522 Field only valid when Update_Svld is set 1523 1524 1525 1526 Field value to be copied over into the RX_REO_QUEUE 1527 descriptor. 1528 1529 <legal all> 1530 */ 1531 #define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET 0x00000010 1532 #define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB 10 1533 #define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK 0x00000400 1534 1535 /* Description REO_UPDATE_RX_REO_QUEUE_4_SSN 1536 1537 Field only valid when Update_SSN is set 1538 1539 1540 1541 Field value to be copied over into the RX_REO_QUEUE 1542 descriptor. 1543 1544 <legal all> 1545 */ 1546 #define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET 0x00000010 1547 #define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB 11 1548 #define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK 0x007ff800 1549 1550 /* Description REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG 1551 1552 Field only valid when Update_Seq_2k_error_detected_flag 1553 is set 1554 1555 1556 1557 Field value to be copied over into the RX_REO_QUEUE 1558 descriptor. 1559 1560 <legal all> 1561 */ 1562 #define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 1563 #define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 1564 #define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 1565 1566 /* Description REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG 1567 1568 Field only valid when Update_pn_error_detected_flag is 1569 set 1570 1571 1572 1573 Field value to be copied over into the RX_REO_QUEUE 1574 descriptor. 1575 1576 <legal all> 1577 */ 1578 #define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 1579 #define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB 24 1580 #define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 1581 1582 /* Description REO_UPDATE_RX_REO_QUEUE_4_PN_VALID 1583 1584 Field only valid when Update_pn_valid is set 1585 1586 1587 1588 Field value to be copied over into the RX_REO_QUEUE 1589 descriptor. 1590 1591 <legal all> 1592 */ 1593 #define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET 0x00000010 1594 #define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB 25 1595 #define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK 0x02000000 1596 1597 /* Description REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE 1598 1599 When set, REO shall, after finishing the execution of 1600 this command, flush the related descriptor from the cache. 1601 1602 <legal all> 1603 */ 1604 #define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_OFFSET 0x00000010 1605 #define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_LSB 26 1606 #define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_MASK 0x04000000 1607 1608 /* Description REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A 1609 1610 <legal 0> 1611 */ 1612 #define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 1613 #define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB 27 1614 #define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK 0xf8000000 1615 1616 /* Description REO_UPDATE_RX_REO_QUEUE_5_PN_31_0 1617 1618 Field only valid when Update_Pn is set 1619 1620 1621 1622 Field value to be copied over into the RX_REO_QUEUE 1623 descriptor. 1624 1625 <legal all> 1626 */ 1627 #define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET 0x00000014 1628 #define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB 0 1629 #define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK 0xffffffff 1630 1631 /* Description REO_UPDATE_RX_REO_QUEUE_6_PN_63_32 1632 1633 Field only valid when Update_pn is set 1634 1635 1636 1637 Field value to be copied over into the RX_REO_QUEUE 1638 descriptor. 1639 1640 <legal all> 1641 */ 1642 #define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET 0x00000018 1643 #define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB 0 1644 #define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK 0xffffffff 1645 1646 /* Description REO_UPDATE_RX_REO_QUEUE_7_PN_95_64 1647 1648 Field only valid when Update_pn is set 1649 1650 1651 1652 Field value to be copied over into the RX_REO_QUEUE 1653 descriptor. 1654 1655 <legal all> 1656 */ 1657 #define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET 0x0000001c 1658 #define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB 0 1659 #define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK 0xffffffff 1660 1661 /* Description REO_UPDATE_RX_REO_QUEUE_8_PN_127_96 1662 1663 Field only valid when Update_pn is set 1664 1665 1666 1667 Field value to be copied over into the RX_REO_QUEUE 1668 descriptor. 1669 1670 <legal all> 1671 */ 1672 #define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET 0x00000020 1673 #define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB 0 1674 #define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK 0xffffffff 1675 1676 1677 #endif // _REO_UPDATE_RX_REO_QUEUE_H_ 1678