1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_FLOW_SEARCH_ENTRY_H_ 25 #define _RX_FLOW_SEARCH_ENTRY_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 src_ip_127_96[31:0] 34 // 1 src_ip_95_64[31:0] 35 // 2 src_ip_63_32[31:0] 36 // 3 src_ip_31_0[31:0] 37 // 4 dest_ip_127_96[31:0] 38 // 5 dest_ip_95_64[31:0] 39 // 6 dest_ip_63_32[31:0] 40 // 7 dest_ip_31_0[31:0] 41 // 8 src_port[15:0], dest_port[31:16] 42 // 9 l4_protocol[7:0], valid[8], reserved_9[23:9], reo_destination_indication[28:24], msdu_drop[29], reo_destination_handler[31:30] 43 // 10 metadata[31:0] 44 // 11 aggregation_count[6:0], lro_eligible[7], msdu_count[31:8] 45 // 12 msdu_byte_count[31:0] 46 // 13 timestamp[31:0] 47 // 14 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16] 48 // 15 tcp_sequence_number[31:0] 49 // 50 // ################ END SUMMARY ################# 51 52 #define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 53 54 struct rx_flow_search_entry { 55 uint32_t src_ip_127_96 : 32; //[31:0] 56 uint32_t src_ip_95_64 : 32; //[31:0] 57 uint32_t src_ip_63_32 : 32; //[31:0] 58 uint32_t src_ip_31_0 : 32; //[31:0] 59 uint32_t dest_ip_127_96 : 32; //[31:0] 60 uint32_t dest_ip_95_64 : 32; //[31:0] 61 uint32_t dest_ip_63_32 : 32; //[31:0] 62 uint32_t dest_ip_31_0 : 32; //[31:0] 63 uint32_t src_port : 16, //[15:0] 64 dest_port : 16; //[31:16] 65 uint32_t l4_protocol : 8, //[7:0] 66 valid : 1, //[8] 67 reserved_9 : 15, //[23:9] 68 reo_destination_indication : 5, //[28:24] 69 msdu_drop : 1, //[29] 70 reo_destination_handler : 2; //[31:30] 71 uint32_t metadata : 32; //[31:0] 72 uint32_t aggregation_count : 7, //[6:0] 73 lro_eligible : 1, //[7] 74 msdu_count : 24; //[31:8] 75 uint32_t msdu_byte_count : 32; //[31:0] 76 uint32_t timestamp : 32; //[31:0] 77 uint32_t cumulative_l4_checksum : 16, //[15:0] 78 cumulative_ip_length : 16; //[31:16] 79 uint32_t tcp_sequence_number : 32; //[31:0] 80 }; 81 82 /* 83 84 src_ip_127_96 85 86 Uppermost 32 bits of source IPv6 address or prefix as 87 per Common Parser register field IP_DA_SA_PREFIX (with the 88 first byte in the MSB and the last byte in the LSB, i.e. 89 requiring a byte-swap for little-endian SW w.r.t. the byte 90 order in an IPv6 packet) 91 92 <legal all> 93 94 src_ip_95_64 95 96 Next 32 bits of source IPv6 address or prefix (requiring 97 a byte-swap for little-endian SW) <legal all> 98 99 src_ip_63_32 100 101 Next 32 bits of source IPv6 address or lowest 32 bits of 102 prefix (requiring a byte-swap for little-endian SW) 103 104 <legal all> 105 106 src_ip_31_0 107 108 Lowest 32 bits of source IPv6 address, or source IPv4 109 address (requiring a byte-swap for little-endian SW w.r.t. 110 the byte order in an IPv6 or IPv4 packet) 111 112 <legal all> 113 114 dest_ip_127_96 115 116 Uppermost 32 bits of destination IPv6 address or prefix 117 as per Common Parser register field IP_DA_SA_PREFIX (with 118 the first byte in the MSB and the last byte in the LSB, i.e. 119 requiring a byte-swap for little-endian SW w.r.t. the byte 120 order as in an IPv6 packet) 121 122 <legal all> 123 124 dest_ip_95_64 125 126 Next 32 bits of destination IPv6 address or prefix 127 (requiring a byte-swap for little-endian SW) 128 129 <legal all> 130 131 dest_ip_63_32 132 133 Next 32 bits of destination IPv6 address or lowest 32 134 bits of prefix (requiring a byte-swap for little-endian SW) 135 136 <legal all> 137 138 dest_ip_31_0 139 140 Lowest 32 bits of destination IPv6 address, or 141 destination IPv4 address (requiring a byte-swap for 142 little-endian SW w.r.t. the byte order in an IPv6 or IPv4 143 packet) 144 145 <legal all> 146 147 src_port 148 149 LSB of SPI in case of ESP/AH 150 151 else source port in case of TCP/UDP without IPsec, 152 153 else zeros in case of ICMP (with the first/third byte in 154 the MSB and the second/fourth byte in the LSB, i.e. 155 requiring a byte-swap for little-endian SW w.r.t. the byte 156 order as in an IPv6 or IPv4 packet) <legal all> 157 158 dest_port 159 160 MSB of SPI in case of ESP/AH 161 162 else destination port in case of TCP/UDP without IPsec, 163 164 else zeros in case of ICMP (with the first byte in the 165 MSB and the second byte in the LSB, i.e. requiring a 166 byte-swap for little-endian SW w.r.t. the byte order as in 167 an IPv6 or IPv4 packet) 168 169 <legal all> 170 171 l4_protocol 172 173 IPsec or L4 protocol 174 175 176 177 <enum 1 ICMPV4> 178 179 <enum 6 TCP> 180 181 <enum 17 UDP> 182 183 <enum 50 ESP> 184 185 <enum 51 AH> 186 187 <enum 58 ICMPV6> 188 189 <legal 1, 6, 17, 50, 51, 58> 190 191 valid 192 193 Indicates validity of entry 194 195 <legal all> 196 197 reserved_9 198 199 <legal 0> 200 201 reo_destination_indication 202 203 The ID of the REO exit ring where the MSDU frame shall 204 push after (MPDU level) reordering has finished. 205 206 207 208 <enum 0 reo_destination_tcl> Reo will push the frame 209 into the REO2TCL ring 210 211 <enum 1 reo_destination_sw1> Reo will push the frame 212 into the REO2SW1 ring 213 214 <enum 2 reo_destination_sw2> Reo will push the frame 215 into the REO2SW2 ring 216 217 <enum 3 reo_destination_sw3> Reo will push the frame 218 into the REO2SW3 ring 219 220 <enum 4 reo_destination_sw4> Reo will push the frame 221 into the REO2SW4 ring 222 223 <enum 5 reo_destination_release> Reo will push the frame 224 into the REO_release ring 225 226 <enum 6 reo_destination_fw> Reo will push the frame into 227 the REO2FW ring 228 229 <enum 7 reo_destination_sw5> Reo will push the frame 230 into the REO2SW5 ring (REO remaps this in chips without 231 REO2SW5 ring, e.g. Pine) 232 233 <enum 8 reo_destination_sw6> Reo will push the frame 234 into the REO2SW6 ring (REO remaps this in chips without 235 REO2SW6 ring, e.g. Pine) 236 237 <enum 9 reo_destination_9> REO remaps this <enum 10 238 reo_destination_10> REO remaps this 239 240 <enum 11 reo_destination_11> REO remaps this 241 242 <enum 12 reo_destination_12> REO remaps this <enum 13 243 reo_destination_13> REO remaps this 244 245 <enum 14 reo_destination_14> REO remaps this 246 247 <enum 15 reo_destination_15> REO remaps this 248 249 <enum 16 reo_destination_16> REO remaps this 250 251 <enum 17 reo_destination_17> REO remaps this 252 253 <enum 18 reo_destination_18> REO remaps this 254 255 <enum 19 reo_destination_19> REO remaps this 256 257 <enum 20 reo_destination_20> REO remaps this 258 259 <enum 21 reo_destination_21> REO remaps this 260 261 <enum 22 reo_destination_22> REO remaps this 262 263 <enum 23 reo_destination_23> REO remaps this 264 265 <enum 24 reo_destination_24> REO remaps this 266 267 <enum 25 reo_destination_25> REO remaps this 268 269 <enum 26 reo_destination_26> REO remaps this 270 271 <enum 27 reo_destination_27> REO remaps this 272 273 <enum 28 reo_destination_28> REO remaps this 274 275 <enum 29 reo_destination_29> REO remaps this 276 277 <enum 30 reo_destination_30> REO remaps this 278 279 <enum 31 reo_destination_31> REO remaps this 280 281 282 283 <legal all> 284 285 msdu_drop 286 287 Overriding indication to REO to forward to REO release 288 ring 289 290 <legal all> 291 292 reo_destination_handler 293 294 Indicates how to decide the REO destination indication 295 296 <enum 0 RXFT_USE_FT> Follow this entry 297 298 <enum 1 RXFT_USE_ASPT> Use address search+peer table 299 entry 300 301 <enum 2 RXFT_USE_FT2> Follow this entry 302 303 <enum 3 RXFT_USE_CCE> Use CCE super-rule 304 305 <legal all> 306 307 metadata 308 309 Value to be passed to SW if this flow search entry 310 matches 311 312 <legal all> 313 314 aggregation_count 315 316 FISA: Number'of MSDU's aggregated so far 317 318 319 320 Set to zero in chips not supporting FISA, e.g. Pine 321 322 <legal all> 323 324 lro_eligible 325 326 FISA: To indicate whether the previous MSDU for this 327 flow is eligible for LRO/FISA 328 329 330 331 Set to zero in chips not supporting FISA, e.g. Pine 332 333 <legal all> 334 335 msdu_count 336 337 Number of Rx MSDUs matching this flow 338 339 <legal all> 340 341 msdu_byte_count 342 343 Number of bytes in Rx MSDUs matching this flow 344 345 <legal all> 346 347 timestamp 348 349 Time of last reception (as measured at Rx OLE) matching 350 this flow 351 352 <legal all> 353 354 cumulative_l4_checksum 355 356 FISA: checksum 'or MSDU's that is part of this flow 357 aggregated so far 358 359 360 361 Set to zero in chips not supporting FISA, e.g. Pine 362 363 <legal all> 364 365 cumulative_ip_length 366 367 FISA: Total MSDU length that is part of this flow 368 aggregated so far 369 370 371 372 Set to zero in chips not supporting FISA, e.g. Pine 373 374 <legal all> 375 376 tcp_sequence_number 377 378 FISA: TCP Sequence number of the last packet in this 379 flow to detect sequence number jump 380 381 382 383 Set to zero in chips not supporting FISA, e.g. Pine 384 385 <legal all> 386 */ 387 388 389 /* Description RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96 390 391 Uppermost 32 bits of source IPv6 address or prefix as 392 per Common Parser register field IP_DA_SA_PREFIX (with the 393 first byte in the MSB and the last byte in the LSB, i.e. 394 requiring a byte-swap for little-endian SW w.r.t. the byte 395 order in an IPv6 packet) 396 397 <legal all> 398 */ 399 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000 400 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0 401 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff 402 403 /* Description RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64 404 405 Next 32 bits of source IPv6 address or prefix (requiring 406 a byte-swap for little-endian SW) <legal all> 407 */ 408 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004 409 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0 410 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff 411 412 /* Description RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32 413 414 Next 32 bits of source IPv6 address or lowest 32 bits of 415 prefix (requiring a byte-swap for little-endian SW) 416 417 <legal all> 418 */ 419 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008 420 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0 421 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff 422 423 /* Description RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0 424 425 Lowest 32 bits of source IPv6 address, or source IPv4 426 address (requiring a byte-swap for little-endian SW w.r.t. 427 the byte order in an IPv6 or IPv4 packet) 428 429 <legal all> 430 */ 431 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c 432 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0 433 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff 434 435 /* Description RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96 436 437 Uppermost 32 bits of destination IPv6 address or prefix 438 as per Common Parser register field IP_DA_SA_PREFIX (with 439 the first byte in the MSB and the last byte in the LSB, i.e. 440 requiring a byte-swap for little-endian SW w.r.t. the byte 441 order as in an IPv6 packet) 442 443 <legal all> 444 */ 445 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010 446 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0 447 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff 448 449 /* Description RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64 450 451 Next 32 bits of destination IPv6 address or prefix 452 (requiring a byte-swap for little-endian SW) 453 454 <legal all> 455 */ 456 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014 457 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0 458 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff 459 460 /* Description RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32 461 462 Next 32 bits of destination IPv6 address or lowest 32 463 bits of prefix (requiring a byte-swap for little-endian SW) 464 465 <legal all> 466 */ 467 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018 468 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0 469 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff 470 471 /* Description RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0 472 473 Lowest 32 bits of destination IPv6 address, or 474 destination IPv4 address (requiring a byte-swap for 475 little-endian SW w.r.t. the byte order in an IPv6 or IPv4 476 packet) 477 478 <legal all> 479 */ 480 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c 481 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0 482 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff 483 484 /* Description RX_FLOW_SEARCH_ENTRY_8_SRC_PORT 485 486 LSB of SPI in case of ESP/AH 487 488 else source port in case of TCP/UDP without IPsec, 489 490 else zeros in case of ICMP (with the first/third byte in 491 the MSB and the second/fourth byte in the LSB, i.e. 492 requiring a byte-swap for little-endian SW w.r.t. the byte 493 order as in an IPv6 or IPv4 packet) <legal all> 494 */ 495 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020 496 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0 497 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff 498 499 /* Description RX_FLOW_SEARCH_ENTRY_8_DEST_PORT 500 501 MSB of SPI in case of ESP/AH 502 503 else destination port in case of TCP/UDP without IPsec, 504 505 else zeros in case of ICMP (with the first byte in the 506 MSB and the second byte in the LSB, i.e. requiring a 507 byte-swap for little-endian SW w.r.t. the byte order as in 508 an IPv6 or IPv4 packet) 509 510 <legal all> 511 */ 512 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020 513 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16 514 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000 515 516 /* Description RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL 517 518 IPsec or L4 protocol 519 520 521 522 <enum 1 ICMPV4> 523 524 <enum 6 TCP> 525 526 <enum 17 UDP> 527 528 <enum 50 ESP> 529 530 <enum 51 AH> 531 532 <enum 58 ICMPV6> 533 534 <legal 1, 6, 17, 50, 51, 58> 535 */ 536 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024 537 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0 538 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff 539 540 /* Description RX_FLOW_SEARCH_ENTRY_9_VALID 541 542 Indicates validity of entry 543 544 <legal all> 545 */ 546 #define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024 547 #define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8 548 #define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100 549 550 /* Description RX_FLOW_SEARCH_ENTRY_9_RESERVED_9 551 552 <legal 0> 553 */ 554 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024 555 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9 556 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00 557 558 /* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION 559 560 The ID of the REO exit ring where the MSDU frame shall 561 push after (MPDU level) reordering has finished. 562 563 564 565 <enum 0 reo_destination_tcl> Reo will push the frame 566 into the REO2TCL ring 567 568 <enum 1 reo_destination_sw1> Reo will push the frame 569 into the REO2SW1 ring 570 571 <enum 2 reo_destination_sw2> Reo will push the frame 572 into the REO2SW2 ring 573 574 <enum 3 reo_destination_sw3> Reo will push the frame 575 into the REO2SW3 ring 576 577 <enum 4 reo_destination_sw4> Reo will push the frame 578 into the REO2SW4 ring 579 580 <enum 5 reo_destination_release> Reo will push the frame 581 into the REO_release ring 582 583 <enum 6 reo_destination_fw> Reo will push the frame into 584 the REO2FW ring 585 586 <enum 7 reo_destination_sw5> Reo will push the frame 587 into the REO2SW5 ring (REO remaps this in chips without 588 REO2SW5 ring, e.g. Pine) 589 590 <enum 8 reo_destination_sw6> Reo will push the frame 591 into the REO2SW6 ring (REO remaps this in chips without 592 REO2SW6 ring, e.g. Pine) 593 594 <enum 9 reo_destination_9> REO remaps this <enum 10 595 reo_destination_10> REO remaps this 596 597 <enum 11 reo_destination_11> REO remaps this 598 599 <enum 12 reo_destination_12> REO remaps this <enum 13 600 reo_destination_13> REO remaps this 601 602 <enum 14 reo_destination_14> REO remaps this 603 604 <enum 15 reo_destination_15> REO remaps this 605 606 <enum 16 reo_destination_16> REO remaps this 607 608 <enum 17 reo_destination_17> REO remaps this 609 610 <enum 18 reo_destination_18> REO remaps this 611 612 <enum 19 reo_destination_19> REO remaps this 613 614 <enum 20 reo_destination_20> REO remaps this 615 616 <enum 21 reo_destination_21> REO remaps this 617 618 <enum 22 reo_destination_22> REO remaps this 619 620 <enum 23 reo_destination_23> REO remaps this 621 622 <enum 24 reo_destination_24> REO remaps this 623 624 <enum 25 reo_destination_25> REO remaps this 625 626 <enum 26 reo_destination_26> REO remaps this 627 628 <enum 27 reo_destination_27> REO remaps this 629 630 <enum 28 reo_destination_28> REO remaps this 631 632 <enum 29 reo_destination_29> REO remaps this 633 634 <enum 30 reo_destination_30> REO remaps this 635 636 <enum 31 reo_destination_31> REO remaps this 637 638 639 640 <legal all> 641 */ 642 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024 643 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24 644 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000 645 646 /* Description RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP 647 648 Overriding indication to REO to forward to REO release 649 ring 650 651 <legal all> 652 */ 653 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024 654 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29 655 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000 656 657 /* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER 658 659 Indicates how to decide the REO destination indication 660 661 <enum 0 RXFT_USE_FT> Follow this entry 662 663 <enum 1 RXFT_USE_ASPT> Use address search+peer table 664 entry 665 666 <enum 2 RXFT_USE_FT2> Follow this entry 667 668 <enum 3 RXFT_USE_CCE> Use CCE super-rule 669 670 <legal all> 671 */ 672 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024 673 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30 674 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000 675 676 /* Description RX_FLOW_SEARCH_ENTRY_10_METADATA 677 678 Value to be passed to SW if this flow search entry 679 matches 680 681 <legal all> 682 */ 683 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028 684 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0 685 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff 686 687 /* Description RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT 688 689 FISA: Number'of MSDU's aggregated so far 690 691 692 693 Set to zero in chips not supporting FISA, e.g. Pine 694 695 <legal all> 696 */ 697 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c 698 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0 699 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f 700 701 /* Description RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE 702 703 FISA: To indicate whether the previous MSDU for this 704 flow is eligible for LRO/FISA 705 706 707 708 Set to zero in chips not supporting FISA, e.g. Pine 709 710 <legal all> 711 */ 712 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c 713 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7 714 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080 715 716 /* Description RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT 717 718 Number of Rx MSDUs matching this flow 719 720 <legal all> 721 */ 722 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c 723 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8 724 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00 725 726 /* Description RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT 727 728 Number of bytes in Rx MSDUs matching this flow 729 730 <legal all> 731 */ 732 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030 733 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0 734 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff 735 736 /* Description RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP 737 738 Time of last reception (as measured at Rx OLE) matching 739 this flow 740 741 <legal all> 742 */ 743 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034 744 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0 745 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff 746 747 /* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM 748 749 FISA: checksum 'or MSDU's that is part of this flow 750 aggregated so far 751 752 753 754 Set to zero in chips not supporting FISA, e.g. Pine 755 756 <legal all> 757 */ 758 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038 759 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0 760 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff 761 762 /* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH 763 764 FISA: Total MSDU length that is part of this flow 765 aggregated so far 766 767 768 769 Set to zero in chips not supporting FISA, e.g. Pine 770 771 <legal all> 772 */ 773 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 774 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16 775 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 776 777 /* Description RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER 778 779 FISA: TCP Sequence number of the last packet in this 780 flow to detect sequence number jump 781 782 783 784 Set to zero in chips not supporting FISA, e.g. Pine 785 786 <legal all> 787 */ 788 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c 789 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0 790 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff 791 792 793 #endif // _RX_FLOW_SEARCH_ENTRY_H_ 794