1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MPDU_END_H_ 25 #define _RX_MPDU_END_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 34 // 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] 35 // 36 // ################ END SUMMARY ################# 37 38 #define NUM_OF_DWORDS_RX_MPDU_END 2 39 40 struct rx_mpdu_end { 41 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 42 sw_frame_group_id : 7, //[8:2] 43 reserved_0 : 7, //[15:9] 44 phy_ppdu_id : 16; //[31:16] 45 uint32_t reserved_1a : 11, //[10:0] 46 unsup_ktype_short_frame : 1, //[11] 47 rx_in_tx_decrypt_byp : 1, //[12] 48 overflow_err : 1, //[13] 49 mpdu_length_err : 1, //[14] 50 tkip_mic_err : 1, //[15] 51 decrypt_err : 1, //[16] 52 unencrypted_frame_err : 1, //[17] 53 pn_fields_contain_valid_info : 1, //[18] 54 fcs_err : 1, //[19] 55 msdu_length_err : 1, //[20] 56 rxdma0_destination_ring : 2, //[22:21] 57 rxdma1_destination_ring : 2, //[24:23] 58 decrypt_status_code : 3, //[27:25] 59 rx_bitmap_not_updated : 1, //[28] 60 reserved_1b : 3; //[31:29] 61 }; 62 63 /* 64 65 rxpcu_mpdu_filter_in_category 66 67 Field indicates what the reason was that this MPDU frame 68 was allowed to come into the receive path by RXPCU 69 70 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 71 frame filter programming of rxpcu 72 73 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 74 regular frame filter and would have been dropped, were it 75 not for the frame fitting into the 'monitor_client' 76 category. 77 78 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 79 regular frame filter and also did not pass the 80 rxpcu_monitor_client filter. It would have been dropped 81 accept that it did pass the 'monitor_other' category. 82 83 <legal 0-2> 84 85 sw_frame_group_id 86 87 SW processes frames based on certain classifications. 88 This field indicates to what sw classification this MPDU is 89 mapped. 90 91 The classification is given in priority order 92 93 94 95 <enum 0 sw_frame_group_NDP_frame> 96 97 98 99 <enum 1 sw_frame_group_Multicast_data> 100 101 <enum 2 sw_frame_group_Unicast_data> 102 103 <enum 3 sw_frame_group_Null_data > This includes mpdus 104 of type Data Null as well as QoS Data Null 105 106 107 108 <enum 4 sw_frame_group_mgmt_0000 > 109 110 <enum 5 sw_frame_group_mgmt_0001 > 111 112 <enum 6 sw_frame_group_mgmt_0010 > 113 114 <enum 7 sw_frame_group_mgmt_0011 > 115 116 <enum 8 sw_frame_group_mgmt_0100 > 117 118 <enum 9 sw_frame_group_mgmt_0101 > 119 120 <enum 10 sw_frame_group_mgmt_0110 > 121 122 <enum 11 sw_frame_group_mgmt_0111 > 123 124 <enum 12 sw_frame_group_mgmt_1000 > 125 126 <enum 13 sw_frame_group_mgmt_1001 > 127 128 <enum 14 sw_frame_group_mgmt_1010 > 129 130 <enum 15 sw_frame_group_mgmt_1011 > 131 132 <enum 16 sw_frame_group_mgmt_1100 > 133 134 <enum 17 sw_frame_group_mgmt_1101 > 135 136 <enum 18 sw_frame_group_mgmt_1110 > 137 138 <enum 19 sw_frame_group_mgmt_1111 > 139 140 141 142 <enum 20 sw_frame_group_ctrl_0000 > 143 144 <enum 21 sw_frame_group_ctrl_0001 > 145 146 <enum 22 sw_frame_group_ctrl_0010 > 147 148 <enum 23 sw_frame_group_ctrl_0011 > 149 150 <enum 24 sw_frame_group_ctrl_0100 > 151 152 <enum 25 sw_frame_group_ctrl_0101 > 153 154 <enum 26 sw_frame_group_ctrl_0110 > 155 156 <enum 27 sw_frame_group_ctrl_0111 > 157 158 <enum 28 sw_frame_group_ctrl_1000 > 159 160 <enum 29 sw_frame_group_ctrl_1001 > 161 162 <enum 30 sw_frame_group_ctrl_1010 > 163 164 <enum 31 sw_frame_group_ctrl_1011 > 165 166 <enum 32 sw_frame_group_ctrl_1100 > 167 168 <enum 33 sw_frame_group_ctrl_1101 > 169 170 <enum 34 sw_frame_group_ctrl_1110 > 171 172 <enum 35 sw_frame_group_ctrl_1111 > 173 174 175 176 <enum 36 sw_frame_group_unsupported> This covers type 3 177 and protocol version != 0 178 179 180 181 182 183 184 <legal 0-37> 185 186 reserved_0 187 188 <legal 0> 189 190 phy_ppdu_id 191 192 A ppdu counter value that PHY increments for every PPDU 193 received. The counter value wraps around 194 195 <legal all> 196 197 reserved_1a 198 199 <legal 0> 200 201 unsup_ktype_short_frame 202 203 This bit will be '1' when WEP or TKIP or WAPI key type 204 is received for 11ah short frame. Crypto will bypass the 205 received packet without decryption to RxOLE after setting 206 this bit. 207 208 rx_in_tx_decrypt_byp 209 210 Indicates that RX packet is not decrypted as Crypto is 211 busy with TX packet processing. 212 213 overflow_err 214 215 RXPCU Receive FIFO ran out of space to receive the full 216 MPDU. Therefor this MPDU is terminated early and is thus 217 corrupted. 218 219 220 221 This MPDU will not be ACKed. 222 223 RXPCU might still be able to correctly receive the 224 following MPDUs in the PPDU if enough fifo space became 225 available in time 226 227 mpdu_length_err 228 229 Set by RXPCU if the expected MPDU length does not 230 correspond with the actually received number of bytes in the 231 MPDU. 232 233 tkip_mic_err 234 235 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 236 for this MPDU 237 238 decrypt_err 239 240 Set by RX CRYPTO when CRYPTO detected a decrypt error 241 for this MPDU or CRYPTO received an encrypted frame, but did 242 not get a valid corresponding key id in the peer entry. 243 244 unencrypted_frame_err 245 246 Set by RX CRYPTO when CRYPTO detected an unencrypted 247 frame while in the peer entry field 248 'All_frames_shall_be_encrypted' is set. 249 250 pn_fields_contain_valid_info 251 252 Set by RX CRYPTO to indicate that there is a valid PN 253 field present in this MPDU 254 255 fcs_err 256 257 Set by RXPCU when there is an FCS error detected for 258 this MPDU 259 260 NOTE that when this field is set, all other (error) 261 field settings should be ignored as modules could have made 262 wrong decisions based on the corrupted data. 263 264 msdu_length_err 265 266 Set by RXOLE when there is an msdu length error detected 267 in at least 1 of the MSDUs embedded within the MPDU 268 269 rxdma0_destination_ring 270 271 The ring to which RXDMA0 shall push the frame, assuming 272 no MPDU level errors are detected. In case of MPDU level 273 errors, RXDMA0 might change the RXDMA0 destination 274 275 276 277 <enum 0 rxdma_release_ring > RXDMA0 shall push the 278 frame to the Release ring. Effectively this means the frame 279 needs to be dropped. 280 281 282 283 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 284 the FW ring 285 286 287 288 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 289 the SW ring 290 291 292 293 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 294 to the REO entrance ring 295 296 297 298 <legal all> 299 300 rxdma1_destination_ring 301 302 The ring to which RXDMA1 shall push the frame, assuming 303 no MPDU level errors are detected. In case of MPDU level 304 errors, RXDMA1 might change the RXDMA destination 305 306 307 308 <enum 0 rxdma_release_ring > RXDMA1 shall push the 309 frame to the Release ring. Effectively this means the frame 310 needs to be dropped. 311 312 313 314 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 315 the FW ring 316 317 318 319 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 320 the SW ring 321 322 323 324 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 325 to the REO entrance ring 326 327 328 329 <legal all> 330 331 decrypt_status_code 332 333 Field provides insight into the decryption performed 334 335 336 337 <enum 0 decrypt_ok> Frame had protection enabled and 338 decrypted properly 339 340 <enum 1 decrypt_unprotected_frame > Frame is unprotected 341 and hence bypassed 342 343 <enum 2 decrypt_data_err > Frame has protection enabled 344 and could not be properly decrypted due to MIC/ICV mismatch 345 etc. 346 347 <enum 3 decrypt_key_invalid > Frame has protection 348 enabled but the key that was required to decrypt this frame 349 was not valid 350 351 <enum 4 decrypt_peer_entry_invalid > Frame has 352 protection enabled but the key that was required to decrypt 353 this frame was not valid 354 355 <enum 5 decrypt_other > Reserved for other indications 356 357 358 359 <legal 0 - 5> 360 361 rx_bitmap_not_updated 362 363 Frame is received, but RXPCU could not update the 364 receive bitmap due to (temporary) fifo contraints. 365 366 <legal all> 367 368 reserved_1b 369 370 <legal 0> 371 */ 372 373 374 /* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 375 376 Field indicates what the reason was that this MPDU frame 377 was allowed to come into the receive path by RXPCU 378 379 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 380 frame filter programming of rxpcu 381 382 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 383 regular frame filter and would have been dropped, were it 384 not for the frame fitting into the 'monitor_client' 385 category. 386 387 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 388 regular frame filter and also did not pass the 389 rxpcu_monitor_client filter. It would have been dropped 390 accept that it did pass the 'monitor_other' category. 391 392 <legal 0-2> 393 */ 394 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 395 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 396 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 397 398 /* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID 399 400 SW processes frames based on certain classifications. 401 This field indicates to what sw classification this MPDU is 402 mapped. 403 404 The classification is given in priority order 405 406 407 408 <enum 0 sw_frame_group_NDP_frame> 409 410 411 412 <enum 1 sw_frame_group_Multicast_data> 413 414 <enum 2 sw_frame_group_Unicast_data> 415 416 <enum 3 sw_frame_group_Null_data > This includes mpdus 417 of type Data Null as well as QoS Data Null 418 419 420 421 <enum 4 sw_frame_group_mgmt_0000 > 422 423 <enum 5 sw_frame_group_mgmt_0001 > 424 425 <enum 6 sw_frame_group_mgmt_0010 > 426 427 <enum 7 sw_frame_group_mgmt_0011 > 428 429 <enum 8 sw_frame_group_mgmt_0100 > 430 431 <enum 9 sw_frame_group_mgmt_0101 > 432 433 <enum 10 sw_frame_group_mgmt_0110 > 434 435 <enum 11 sw_frame_group_mgmt_0111 > 436 437 <enum 12 sw_frame_group_mgmt_1000 > 438 439 <enum 13 sw_frame_group_mgmt_1001 > 440 441 <enum 14 sw_frame_group_mgmt_1010 > 442 443 <enum 15 sw_frame_group_mgmt_1011 > 444 445 <enum 16 sw_frame_group_mgmt_1100 > 446 447 <enum 17 sw_frame_group_mgmt_1101 > 448 449 <enum 18 sw_frame_group_mgmt_1110 > 450 451 <enum 19 sw_frame_group_mgmt_1111 > 452 453 454 455 <enum 20 sw_frame_group_ctrl_0000 > 456 457 <enum 21 sw_frame_group_ctrl_0001 > 458 459 <enum 22 sw_frame_group_ctrl_0010 > 460 461 <enum 23 sw_frame_group_ctrl_0011 > 462 463 <enum 24 sw_frame_group_ctrl_0100 > 464 465 <enum 25 sw_frame_group_ctrl_0101 > 466 467 <enum 26 sw_frame_group_ctrl_0110 > 468 469 <enum 27 sw_frame_group_ctrl_0111 > 470 471 <enum 28 sw_frame_group_ctrl_1000 > 472 473 <enum 29 sw_frame_group_ctrl_1001 > 474 475 <enum 30 sw_frame_group_ctrl_1010 > 476 477 <enum 31 sw_frame_group_ctrl_1011 > 478 479 <enum 32 sw_frame_group_ctrl_1100 > 480 481 <enum 33 sw_frame_group_ctrl_1101 > 482 483 <enum 34 sw_frame_group_ctrl_1110 > 484 485 <enum 35 sw_frame_group_ctrl_1111 > 486 487 488 489 <enum 36 sw_frame_group_unsupported> This covers type 3 490 and protocol version != 0 491 492 493 494 495 496 497 <legal 0-37> 498 */ 499 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 500 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 501 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 502 503 /* Description RX_MPDU_END_0_RESERVED_0 504 505 <legal 0> 506 */ 507 #define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 508 #define RX_MPDU_END_0_RESERVED_0_LSB 9 509 #define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 510 511 /* Description RX_MPDU_END_0_PHY_PPDU_ID 512 513 A ppdu counter value that PHY increments for every PPDU 514 received. The counter value wraps around 515 516 <legal all> 517 */ 518 #define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 519 #define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 520 #define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 521 522 /* Description RX_MPDU_END_1_RESERVED_1A 523 524 <legal 0> 525 */ 526 #define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 527 #define RX_MPDU_END_1_RESERVED_1A_LSB 0 528 #define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff 529 530 /* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME 531 532 This bit will be '1' when WEP or TKIP or WAPI key type 533 is received for 11ah short frame. Crypto will bypass the 534 received packet without decryption to RxOLE after setting 535 this bit. 536 */ 537 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 538 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 539 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 540 541 /* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP 542 543 Indicates that RX packet is not decrypted as Crypto is 544 busy with TX packet processing. 545 */ 546 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 547 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 548 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 549 550 /* Description RX_MPDU_END_1_OVERFLOW_ERR 551 552 RXPCU Receive FIFO ran out of space to receive the full 553 MPDU. Therefor this MPDU is terminated early and is thus 554 corrupted. 555 556 557 558 This MPDU will not be ACKed. 559 560 RXPCU might still be able to correctly receive the 561 following MPDUs in the PPDU if enough fifo space became 562 available in time 563 */ 564 #define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 565 #define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 566 #define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 567 568 /* Description RX_MPDU_END_1_MPDU_LENGTH_ERR 569 570 Set by RXPCU if the expected MPDU length does not 571 correspond with the actually received number of bytes in the 572 MPDU. 573 */ 574 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 575 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 576 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 577 578 /* Description RX_MPDU_END_1_TKIP_MIC_ERR 579 580 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 581 for this MPDU 582 */ 583 #define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 584 #define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 585 #define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 586 587 /* Description RX_MPDU_END_1_DECRYPT_ERR 588 589 Set by RX CRYPTO when CRYPTO detected a decrypt error 590 for this MPDU or CRYPTO received an encrypted frame, but did 591 not get a valid corresponding key id in the peer entry. 592 */ 593 #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 594 #define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 595 #define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 596 597 /* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR 598 599 Set by RX CRYPTO when CRYPTO detected an unencrypted 600 frame while in the peer entry field 601 'All_frames_shall_be_encrypted' is set. 602 */ 603 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 604 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 605 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 606 607 /* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO 608 609 Set by RX CRYPTO to indicate that there is a valid PN 610 field present in this MPDU 611 */ 612 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 613 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 614 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 615 616 /* Description RX_MPDU_END_1_FCS_ERR 617 618 Set by RXPCU when there is an FCS error detected for 619 this MPDU 620 621 NOTE that when this field is set, all other (error) 622 field settings should be ignored as modules could have made 623 wrong decisions based on the corrupted data. 624 */ 625 #define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 626 #define RX_MPDU_END_1_FCS_ERR_LSB 19 627 #define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 628 629 /* Description RX_MPDU_END_1_MSDU_LENGTH_ERR 630 631 Set by RXOLE when there is an msdu length error detected 632 in at least 1 of the MSDUs embedded within the MPDU 633 */ 634 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 635 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 636 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 637 638 /* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING 639 640 The ring to which RXDMA0 shall push the frame, assuming 641 no MPDU level errors are detected. In case of MPDU level 642 errors, RXDMA0 might change the RXDMA0 destination 643 644 645 646 <enum 0 rxdma_release_ring > RXDMA0 shall push the 647 frame to the Release ring. Effectively this means the frame 648 needs to be dropped. 649 650 651 652 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 653 the FW ring 654 655 656 657 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 658 the SW ring 659 660 661 662 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 663 to the REO entrance ring 664 665 666 667 <legal all> 668 */ 669 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 670 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 671 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 672 673 /* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING 674 675 The ring to which RXDMA1 shall push the frame, assuming 676 no MPDU level errors are detected. In case of MPDU level 677 errors, RXDMA1 might change the RXDMA destination 678 679 680 681 <enum 0 rxdma_release_ring > RXDMA1 shall push the 682 frame to the Release ring. Effectively this means the frame 683 needs to be dropped. 684 685 686 687 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 688 the FW ring 689 690 691 692 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 693 the SW ring 694 695 696 697 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 698 to the REO entrance ring 699 700 701 702 <legal all> 703 */ 704 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 705 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 706 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 707 708 /* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE 709 710 Field provides insight into the decryption performed 711 712 713 714 <enum 0 decrypt_ok> Frame had protection enabled and 715 decrypted properly 716 717 <enum 1 decrypt_unprotected_frame > Frame is unprotected 718 and hence bypassed 719 720 <enum 2 decrypt_data_err > Frame has protection enabled 721 and could not be properly decrypted due to MIC/ICV mismatch 722 etc. 723 724 <enum 3 decrypt_key_invalid > Frame has protection 725 enabled but the key that was required to decrypt this frame 726 was not valid 727 728 <enum 4 decrypt_peer_entry_invalid > Frame has 729 protection enabled but the key that was required to decrypt 730 this frame was not valid 731 732 <enum 5 decrypt_other > Reserved for other indications 733 734 735 736 <legal 0 - 5> 737 */ 738 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 739 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 740 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 741 742 /* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED 743 744 Frame is received, but RXPCU could not update the 745 receive bitmap due to (temporary) fifo contraints. 746 747 <legal all> 748 */ 749 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 750 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 751 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 752 753 /* Description RX_MPDU_END_1_RESERVED_1B 754 755 <legal 0> 756 */ 757 #define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 758 #define RX_MPDU_END_1_RESERVED_1B_LSB 29 759 #define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 760 761 762 #endif // _RX_MPDU_END_H_ 763