1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MPDU_INFO_H_ 25 #define _RX_MPDU_INFO_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rxpt_classify_info.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct rxpt_classify_info rxpt_classify_info_details; 35 // 1 rx_reo_queue_desc_addr_31_0[31:0] 36 // 2 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_2a[31:26] 37 // 3 pn_31_0[31:0] 38 // 4 pn_63_32[31:0] 39 // 5 pn_95_64[31:0] 40 // 6 pn_127_96[31:0] 41 // 7 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], wep_key_width_for_variable_key[7:6], mesh_sta[9:8], bssid_hit[10], bssid_number[14:11], tid[18:15], reserved_7a[31:19] 42 // 8 peer_meta_data[31:0] 43 // 9 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_9a[15:14], phy_ppdu_id[31:16] 44 // 10 ast_index[15:0], sw_peer_id[31:16] 45 // 11 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], mpdu_fragment_number[13:10], more_fragment_flag[14], reserved_11a[15], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] 46 // 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], raw_mpdu[30], reserved_12[31] 47 // 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], amsdu_present[30], reserved_13[31] 48 // 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] 49 // 15 mac_addr_ad1_31_0[31:0] 50 // 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] 51 // 17 mac_addr_ad2_47_16[31:0] 52 // 18 mac_addr_ad3_31_0[31:0] 53 // 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] 54 // 20 mac_addr_ad4_31_0[31:0] 55 // 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] 56 // 22 mpdu_ht_control_field[31:0] 57 // 58 // ################ END SUMMARY ################# 59 60 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 61 62 struct rx_mpdu_info { 63 struct rxpt_classify_info rxpt_classify_info_details; 64 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 65 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 66 receive_queue_number : 16, //[23:8] 67 pre_delim_err_warning : 1, //[24] 68 first_delim_err : 1, //[25] 69 reserved_2a : 6; //[31:26] 70 uint32_t pn_31_0 : 32; //[31:0] 71 uint32_t pn_63_32 : 32; //[31:0] 72 uint32_t pn_95_64 : 32; //[31:0] 73 uint32_t pn_127_96 : 32; //[31:0] 74 uint32_t epd_en : 1, //[0] 75 all_frames_shall_be_encrypted : 1, //[1] 76 encrypt_type : 4, //[5:2] 77 wep_key_width_for_variable_key : 2, //[7:6] 78 mesh_sta : 2, //[9:8] 79 bssid_hit : 1, //[10] 80 bssid_number : 4, //[14:11] 81 tid : 4, //[18:15] 82 reserved_7a : 13; //[31:19] 83 uint32_t peer_meta_data : 32; //[31:0] 84 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 85 sw_frame_group_id : 7, //[8:2] 86 ndp_frame : 1, //[9] 87 phy_err : 1, //[10] 88 phy_err_during_mpdu_header : 1, //[11] 89 protocol_version_err : 1, //[12] 90 ast_based_lookup_valid : 1, //[13] 91 reserved_9a : 2, //[15:14] 92 phy_ppdu_id : 16; //[31:16] 93 uint32_t ast_index : 16, //[15:0] 94 sw_peer_id : 16; //[31:16] 95 uint32_t mpdu_frame_control_valid : 1, //[0] 96 mpdu_duration_valid : 1, //[1] 97 mac_addr_ad1_valid : 1, //[2] 98 mac_addr_ad2_valid : 1, //[3] 99 mac_addr_ad3_valid : 1, //[4] 100 mac_addr_ad4_valid : 1, //[5] 101 mpdu_sequence_control_valid : 1, //[6] 102 mpdu_qos_control_valid : 1, //[7] 103 mpdu_ht_control_valid : 1, //[8] 104 frame_encryption_info_valid : 1, //[9] 105 mpdu_fragment_number : 4, //[13:10] 106 more_fragment_flag : 1, //[14] 107 reserved_11a : 1, //[15] 108 fr_ds : 1, //[16] 109 to_ds : 1, //[17] 110 encrypted : 1, //[18] 111 mpdu_retry : 1, //[19] 112 mpdu_sequence_number : 12; //[31:20] 113 uint32_t key_id_octet : 8, //[7:0] 114 new_peer_entry : 1, //[8] 115 decrypt_needed : 1, //[9] 116 decap_type : 2, //[11:10] 117 rx_insert_vlan_c_tag_padding : 1, //[12] 118 rx_insert_vlan_s_tag_padding : 1, //[13] 119 strip_vlan_c_tag_decap : 1, //[14] 120 strip_vlan_s_tag_decap : 1, //[15] 121 pre_delim_count : 12, //[27:16] 122 ampdu_flag : 1, //[28] 123 bar_frame : 1, //[29] 124 raw_mpdu : 1, //[30] 125 reserved_12 : 1; //[31] 126 uint32_t mpdu_length : 14, //[13:0] 127 first_mpdu : 1, //[14] 128 mcast_bcast : 1, //[15] 129 ast_index_not_found : 1, //[16] 130 ast_index_timeout : 1, //[17] 131 power_mgmt : 1, //[18] 132 non_qos : 1, //[19] 133 null_data : 1, //[20] 134 mgmt_type : 1, //[21] 135 ctrl_type : 1, //[22] 136 more_data : 1, //[23] 137 eosp : 1, //[24] 138 fragment_flag : 1, //[25] 139 order : 1, //[26] 140 u_apsd_trigger : 1, //[27] 141 encrypt_required : 1, //[28] 142 directed : 1, //[29] 143 amsdu_present : 1, //[30] 144 reserved_13 : 1; //[31] 145 uint32_t mpdu_frame_control_field : 16, //[15:0] 146 mpdu_duration_field : 16; //[31:16] 147 uint32_t mac_addr_ad1_31_0 : 32; //[31:0] 148 uint32_t mac_addr_ad1_47_32 : 16, //[15:0] 149 mac_addr_ad2_15_0 : 16; //[31:16] 150 uint32_t mac_addr_ad2_47_16 : 32; //[31:0] 151 uint32_t mac_addr_ad3_31_0 : 32; //[31:0] 152 uint32_t mac_addr_ad3_47_32 : 16, //[15:0] 153 mpdu_sequence_control_field : 16; //[31:16] 154 uint32_t mac_addr_ad4_31_0 : 32; //[31:0] 155 uint32_t mac_addr_ad4_47_32 : 16, //[15:0] 156 mpdu_qos_control_field : 16; //[31:16] 157 uint32_t mpdu_ht_control_field : 32; //[31:0] 158 }; 159 160 /* 161 162 struct rxpt_classify_info rxpt_classify_info_details 163 164 In case of ndp or phy_err or AST_based_lookup_valid == 165 0, this field will be set to 0 166 167 168 169 RXOLE related classification info 170 171 <legal all 172 173 rx_reo_queue_desc_addr_31_0 174 175 In case of ndp or phy_err or AST_based_lookup_valid == 176 0, this field will be set to 0 177 178 179 180 Address (lower 32 bits) of the REO queue descriptor. 181 182 183 184 If no Peer entry lookup happened for this frame, the 185 value wil be set to 0, and the frame shall never be pushed 186 to REO entrance ring. 187 188 <legal all> 189 190 rx_reo_queue_desc_addr_39_32 191 192 In case of ndp or phy_err or AST_based_lookup_valid == 193 0, this field will be set to 0 194 195 196 197 Address (upper 8 bits) of the REO queue descriptor. 198 199 200 201 If no Peer entry lookup happened for this frame, the 202 value wil be set to 0, and the frame shall never be pushed 203 to REO entrance ring. 204 205 <legal all> 206 207 receive_queue_number 208 209 In case of ndp or phy_err or AST_based_lookup_valid == 210 0, this field will be set to 0 211 212 213 214 Indicates the MPDU queue ID to which this MPDU link 215 descriptor belongs 216 217 Used for tracking and debugging 218 219 <legal all> 220 221 pre_delim_err_warning 222 223 Indicates that a delimiter FCS error was found in 224 between the Previous MPDU and this MPDU. 225 226 227 228 Note that this is just a warning, and does not mean that 229 this MPDU is corrupted in any way. If it is, there will be 230 other errors indicated such as FCS or decrypt errors 231 232 233 234 In case of ndp or phy_err, this field will indicate at 235 least one of delimiters located after the last MPDU in the 236 previous PPDU has been corrupted. 237 238 first_delim_err 239 240 Indicates that the first delimiter had a FCS failure. 241 Only valid when first_mpdu and first_msdu are set. 242 243 244 245 246 reserved_2a 247 248 <legal 0> 249 250 pn_31_0 251 252 253 254 255 256 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 257 is valid. 258 259 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 260 WEPSeed[1], pn1}. Only pn[47:0] is valid. 261 262 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 263 pn1, pn0}. Only pn[47:0] is valid. 264 265 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 266 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 267 pn0}. pn[127:0] are valid. 268 269 270 271 272 pn_63_32 273 274 275 276 277 Bits [63:32] of the PN number. See description for 278 pn_31_0. 279 280 281 282 283 pn_95_64 284 285 286 287 288 Bits [95:64] of the PN number. See description for 289 pn_31_0. 290 291 292 293 294 pn_127_96 295 296 297 298 299 Bits [127:96] of the PN number. See description for 300 pn_31_0. 301 302 303 304 305 epd_en 306 307 Field only valid when AST_based_lookup_valid == 1. 308 309 310 311 312 313 In case of ndp or phy_err or AST_based_lookup_valid == 314 0, this field will be set to 0 315 316 317 318 If set to one use EPD instead of LPD 319 320 321 322 323 <legal all> 324 325 all_frames_shall_be_encrypted 326 327 In case of ndp or phy_err or AST_based_lookup_valid == 328 0, this field will be set to 0 329 330 331 332 When set, all frames (data only ?) shall be encrypted. 333 If not, RX CRYPTO shall set an error flag. 334 335 <legal all> 336 337 encrypt_type 338 339 In case of ndp or phy_err or AST_based_lookup_valid == 340 0, this field will be set to 0 341 342 343 344 Indicates type of decrypt cipher used (as defined in the 345 peer entry) 346 347 348 349 <enum 0 wep_40> WEP 40-bit 350 351 <enum 1 wep_104> WEP 104-bit 352 353 <enum 2 tkip_no_mic> TKIP without MIC 354 355 <enum 3 wep_128> WEP 128-bit 356 357 <enum 4 tkip_with_mic> TKIP with MIC 358 359 <enum 5 wapi> WAPI 360 361 <enum 6 aes_ccmp_128> AES CCMP 128 362 363 <enum 7 no_cipher> No crypto 364 365 <enum 8 aes_ccmp_256> AES CCMP 256 366 367 <enum 9 aes_gcmp_128> AES CCMP 128 368 369 <enum 10 aes_gcmp_256> AES CCMP 256 370 371 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 372 373 374 375 <enum 12 wep_varied_width> WEP encryption. As for WEP 376 per keyid the key bit width can vary, the key bit width for 377 this MPDU will be indicated in field 378 wep_key_width_for_variable key 379 380 <legal 0-12> 381 382 wep_key_width_for_variable_key 383 384 Field only valid when key_type is set to 385 wep_varied_width. 386 387 388 389 This field indicates the size of the wep key for this 390 MPDU. 391 392 393 394 <enum 0 wep_varied_width_40> WEP 40-bit 395 396 <enum 1 wep_varied_width_104> WEP 104-bit 397 398 <enum 2 wep_varied_width_128> WEP 128-bit 399 400 401 402 <legal 0-2> 403 404 mesh_sta 405 406 In case of ndp or phy_err or AST_based_lookup_valid == 407 0, this field will be set to 0 408 409 410 411 When set, this is a Mesh (11s) STA. 412 413 414 415 The interpretation of the A-MSDU 'Length' field in the 416 MPDU (if any) is decided by the e-numerations below. 417 418 419 420 <enum 0 MESH_DISABLE> 421 422 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 423 includes the length of Mesh Control. 424 425 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 426 excludes the length of Mesh Control. 427 428 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 429 and excludes the length of Mesh Control. This is 430 802.11s-compliant. 431 432 <legal all> 433 434 bssid_hit 435 436 In case of ndp or phy_err or AST_based_lookup_valid == 437 0, this field will be set to 0 438 439 440 441 When set, the BSSID of the incoming frame matched one of 442 the 8 BSSID register values 443 444 445 446 <legal all> 447 448 bssid_number 449 450 Field only valid when bssid_hit is set. 451 452 453 454 This number indicates which one out of the 8 BSSID 455 register values matched the incoming frame 456 457 <legal all> 458 459 tid 460 461 Field only valid when mpdu_qos_control_valid is set 462 463 464 465 The TID field in the QoS control field 466 467 <legal all> 468 469 reserved_7a 470 471 <legal 0> 472 473 peer_meta_data 474 475 In case of ndp or phy_err or AST_based_lookup_valid == 476 0, this field will be set to 0 477 478 479 480 Meta data that SW has programmed in the Peer table entry 481 of the transmitting STA. 482 483 <legal all> 484 485 rxpcu_mpdu_filter_in_category 486 487 Field indicates what the reason was that this MPDU frame 488 was allowed to come into the receive path by RXPCU 489 490 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 491 frame filter programming of rxpcu 492 493 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 494 regular frame filter and would have been dropped, were it 495 not for the frame fitting into the 'monitor_client' 496 category. 497 498 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 499 regular frame filter and also did not pass the 500 rxpcu_monitor_client filter. It would have been dropped 501 accept that it did pass the 'monitor_other' category. 502 503 504 505 Note: for ndp frame, if it was expected because the 506 preceding NDPA was filter_pass, the setting 507 rxpcu_filter_pass will be used. This setting will also be 508 used for every ndp frame in case Promiscuous mode is 509 enabled. 510 511 512 513 In case promiscuous is not enabled, and an NDP is not 514 preceded by a NPDA filter pass frame, the only other setting 515 that could appear here for the NDP is rxpcu_monitor_other. 516 517 (rxpcu has a configuration bit specifically for this 518 scenario) 519 520 521 522 Note: for 523 524 <legal 0-2> 525 526 sw_frame_group_id 527 528 SW processes frames based on certain classifications. 529 This field indicates to what sw classification this MPDU is 530 mapped. 531 532 The classification is given in priority order 533 534 535 536 <enum 0 sw_frame_group_NDP_frame> Note: The 537 corresponding Rxpcu_Mpdu_filter_in_category can be 538 rxpcu_filter_pass or rxpcu_monitor_other 539 540 541 542 <enum 1 sw_frame_group_Multicast_data> 543 544 <enum 2 sw_frame_group_Unicast_data> 545 546 <enum 3 sw_frame_group_Null_data > This includes mpdus 547 of type Data Null as well as QoS Data Null 548 549 550 551 <enum 4 sw_frame_group_mgmt_0000 > 552 553 <enum 5 sw_frame_group_mgmt_0001 > 554 555 <enum 6 sw_frame_group_mgmt_0010 > 556 557 <enum 7 sw_frame_group_mgmt_0011 > 558 559 <enum 8 sw_frame_group_mgmt_0100 > 560 561 <enum 9 sw_frame_group_mgmt_0101 > 562 563 <enum 10 sw_frame_group_mgmt_0110 > 564 565 <enum 11 sw_frame_group_mgmt_0111 > 566 567 <enum 12 sw_frame_group_mgmt_1000 > 568 569 <enum 13 sw_frame_group_mgmt_1001 > 570 571 <enum 14 sw_frame_group_mgmt_1010 > 572 573 <enum 15 sw_frame_group_mgmt_1011 > 574 575 <enum 16 sw_frame_group_mgmt_1100 > 576 577 <enum 17 sw_frame_group_mgmt_1101 > 578 579 <enum 18 sw_frame_group_mgmt_1110 > 580 581 <enum 19 sw_frame_group_mgmt_1111 > 582 583 584 585 <enum 20 sw_frame_group_ctrl_0000 > 586 587 <enum 21 sw_frame_group_ctrl_0001 > 588 589 <enum 22 sw_frame_group_ctrl_0010 > 590 591 <enum 23 sw_frame_group_ctrl_0011 > 592 593 <enum 24 sw_frame_group_ctrl_0100 > 594 595 <enum 25 sw_frame_group_ctrl_0101 > 596 597 <enum 26 sw_frame_group_ctrl_0110 > 598 599 <enum 27 sw_frame_group_ctrl_0111 > 600 601 <enum 28 sw_frame_group_ctrl_1000 > 602 603 <enum 29 sw_frame_group_ctrl_1001 > 604 605 <enum 30 sw_frame_group_ctrl_1010 > 606 607 <enum 31 sw_frame_group_ctrl_1011 > 608 609 <enum 32 sw_frame_group_ctrl_1100 > 610 611 <enum 33 sw_frame_group_ctrl_1101 > 612 613 <enum 34 sw_frame_group_ctrl_1110 > 614 615 <enum 35 sw_frame_group_ctrl_1111 > 616 617 618 619 <enum 36 sw_frame_group_unsupported> This covers type 3 620 and protocol version != 0 621 622 Note: The corresponding Rxpcu_Mpdu_filter_in_category 623 can only be rxpcu_monitor_other 624 625 626 627 628 Note: The corresponding Rxpcu_Mpdu_filter_in_category 629 can be rxpcu_filter_pass 630 631 632 633 <legal 0-37> 634 635 ndp_frame 636 637 When set, the received frame was an NDP frame, and thus 638 there will be no MPDU data. 639 640 <legal all> 641 642 phy_err 643 644 When set, a PHY error was received before MAC received 645 any data, and thus there will be no MPDU data. 646 647 <legal all> 648 649 phy_err_during_mpdu_header 650 651 When set, a PHY error was received before MAC received 652 the complete MPDU header which was needed for proper 653 decoding 654 655 <legal all> 656 657 protocol_version_err 658 659 Set when RXPCU detected a version error in the Frame 660 control field 661 662 <legal all> 663 664 ast_based_lookup_valid 665 666 When set, AST based lookup for this frame has found a 667 valid result. 668 669 670 671 Note that for NDP frame this will never be set 672 673 <legal all> 674 675 reserved_9a 676 677 <legal 0> 678 679 phy_ppdu_id 680 681 A ppdu counter value that PHY increments for every PPDU 682 received. The counter value wraps around 683 684 <legal all> 685 686 ast_index 687 688 This field indicates the index of the AST entry 689 corresponding to this MPDU. It is provided by the GSE module 690 instantiated in RXPCU. 691 692 A value of 0xFFFF indicates an invalid AST index, 693 meaning that No AST entry was found or NO AST search was 694 performed 695 696 697 698 In case of ndp or phy_err, this field will be set to 699 0xFFFF 700 701 <legal all> 702 703 sw_peer_id 704 705 In case of ndp or phy_err or AST_based_lookup_valid == 706 0, this field will be set to 0 707 708 709 710 This field indicates a unique peer identifier. It is set 711 equal to field 'sw_peer_id' from the AST entry 712 713 714 715 <legal all> 716 717 mpdu_frame_control_valid 718 719 When set, the field Mpdu_Frame_control_field has valid 720 information 721 722 723 724 725 <legal all> 726 727 mpdu_duration_valid 728 729 When set, the field Mpdu_duration_field has valid 730 information 731 732 733 734 735 <legal all> 736 737 mac_addr_ad1_valid 738 739 When set, the fields mac_addr_ad1_..... have valid 740 information 741 742 743 744 745 <legal all> 746 747 mac_addr_ad2_valid 748 749 When set, the fields mac_addr_ad2_..... have valid 750 information 751 752 753 754 755 756 757 758 <legal all> 759 760 mac_addr_ad3_valid 761 762 When set, the fields mac_addr_ad3_..... have valid 763 information 764 765 766 767 768 769 770 771 <legal all> 772 773 mac_addr_ad4_valid 774 775 When set, the fields mac_addr_ad4_..... have valid 776 information 777 778 779 780 781 782 783 784 <legal all> 785 786 mpdu_sequence_control_valid 787 788 When set, the fields mpdu_sequence_control_field and 789 mpdu_sequence_number have valid information as well as field 790 791 792 793 For MPDUs without a sequence control field, this field 794 will not be set. 795 796 797 798 799 <legal all> 800 801 mpdu_qos_control_valid 802 803 When set, the field mpdu_qos_control_field has valid 804 information 805 806 807 808 For MPDUs without a QoS control field, this field will 809 not be set. 810 811 812 813 814 <legal all> 815 816 mpdu_ht_control_valid 817 818 When set, the field mpdu_HT_control_field has valid 819 information 820 821 822 823 For MPDUs without a HT control field, this field will 824 not be set. 825 826 827 828 829 <legal all> 830 831 frame_encryption_info_valid 832 833 When set, the encryption related info fields, like IV 834 and PN are valid 835 836 837 838 For MPDUs that are not encrypted, this will not be set. 839 840 841 842 843 <legal all> 844 845 mpdu_fragment_number 846 847 Field only valid when Mpdu_sequence_control_valid is set 848 AND Fragment_flag is set 849 850 851 852 The fragment number from the 802.11 header 853 854 855 856 <legal all> 857 858 more_fragment_flag 859 860 The More Fragment bit setting from the MPDU header of 861 the received frame 862 863 864 865 <legal all> 866 867 reserved_11a 868 869 <legal 0> 870 871 fr_ds 872 873 Field only valid when Mpdu_frame_control_valid is set 874 875 876 877 Set if the from DS bit is set in the frame control. 878 879 <legal all> 880 881 to_ds 882 883 Field only valid when Mpdu_frame_control_valid is set 884 885 886 887 Set if the to DS bit is set in the frame control. 888 889 <legal all> 890 891 encrypted 892 893 Field only valid when Mpdu_frame_control_valid is set. 894 895 896 897 Protected bit from the frame control. 898 899 <legal all> 900 901 mpdu_retry 902 903 Field only valid when Mpdu_frame_control_valid is set. 904 905 906 907 Retry bit from the frame control. Only valid when 908 first_msdu is set. 909 910 <legal all> 911 912 mpdu_sequence_number 913 914 Field only valid when Mpdu_sequence_control_valid is 915 set. 916 917 918 919 The sequence number from the 802.11 header. 920 921 <legal all> 922 923 key_id_octet 924 925 926 927 928 The key ID octet from the IV. 929 930 931 932 In case of ndp or phy_err or AST_based_lookup_valid == 933 0, this field will be set to 0 934 935 <legal all> 936 937 new_peer_entry 938 939 In case of ndp or phy_err or AST_based_lookup_valid == 940 0, this field will be set to 0 941 942 943 944 Set if new RX_PEER_ENTRY TLV follows. If clear, 945 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 946 uses old peer entry or not decrypt. 947 948 <legal all> 949 950 decrypt_needed 951 952 In case of ndp or phy_err or AST_based_lookup_valid == 953 0, this field will be set to 0 954 955 956 957 Set if decryption is needed. 958 959 960 961 Note: 962 963 When RXPCU sets bit 'ast_index_not_found' and/or 964 ast_index_timeout', RXPCU will also ensure that this bit is 965 NOT set 966 967 CRYPTO for that reason only needs to evaluate this bit 968 and non of the other ones. 969 970 <legal all> 971 972 decap_type 973 974 In case of ndp or phy_err or AST_based_lookup_valid == 975 0, this field will be set to 0 976 977 978 979 Used by the OLE during decapsulation. 980 981 982 983 Indicates the decapsulation that HW will perform: 984 985 986 987 <enum 0 RAW> No encapsulation 988 989 <enum 1 Native_WiFi> 990 991 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 992 SNAP/LLC) 993 994 <enum 3 802_3> Indicate Ethernet 995 996 997 998 <legal all> 999 1000 rx_insert_vlan_c_tag_padding 1001 1002 In case of ndp or phy_err or AST_based_lookup_valid == 1003 0, this field will be set to 0 1004 1005 1006 1007 Insert 4 byte of all zeros as VLAN tag if the rx payload 1008 does not have VLAN. Used during decapsulation. 1009 1010 <legal all> 1011 1012 rx_insert_vlan_s_tag_padding 1013 1014 In case of ndp or phy_err or AST_based_lookup_valid == 1015 0, this field will be set to 0 1016 1017 1018 1019 Insert 4 byte of all zeros as double VLAN tag if the rx 1020 payload does not have VLAN. Used during 1021 1022 <legal all> 1023 1024 strip_vlan_c_tag_decap 1025 1026 In case of ndp or phy_err or AST_based_lookup_valid == 1027 0, this field will be set to 0 1028 1029 1030 1031 Strip the VLAN during decapsulation. Used by the OLE. 1032 1033 <legal all> 1034 1035 strip_vlan_s_tag_decap 1036 1037 In case of ndp or phy_err or AST_based_lookup_valid == 1038 0, this field will be set to 0 1039 1040 1041 1042 Strip the double VLAN during decapsulation. Used by 1043 the OLE. 1044 1045 <legal all> 1046 1047 pre_delim_count 1048 1049 The number of delimiters before this MPDU. 1050 1051 1052 1053 Note that this number is cleared at PPDU start. 1054 1055 1056 1057 If this MPDU is the first received MPDU in the PPDU and 1058 this MPDU gets filtered-in, this field will indicate the 1059 number of delimiters located after the last MPDU in the 1060 previous PPDU. 1061 1062 1063 1064 If this MPDU is located after the first received MPDU in 1065 an PPDU, this field will indicate the number of delimiters 1066 located between the previous MPDU and this MPDU. 1067 1068 1069 1070 In case of ndp or phy_err, this field will indicate the 1071 number of delimiters located after the last MPDU in the 1072 previous PPDU. 1073 1074 <legal all> 1075 1076 ampdu_flag 1077 1078 When set, received frame was part of an A-MPDU. 1079 1080 1081 1082 1083 <legal all> 1084 1085 bar_frame 1086 1087 In case of ndp or phy_err or AST_based_lookup_valid == 1088 0, this field will be set to 0 1089 1090 1091 1092 When set, received frame is a BAR frame 1093 1094 <legal all> 1095 1096 raw_mpdu 1097 1098 Consumer: SW 1099 1100 Producer: RXOLE 1101 1102 1103 1104 RXPCU sets this field to 0 and RXOLE overwrites it. 1105 1106 1107 1108 Set to 1 by RXOLE when it has not performed any 802.11 1109 to Ethernet/Natvie WiFi header conversion on this MPDU. 1110 1111 <legal all> 1112 1113 reserved_12 1114 1115 <legal 0> 1116 1117 mpdu_length 1118 1119 In case of ndp or phy_err this field will be set to 0 1120 1121 1122 1123 MPDU length before decapsulation. 1124 1125 <legal all> 1126 1127 first_mpdu 1128 1129 See definition in RX attention descriptor 1130 1131 1132 1133 In case of ndp or phy_err, this field will be set. Note 1134 however that there will not actually be any data contents in 1135 the MPDU. 1136 1137 <legal all> 1138 1139 mcast_bcast 1140 1141 In case of ndp or phy_err or Phy_err_during_mpdu_header 1142 this field will be set to 0 1143 1144 1145 1146 See definition in RX attention descriptor 1147 1148 <legal all> 1149 1150 ast_index_not_found 1151 1152 In case of ndp or phy_err or Phy_err_during_mpdu_header 1153 this field will be set to 0 1154 1155 1156 1157 See definition in RX attention descriptor 1158 1159 <legal all> 1160 1161 ast_index_timeout 1162 1163 In case of ndp or phy_err or Phy_err_during_mpdu_header 1164 this field will be set to 0 1165 1166 1167 1168 See definition in RX attention descriptor 1169 1170 <legal all> 1171 1172 power_mgmt 1173 1174 In case of ndp or phy_err or Phy_err_during_mpdu_header 1175 this field will be set to 0 1176 1177 1178 1179 See definition in RX attention descriptor 1180 1181 <legal all> 1182 1183 non_qos 1184 1185 In case of ndp or phy_err or Phy_err_during_mpdu_header 1186 this field will be set to 1 1187 1188 1189 1190 See definition in RX attention descriptor 1191 1192 <legal all> 1193 1194 null_data 1195 1196 In case of ndp or phy_err or Phy_err_during_mpdu_header 1197 this field will be set to 0 1198 1199 1200 1201 See definition in RX attention descriptor 1202 1203 <legal all> 1204 1205 mgmt_type 1206 1207 In case of ndp or phy_err or Phy_err_during_mpdu_header 1208 this field will be set to 0 1209 1210 1211 1212 See definition in RX attention descriptor 1213 1214 <legal all> 1215 1216 ctrl_type 1217 1218 In case of ndp or phy_err or Phy_err_during_mpdu_header 1219 this field will be set to 0 1220 1221 1222 1223 See definition in RX attention descriptor 1224 1225 <legal all> 1226 1227 more_data 1228 1229 In case of ndp or phy_err or Phy_err_during_mpdu_header 1230 this field will be set to 0 1231 1232 1233 1234 See definition in RX attention descriptor 1235 1236 <legal all> 1237 1238 eosp 1239 1240 In case of ndp or phy_err or Phy_err_during_mpdu_header 1241 this field will be set to 0 1242 1243 1244 1245 See definition in RX attention descriptor 1246 1247 <legal all> 1248 1249 fragment_flag 1250 1251 In case of ndp or phy_err or Phy_err_during_mpdu_header 1252 this field will be set to 0 1253 1254 1255 1256 See definition in RX attention descriptor 1257 1258 <legal all> 1259 1260 order 1261 1262 In case of ndp or phy_err or Phy_err_during_mpdu_header 1263 this field will be set to 0 1264 1265 1266 1267 See definition in RX attention descriptor 1268 1269 1270 1271 <legal all> 1272 1273 u_apsd_trigger 1274 1275 In case of ndp or phy_err or Phy_err_during_mpdu_header 1276 this field will be set to 0 1277 1278 1279 1280 See definition in RX attention descriptor 1281 1282 <legal all> 1283 1284 encrypt_required 1285 1286 In case of ndp or phy_err or Phy_err_during_mpdu_header 1287 this field will be set to 0 1288 1289 1290 1291 See definition in RX attention descriptor 1292 1293 <legal all> 1294 1295 directed 1296 1297 In case of ndp or phy_err or Phy_err_during_mpdu_header 1298 this field will be set to 0 1299 1300 1301 1302 See definition in RX attention descriptor 1303 1304 <legal all> 1305 1306 amsdu_present 1307 1308 Field only valid when Mpdu_qos_control_valid is set 1309 1310 1311 1312 The 'amsdu_present' bit within the QoS control field of 1313 the MPDU 1314 1315 <legal all> 1316 1317 reserved_13 1318 1319 <legal 0> 1320 1321 mpdu_frame_control_field 1322 1323 Field only valid when Mpdu_frame_control_valid is set 1324 1325 1326 1327 The frame control field of this received MPDU. 1328 1329 1330 1331 Field only valid when Ndp_frame and phy_err are NOT set 1332 1333 1334 1335 Bytes 0 + 1 of the received MPDU 1336 1337 <legal all> 1338 1339 mpdu_duration_field 1340 1341 Field only valid when Mpdu_duration_valid is set 1342 1343 1344 1345 The duration field of this received MPDU. 1346 1347 <legal all> 1348 1349 mac_addr_ad1_31_0 1350 1351 Field only valid when mac_addr_ad1_valid is set 1352 1353 1354 1355 The Least Significant 4 bytes of the Received Frames MAC 1356 Address AD1 1357 1358 <legal all> 1359 1360 mac_addr_ad1_47_32 1361 1362 Field only valid when mac_addr_ad1_valid is set 1363 1364 1365 1366 The 2 most significant bytes of the Received Frames MAC 1367 Address AD1 1368 1369 <legal all> 1370 1371 mac_addr_ad2_15_0 1372 1373 Field only valid when mac_addr_ad2_valid is set 1374 1375 1376 1377 The Least Significant 2 bytes of the Received Frames MAC 1378 Address AD2 1379 1380 <legal all> 1381 1382 mac_addr_ad2_47_16 1383 1384 Field only valid when mac_addr_ad2_valid is set 1385 1386 1387 1388 The 4 most significant bytes of the Received Frames MAC 1389 Address AD2 1390 1391 <legal all> 1392 1393 mac_addr_ad3_31_0 1394 1395 Field only valid when mac_addr_ad3_valid is set 1396 1397 1398 1399 The Least Significant 4 bytes of the Received Frames MAC 1400 Address AD3 1401 1402 <legal all> 1403 1404 mac_addr_ad3_47_32 1405 1406 Field only valid when mac_addr_ad3_valid is set 1407 1408 1409 1410 The 2 most significant bytes of the Received Frames MAC 1411 Address AD3 1412 1413 <legal all> 1414 1415 mpdu_sequence_control_field 1416 1417 1418 1419 1420 The sequence control field of the MPDU 1421 1422 <legal all> 1423 1424 mac_addr_ad4_31_0 1425 1426 Field only valid when mac_addr_ad4_valid is set 1427 1428 1429 1430 The Least Significant 4 bytes of the Received Frames MAC 1431 Address AD4 1432 1433 <legal all> 1434 1435 mac_addr_ad4_47_32 1436 1437 Field only valid when mac_addr_ad4_valid is set 1438 1439 1440 1441 The 2 most significant bytes of the Received Frames MAC 1442 Address AD4 1443 1444 <legal all> 1445 1446 mpdu_qos_control_field 1447 1448 Field only valid when mpdu_qos_control_valid is set 1449 1450 1451 1452 The sequence control field of the MPDU 1453 1454 <legal all> 1455 1456 mpdu_ht_control_field 1457 1458 Field only valid when mpdu_qos_control_valid is set 1459 1460 1461 1462 The HT control field of the MPDU 1463 1464 <legal all> 1465 */ 1466 1467 1468 /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ 1469 1470 1471 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION 1472 1473 The ID of the REO exit ring where the MSDU frame shall 1474 push after (MPDU level) reordering has finished. 1475 1476 1477 1478 <enum 0 reo_destination_tcl> Reo will push the frame 1479 into the REO2TCL ring 1480 1481 <enum 1 reo_destination_sw1> Reo will push the frame 1482 into the REO2SW1 ring 1483 1484 <enum 2 reo_destination_sw2> Reo will push the frame 1485 into the REO2SW2 ring 1486 1487 <enum 3 reo_destination_sw3> Reo will push the frame 1488 into the REO2SW3 ring 1489 1490 <enum 4 reo_destination_sw4> Reo will push the frame 1491 into the REO2SW4 ring 1492 1493 <enum 5 reo_destination_release> Reo will push the frame 1494 into the REO_release ring 1495 1496 <enum 6 reo_destination_fw> Reo will push the frame into 1497 the REO2FW ring 1498 1499 <enum 7 reo_destination_sw5> Reo will push the frame 1500 into the REO2SW5 ring (REO remaps this in chips without 1501 REO2SW5 ring, e.g. Pine) 1502 1503 <enum 8 reo_destination_sw6> Reo will push the frame 1504 into the REO2SW6 ring (REO remaps this in chips without 1505 REO2SW6 ring, e.g. Pine) 1506 1507 <enum 9 reo_destination_9> REO remaps this <enum 10 1508 reo_destination_10> REO remaps this 1509 1510 <enum 11 reo_destination_11> REO remaps this 1511 1512 <enum 12 reo_destination_12> REO remaps this <enum 13 1513 reo_destination_13> REO remaps this 1514 1515 <enum 14 reo_destination_14> REO remaps this 1516 1517 <enum 15 reo_destination_15> REO remaps this 1518 1519 <enum 16 reo_destination_16> REO remaps this 1520 1521 <enum 17 reo_destination_17> REO remaps this 1522 1523 <enum 18 reo_destination_18> REO remaps this 1524 1525 <enum 19 reo_destination_19> REO remaps this 1526 1527 <enum 20 reo_destination_20> REO remaps this 1528 1529 <enum 21 reo_destination_21> REO remaps this 1530 1531 <enum 22 reo_destination_22> REO remaps this 1532 1533 <enum 23 reo_destination_23> REO remaps this 1534 1535 <enum 24 reo_destination_24> REO remaps this 1536 1537 <enum 25 reo_destination_25> REO remaps this 1538 1539 <enum 26 reo_destination_26> REO remaps this 1540 1541 <enum 27 reo_destination_27> REO remaps this 1542 1543 <enum 28 reo_destination_28> REO remaps this 1544 1545 <enum 29 reo_destination_29> REO remaps this 1546 1547 <enum 30 reo_destination_30> REO remaps this 1548 1549 <enum 31 reo_destination_31> REO remaps this 1550 1551 1552 1553 <legal all> 1554 */ 1555 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 1556 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 1557 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 1558 1559 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB 1560 1561 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 1562 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 1563 hash[3:0]} using the chosen Toeplitz hash from Common Parser 1564 if flow search fails. 1565 1566 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 1567 's not 2'b00, Rx OLE uses a REO desination indication of 1568 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash 1569 from Common Parser if flow search fails. 1570 1571 This LMAC/peer-based routing is not supported in 1572 Hastings80 and HastingsPrime. 1573 1574 <legal all> 1575 */ 1576 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 1577 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 1578 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 1579 1580 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY 1581 1582 Indication to Rx OLE to enable REO destination routing 1583 based on the chosen Toeplitz hash from Common Parser, in 1584 case flow search fails 1585 1586 <legal all> 1587 */ 1588 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 1589 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 1590 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 1591 1592 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA 1593 1594 Filter pass Unicast data frame (matching 1595 rxpcu_filter_pass and sw_frame_group_Unicast_data) routing 1596 selection 1597 1598 1599 1600 1'b0: source and destination rings are selected from the 1601 RxOLE register settings for the packet type 1602 1603 1604 1605 1'b1: source ring and destination ring is selected from 1606 the rxdma0_source_ring_selection and 1607 rxdma0_destination_ring_selection fields in this STRUCT 1608 1609 <legal all> 1610 */ 1611 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 1612 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 1613 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 1614 1615 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA 1616 1617 Filter pass Multicast data frame (matching 1618 rxpcu_filter_pass and sw_frame_group_Multicast_data) routing 1619 selection 1620 1621 1622 1623 1'b0: source and destination rings are selected from the 1624 RxOLE register settings for the packet type 1625 1626 1627 1628 1'b1: source ring and destination ring is selected from 1629 the rxdma0_source_ring_selection and 1630 rxdma0_destination_ring_selection fields in this STRUCT 1631 1632 <legal all> 1633 */ 1634 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 1635 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 1636 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 1637 1638 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 1639 1640 Filter pass BAR frame (matching rxpcu_filter_pass and 1641 sw_frame_group_ctrl_1000) routing selection 1642 1643 1644 1645 1'b0: source and destination rings are selected from the 1646 RxOLE register settings for the packet type 1647 1648 1649 1650 1'b1: source ring and destination ring is selected from 1651 the rxdma0_source_ring_selection and 1652 rxdma0_destination_ring_selection fields in this STRUCT 1653 1654 <legal all> 1655 */ 1656 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 1657 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 1658 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 1659 1660 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION 1661 1662 Field only valid when for the received frame type the 1663 corresponding pkt_selection_fp_... bit is set 1664 1665 1666 1667 <enum 0 wbm2rxdma_buf_source_ring> The data buffer for 1668 1669 <enum 1 fw2rxdma_buf_source_ring> The data buffer for 1670 this frame shall be sourced by fw2rxdma buffer source ring. 1671 1672 <enum 2 sw2rxdma_buf_source_ring> The data buffer for 1673 this frame shall be sourced by sw2rxdma buffer source ring. 1674 1675 <enum 3 no_buffer_ring> The frame shall not be written 1676 to any data buffer. 1677 1678 1679 1680 <legal all> 1681 */ 1682 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 1683 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 1684 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 1685 1686 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION 1687 1688 Field only valid when for the received frame type the 1689 corresponding pkt_selection_fp_... bit is set 1690 1691 1692 1693 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 1694 to the Release ring. Effectively this means the frame needs 1695 to be dropped. 1696 1697 <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to 1698 the FW ring. 1699 1700 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to 1701 the SW ring. 1702 1703 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 1704 the REO entrance ring. 1705 1706 1707 1708 <legal all> 1709 */ 1710 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 1711 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 1712 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 1713 1714 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B 1715 1716 <legal 0> 1717 */ 1718 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 1719 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 1720 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 1721 1722 /* Description RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0 1723 1724 In case of ndp or phy_err or AST_based_lookup_valid == 1725 0, this field will be set to 0 1726 1727 1728 1729 Address (lower 32 bits) of the REO queue descriptor. 1730 1731 1732 1733 If no Peer entry lookup happened for this frame, the 1734 value wil be set to 0, and the frame shall never be pushed 1735 to REO entrance ring. 1736 1737 <legal all> 1738 */ 1739 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 1740 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 1741 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 1742 1743 /* Description RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32 1744 1745 In case of ndp or phy_err or AST_based_lookup_valid == 1746 0, this field will be set to 0 1747 1748 1749 1750 Address (upper 8 bits) of the REO queue descriptor. 1751 1752 1753 1754 If no Peer entry lookup happened for this frame, the 1755 value wil be set to 0, and the frame shall never be pushed 1756 to REO entrance ring. 1757 1758 <legal all> 1759 */ 1760 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 1761 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1762 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1763 1764 /* Description RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER 1765 1766 In case of ndp or phy_err or AST_based_lookup_valid == 1767 0, this field will be set to 0 1768 1769 1770 1771 Indicates the MPDU queue ID to which this MPDU link 1772 descriptor belongs 1773 1774 Used for tracking and debugging 1775 1776 <legal all> 1777 */ 1778 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 1779 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8 1780 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 1781 1782 /* Description RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING 1783 1784 Indicates that a delimiter FCS error was found in 1785 between the Previous MPDU and this MPDU. 1786 1787 1788 1789 Note that this is just a warning, and does not mean that 1790 this MPDU is corrupted in any way. If it is, there will be 1791 other errors indicated such as FCS or decrypt errors 1792 1793 1794 1795 In case of ndp or phy_err, this field will indicate at 1796 least one of delimiters located after the last MPDU in the 1797 previous PPDU has been corrupted. 1798 */ 1799 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 1800 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24 1801 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000 1802 1803 /* Description RX_MPDU_INFO_2_FIRST_DELIM_ERR 1804 1805 Indicates that the first delimiter had a FCS failure. 1806 Only valid when first_mpdu and first_msdu are set. 1807 1808 1809 1810 */ 1811 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008 1812 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25 1813 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000 1814 1815 /* Description RX_MPDU_INFO_2_RESERVED_2A 1816 1817 <legal 0> 1818 */ 1819 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 1820 #define RX_MPDU_INFO_2_RESERVED_2A_LSB 26 1821 #define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000 1822 1823 /* Description RX_MPDU_INFO_3_PN_31_0 1824 1825 1826 1827 1828 1829 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 1830 is valid. 1831 1832 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 1833 WEPSeed[1], pn1}. Only pn[47:0] is valid. 1834 1835 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 1836 pn1, pn0}. Only pn[47:0] is valid. 1837 1838 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 1839 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 1840 pn0}. pn[127:0] are valid. 1841 1842 1843 1844 */ 1845 #define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c 1846 #define RX_MPDU_INFO_3_PN_31_0_LSB 0 1847 #define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff 1848 1849 /* Description RX_MPDU_INFO_4_PN_63_32 1850 1851 1852 1853 1854 Bits [63:32] of the PN number. See description for 1855 pn_31_0. 1856 1857 1858 1859 */ 1860 #define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010 1861 #define RX_MPDU_INFO_4_PN_63_32_LSB 0 1862 #define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff 1863 1864 /* Description RX_MPDU_INFO_5_PN_95_64 1865 1866 1867 1868 1869 Bits [95:64] of the PN number. See description for 1870 pn_31_0. 1871 1872 1873 1874 */ 1875 #define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014 1876 #define RX_MPDU_INFO_5_PN_95_64_LSB 0 1877 #define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff 1878 1879 /* Description RX_MPDU_INFO_6_PN_127_96 1880 1881 1882 1883 1884 Bits [127:96] of the PN number. See description for 1885 pn_31_0. 1886 1887 1888 1889 */ 1890 #define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018 1891 #define RX_MPDU_INFO_6_PN_127_96_LSB 0 1892 #define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff 1893 1894 /* Description RX_MPDU_INFO_7_EPD_EN 1895 1896 Field only valid when AST_based_lookup_valid == 1. 1897 1898 1899 1900 1901 1902 In case of ndp or phy_err or AST_based_lookup_valid == 1903 0, this field will be set to 0 1904 1905 1906 1907 If set to one use EPD instead of LPD 1908 1909 1910 1911 1912 <legal all> 1913 */ 1914 #define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c 1915 #define RX_MPDU_INFO_7_EPD_EN_LSB 0 1916 #define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001 1917 1918 /* Description RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED 1919 1920 In case of ndp or phy_err or AST_based_lookup_valid == 1921 0, this field will be set to 0 1922 1923 1924 1925 When set, all frames (data only ?) shall be encrypted. 1926 If not, RX CRYPTO shall set an error flag. 1927 1928 <legal all> 1929 */ 1930 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 1931 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 1932 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 1933 1934 /* Description RX_MPDU_INFO_7_ENCRYPT_TYPE 1935 1936 In case of ndp or phy_err or AST_based_lookup_valid == 1937 0, this field will be set to 0 1938 1939 1940 1941 Indicates type of decrypt cipher used (as defined in the 1942 peer entry) 1943 1944 1945 1946 <enum 0 wep_40> WEP 40-bit 1947 1948 <enum 1 wep_104> WEP 104-bit 1949 1950 <enum 2 tkip_no_mic> TKIP without MIC 1951 1952 <enum 3 wep_128> WEP 128-bit 1953 1954 <enum 4 tkip_with_mic> TKIP with MIC 1955 1956 <enum 5 wapi> WAPI 1957 1958 <enum 6 aes_ccmp_128> AES CCMP 128 1959 1960 <enum 7 no_cipher> No crypto 1961 1962 <enum 8 aes_ccmp_256> AES CCMP 256 1963 1964 <enum 9 aes_gcmp_128> AES CCMP 128 1965 1966 <enum 10 aes_gcmp_256> AES CCMP 256 1967 1968 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 1969 1970 1971 1972 <enum 12 wep_varied_width> WEP encryption. As for WEP 1973 per keyid the key bit width can vary, the key bit width for 1974 this MPDU will be indicated in field 1975 wep_key_width_for_variable key 1976 1977 <legal 0-12> 1978 */ 1979 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c 1980 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2 1981 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c 1982 1983 /* Description RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 1984 1985 Field only valid when key_type is set to 1986 wep_varied_width. 1987 1988 1989 1990 This field indicates the size of the wep key for this 1991 MPDU. 1992 1993 1994 1995 <enum 0 wep_varied_width_40> WEP 40-bit 1996 1997 <enum 1 wep_varied_width_104> WEP 104-bit 1998 1999 <enum 2 wep_varied_width_128> WEP 128-bit 2000 2001 2002 2003 <legal 0-2> 2004 */ 2005 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 2006 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 2007 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 2008 2009 /* Description RX_MPDU_INFO_7_MESH_STA 2010 2011 In case of ndp or phy_err or AST_based_lookup_valid == 2012 0, this field will be set to 0 2013 2014 2015 2016 When set, this is a Mesh (11s) STA. 2017 2018 2019 2020 The interpretation of the A-MSDU 'Length' field in the 2021 MPDU (if any) is decided by the e-numerations below. 2022 2023 2024 2025 <enum 0 MESH_DISABLE> 2026 2027 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 2028 includes the length of Mesh Control. 2029 2030 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 2031 excludes the length of Mesh Control. 2032 2033 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 2034 and excludes the length of Mesh Control. This is 2035 802.11s-compliant. 2036 2037 <legal all> 2038 */ 2039 #define RX_MPDU_INFO_7_MESH_STA_OFFSET 0x0000001c 2040 #define RX_MPDU_INFO_7_MESH_STA_LSB 8 2041 #define RX_MPDU_INFO_7_MESH_STA_MASK 0x00000300 2042 2043 /* Description RX_MPDU_INFO_7_BSSID_HIT 2044 2045 In case of ndp or phy_err or AST_based_lookup_valid == 2046 0, this field will be set to 0 2047 2048 2049 2050 When set, the BSSID of the incoming frame matched one of 2051 the 8 BSSID register values 2052 2053 2054 2055 <legal all> 2056 */ 2057 #define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c 2058 #define RX_MPDU_INFO_7_BSSID_HIT_LSB 10 2059 #define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400 2060 2061 /* Description RX_MPDU_INFO_7_BSSID_NUMBER 2062 2063 Field only valid when bssid_hit is set. 2064 2065 2066 2067 This number indicates which one out of the 8 BSSID 2068 register values matched the incoming frame 2069 2070 <legal all> 2071 */ 2072 #define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c 2073 #define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11 2074 #define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800 2075 2076 /* Description RX_MPDU_INFO_7_TID 2077 2078 Field only valid when mpdu_qos_control_valid is set 2079 2080 2081 2082 The TID field in the QoS control field 2083 2084 <legal all> 2085 */ 2086 #define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c 2087 #define RX_MPDU_INFO_7_TID_LSB 15 2088 #define RX_MPDU_INFO_7_TID_MASK 0x00078000 2089 2090 /* Description RX_MPDU_INFO_7_RESERVED_7A 2091 2092 <legal 0> 2093 */ 2094 #define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c 2095 #define RX_MPDU_INFO_7_RESERVED_7A_LSB 19 2096 #define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000 2097 2098 /* Description RX_MPDU_INFO_8_PEER_META_DATA 2099 2100 In case of ndp or phy_err or AST_based_lookup_valid == 2101 0, this field will be set to 0 2102 2103 2104 2105 Meta data that SW has programmed in the Peer table entry 2106 of the transmitting STA. 2107 2108 <legal all> 2109 */ 2110 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 2111 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 2112 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 2113 2114 /* Description RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY 2115 2116 Field indicates what the reason was that this MPDU frame 2117 was allowed to come into the receive path by RXPCU 2118 2119 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 2120 frame filter programming of rxpcu 2121 2122 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 2123 regular frame filter and would have been dropped, were it 2124 not for the frame fitting into the 'monitor_client' 2125 category. 2126 2127 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 2128 regular frame filter and also did not pass the 2129 rxpcu_monitor_client filter. It would have been dropped 2130 accept that it did pass the 'monitor_other' category. 2131 2132 2133 2134 Note: for ndp frame, if it was expected because the 2135 preceding NDPA was filter_pass, the setting 2136 rxpcu_filter_pass will be used. This setting will also be 2137 used for every ndp frame in case Promiscuous mode is 2138 enabled. 2139 2140 2141 2142 In case promiscuous is not enabled, and an NDP is not 2143 preceded by a NPDA filter pass frame, the only other setting 2144 that could appear here for the NDP is rxpcu_monitor_other. 2145 2146 (rxpcu has a configuration bit specifically for this 2147 scenario) 2148 2149 2150 2151 Note: for 2152 2153 <legal 0-2> 2154 */ 2155 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 2156 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 2157 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 2158 2159 /* Description RX_MPDU_INFO_9_SW_FRAME_GROUP_ID 2160 2161 SW processes frames based on certain classifications. 2162 This field indicates to what sw classification this MPDU is 2163 mapped. 2164 2165 The classification is given in priority order 2166 2167 2168 2169 <enum 0 sw_frame_group_NDP_frame> Note: The 2170 corresponding Rxpcu_Mpdu_filter_in_category can be 2171 rxpcu_filter_pass or rxpcu_monitor_other 2172 2173 2174 2175 <enum 1 sw_frame_group_Multicast_data> 2176 2177 <enum 2 sw_frame_group_Unicast_data> 2178 2179 <enum 3 sw_frame_group_Null_data > This includes mpdus 2180 of type Data Null as well as QoS Data Null 2181 2182 2183 2184 <enum 4 sw_frame_group_mgmt_0000 > 2185 2186 <enum 5 sw_frame_group_mgmt_0001 > 2187 2188 <enum 6 sw_frame_group_mgmt_0010 > 2189 2190 <enum 7 sw_frame_group_mgmt_0011 > 2191 2192 <enum 8 sw_frame_group_mgmt_0100 > 2193 2194 <enum 9 sw_frame_group_mgmt_0101 > 2195 2196 <enum 10 sw_frame_group_mgmt_0110 > 2197 2198 <enum 11 sw_frame_group_mgmt_0111 > 2199 2200 <enum 12 sw_frame_group_mgmt_1000 > 2201 2202 <enum 13 sw_frame_group_mgmt_1001 > 2203 2204 <enum 14 sw_frame_group_mgmt_1010 > 2205 2206 <enum 15 sw_frame_group_mgmt_1011 > 2207 2208 <enum 16 sw_frame_group_mgmt_1100 > 2209 2210 <enum 17 sw_frame_group_mgmt_1101 > 2211 2212 <enum 18 sw_frame_group_mgmt_1110 > 2213 2214 <enum 19 sw_frame_group_mgmt_1111 > 2215 2216 2217 2218 <enum 20 sw_frame_group_ctrl_0000 > 2219 2220 <enum 21 sw_frame_group_ctrl_0001 > 2221 2222 <enum 22 sw_frame_group_ctrl_0010 > 2223 2224 <enum 23 sw_frame_group_ctrl_0011 > 2225 2226 <enum 24 sw_frame_group_ctrl_0100 > 2227 2228 <enum 25 sw_frame_group_ctrl_0101 > 2229 2230 <enum 26 sw_frame_group_ctrl_0110 > 2231 2232 <enum 27 sw_frame_group_ctrl_0111 > 2233 2234 <enum 28 sw_frame_group_ctrl_1000 > 2235 2236 <enum 29 sw_frame_group_ctrl_1001 > 2237 2238 <enum 30 sw_frame_group_ctrl_1010 > 2239 2240 <enum 31 sw_frame_group_ctrl_1011 > 2241 2242 <enum 32 sw_frame_group_ctrl_1100 > 2243 2244 <enum 33 sw_frame_group_ctrl_1101 > 2245 2246 <enum 34 sw_frame_group_ctrl_1110 > 2247 2248 <enum 35 sw_frame_group_ctrl_1111 > 2249 2250 2251 2252 <enum 36 sw_frame_group_unsupported> This covers type 3 2253 and protocol version != 0 2254 2255 Note: The corresponding Rxpcu_Mpdu_filter_in_category 2256 can only be rxpcu_monitor_other 2257 2258 2259 2260 2261 Note: The corresponding Rxpcu_Mpdu_filter_in_category 2262 can be rxpcu_filter_pass 2263 2264 2265 2266 <legal 0-37> 2267 */ 2268 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024 2269 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2 2270 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc 2271 2272 /* Description RX_MPDU_INFO_9_NDP_FRAME 2273 2274 When set, the received frame was an NDP frame, and thus 2275 there will be no MPDU data. 2276 2277 <legal all> 2278 */ 2279 #define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024 2280 #define RX_MPDU_INFO_9_NDP_FRAME_LSB 9 2281 #define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200 2282 2283 /* Description RX_MPDU_INFO_9_PHY_ERR 2284 2285 When set, a PHY error was received before MAC received 2286 any data, and thus there will be no MPDU data. 2287 2288 <legal all> 2289 */ 2290 #define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024 2291 #define RX_MPDU_INFO_9_PHY_ERR_LSB 10 2292 #define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400 2293 2294 /* Description RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER 2295 2296 When set, a PHY error was received before MAC received 2297 the complete MPDU header which was needed for proper 2298 decoding 2299 2300 <legal all> 2301 */ 2302 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 2303 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11 2304 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 2305 2306 /* Description RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR 2307 2308 Set when RXPCU detected a version error in the Frame 2309 control field 2310 2311 <legal all> 2312 */ 2313 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 2314 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12 2315 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000 2316 2317 /* Description RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID 2318 2319 When set, AST based lookup for this frame has found a 2320 valid result. 2321 2322 2323 2324 Note that for NDP frame this will never be set 2325 2326 <legal all> 2327 */ 2328 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 2329 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13 2330 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000 2331 2332 /* Description RX_MPDU_INFO_9_RESERVED_9A 2333 2334 <legal 0> 2335 */ 2336 #define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024 2337 #define RX_MPDU_INFO_9_RESERVED_9A_LSB 14 2338 #define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000 2339 2340 /* Description RX_MPDU_INFO_9_PHY_PPDU_ID 2341 2342 A ppdu counter value that PHY increments for every PPDU 2343 received. The counter value wraps around 2344 2345 <legal all> 2346 */ 2347 #define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024 2348 #define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16 2349 #define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000 2350 2351 /* Description RX_MPDU_INFO_10_AST_INDEX 2352 2353 This field indicates the index of the AST entry 2354 corresponding to this MPDU. It is provided by the GSE module 2355 instantiated in RXPCU. 2356 2357 A value of 0xFFFF indicates an invalid AST index, 2358 meaning that No AST entry was found or NO AST search was 2359 performed 2360 2361 2362 2363 In case of ndp or phy_err, this field will be set to 2364 0xFFFF 2365 2366 <legal all> 2367 */ 2368 #define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028 2369 #define RX_MPDU_INFO_10_AST_INDEX_LSB 0 2370 #define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff 2371 2372 /* Description RX_MPDU_INFO_10_SW_PEER_ID 2373 2374 In case of ndp or phy_err or AST_based_lookup_valid == 2375 0, this field will be set to 0 2376 2377 2378 2379 This field indicates a unique peer identifier. It is set 2380 equal to field 'sw_peer_id' from the AST entry 2381 2382 2383 2384 <legal all> 2385 */ 2386 #define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028 2387 #define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16 2388 #define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000 2389 2390 /* Description RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID 2391 2392 When set, the field Mpdu_Frame_control_field has valid 2393 information 2394 2395 2396 2397 2398 <legal all> 2399 */ 2400 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 2401 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0 2402 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 2403 2404 /* Description RX_MPDU_INFO_11_MPDU_DURATION_VALID 2405 2406 When set, the field Mpdu_duration_field has valid 2407 information 2408 2409 2410 2411 2412 <legal all> 2413 */ 2414 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c 2415 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1 2416 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002 2417 2418 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID 2419 2420 When set, the fields mac_addr_ad1_..... have valid 2421 information 2422 2423 2424 2425 2426 <legal all> 2427 */ 2428 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 2429 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2 2430 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004 2431 2432 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID 2433 2434 When set, the fields mac_addr_ad2_..... have valid 2435 information 2436 2437 2438 2439 2440 2441 2442 2443 <legal all> 2444 */ 2445 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 2446 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3 2447 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008 2448 2449 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID 2450 2451 When set, the fields mac_addr_ad3_..... have valid 2452 information 2453 2454 2455 2456 2457 2458 2459 2460 <legal all> 2461 */ 2462 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 2463 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4 2464 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010 2465 2466 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID 2467 2468 When set, the fields mac_addr_ad4_..... have valid 2469 information 2470 2471 2472 2473 2474 2475 2476 2477 <legal all> 2478 */ 2479 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 2480 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5 2481 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020 2482 2483 /* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID 2484 2485 When set, the fields mpdu_sequence_control_field and 2486 mpdu_sequence_number have valid information as well as field 2487 2488 2489 2490 For MPDUs without a sequence control field, this field 2491 will not be set. 2492 2493 2494 2495 2496 <legal all> 2497 */ 2498 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 2499 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 2500 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 2501 2502 /* Description RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID 2503 2504 When set, the field mpdu_qos_control_field has valid 2505 information 2506 2507 2508 2509 For MPDUs without a QoS control field, this field will 2510 not be set. 2511 2512 2513 2514 2515 <legal all> 2516 */ 2517 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 2518 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7 2519 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 2520 2521 /* Description RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID 2522 2523 When set, the field mpdu_HT_control_field has valid 2524 information 2525 2526 2527 2528 For MPDUs without a HT control field, this field will 2529 not be set. 2530 2531 2532 2533 2534 <legal all> 2535 */ 2536 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 2537 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8 2538 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100 2539 2540 /* Description RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID 2541 2542 When set, the encryption related info fields, like IV 2543 and PN are valid 2544 2545 2546 2547 For MPDUs that are not encrypted, this will not be set. 2548 2549 2550 2551 2552 <legal all> 2553 */ 2554 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 2555 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9 2556 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 2557 2558 /* Description RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER 2559 2560 Field only valid when Mpdu_sequence_control_valid is set 2561 AND Fragment_flag is set 2562 2563 2564 2565 The fragment number from the 802.11 header 2566 2567 2568 2569 <legal all> 2570 */ 2571 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 2572 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10 2573 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 2574 2575 /* Description RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG 2576 2577 The More Fragment bit setting from the MPDU header of 2578 the received frame 2579 2580 2581 2582 <legal all> 2583 */ 2584 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 2585 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14 2586 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000 2587 2588 /* Description RX_MPDU_INFO_11_RESERVED_11A 2589 2590 <legal 0> 2591 */ 2592 #define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c 2593 #define RX_MPDU_INFO_11_RESERVED_11A_LSB 15 2594 #define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000 2595 2596 /* Description RX_MPDU_INFO_11_FR_DS 2597 2598 Field only valid when Mpdu_frame_control_valid is set 2599 2600 2601 2602 Set if the from DS bit is set in the frame control. 2603 2604 <legal all> 2605 */ 2606 #define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c 2607 #define RX_MPDU_INFO_11_FR_DS_LSB 16 2608 #define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000 2609 2610 /* Description RX_MPDU_INFO_11_TO_DS 2611 2612 Field only valid when Mpdu_frame_control_valid is set 2613 2614 2615 2616 Set if the to DS bit is set in the frame control. 2617 2618 <legal all> 2619 */ 2620 #define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c 2621 #define RX_MPDU_INFO_11_TO_DS_LSB 17 2622 #define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000 2623 2624 /* Description RX_MPDU_INFO_11_ENCRYPTED 2625 2626 Field only valid when Mpdu_frame_control_valid is set. 2627 2628 2629 2630 Protected bit from the frame control. 2631 2632 <legal all> 2633 */ 2634 #define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c 2635 #define RX_MPDU_INFO_11_ENCRYPTED_LSB 18 2636 #define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000 2637 2638 /* Description RX_MPDU_INFO_11_MPDU_RETRY 2639 2640 Field only valid when Mpdu_frame_control_valid is set. 2641 2642 2643 2644 Retry bit from the frame control. Only valid when 2645 first_msdu is set. 2646 2647 <legal all> 2648 */ 2649 #define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c 2650 #define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19 2651 #define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000 2652 2653 /* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER 2654 2655 Field only valid when Mpdu_sequence_control_valid is 2656 set. 2657 2658 2659 2660 The sequence number from the 802.11 header. 2661 2662 <legal all> 2663 */ 2664 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 2665 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20 2666 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 2667 2668 /* Description RX_MPDU_INFO_12_KEY_ID_OCTET 2669 2670 2671 2672 2673 The key ID octet from the IV. 2674 2675 2676 2677 In case of ndp or phy_err or AST_based_lookup_valid == 2678 0, this field will be set to 0 2679 2680 <legal all> 2681 */ 2682 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 2683 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 2684 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 2685 2686 /* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY 2687 2688 In case of ndp or phy_err or AST_based_lookup_valid == 2689 0, this field will be set to 0 2690 2691 2692 2693 Set if new RX_PEER_ENTRY TLV follows. If clear, 2694 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 2695 uses old peer entry or not decrypt. 2696 2697 <legal all> 2698 */ 2699 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 2700 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 2701 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 2702 2703 /* Description RX_MPDU_INFO_12_DECRYPT_NEEDED 2704 2705 In case of ndp or phy_err or AST_based_lookup_valid == 2706 0, this field will be set to 0 2707 2708 2709 2710 Set if decryption is needed. 2711 2712 2713 2714 Note: 2715 2716 When RXPCU sets bit 'ast_index_not_found' and/or 2717 ast_index_timeout', RXPCU will also ensure that this bit is 2718 NOT set 2719 2720 CRYPTO for that reason only needs to evaluate this bit 2721 and non of the other ones. 2722 2723 <legal all> 2724 */ 2725 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 2726 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 2727 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 2728 2729 /* Description RX_MPDU_INFO_12_DECAP_TYPE 2730 2731 In case of ndp or phy_err or AST_based_lookup_valid == 2732 0, this field will be set to 0 2733 2734 2735 2736 Used by the OLE during decapsulation. 2737 2738 2739 2740 Indicates the decapsulation that HW will perform: 2741 2742 2743 2744 <enum 0 RAW> No encapsulation 2745 2746 <enum 1 Native_WiFi> 2747 2748 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 2749 SNAP/LLC) 2750 2751 <enum 3 802_3> Indicate Ethernet 2752 2753 2754 2755 <legal all> 2756 */ 2757 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 2758 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 2759 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 2760 2761 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING 2762 2763 In case of ndp or phy_err or AST_based_lookup_valid == 2764 0, this field will be set to 0 2765 2766 2767 2768 Insert 4 byte of all zeros as VLAN tag if the rx payload 2769 does not have VLAN. Used during decapsulation. 2770 2771 <legal all> 2772 */ 2773 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 2774 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 2775 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 2776 2777 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING 2778 2779 In case of ndp or phy_err or AST_based_lookup_valid == 2780 0, this field will be set to 0 2781 2782 2783 2784 Insert 4 byte of all zeros as double VLAN tag if the rx 2785 payload does not have VLAN. Used during 2786 2787 <legal all> 2788 */ 2789 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 2790 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 2791 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 2792 2793 /* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP 2794 2795 In case of ndp or phy_err or AST_based_lookup_valid == 2796 0, this field will be set to 0 2797 2798 2799 2800 Strip the VLAN during decapsulation. Used by the OLE. 2801 2802 <legal all> 2803 */ 2804 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 2805 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 2806 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 2807 2808 /* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP 2809 2810 In case of ndp or phy_err or AST_based_lookup_valid == 2811 0, this field will be set to 0 2812 2813 2814 2815 Strip the double VLAN during decapsulation. Used by 2816 the OLE. 2817 2818 <legal all> 2819 */ 2820 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 2821 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 2822 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 2823 2824 /* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT 2825 2826 The number of delimiters before this MPDU. 2827 2828 2829 2830 Note that this number is cleared at PPDU start. 2831 2832 2833 2834 If this MPDU is the first received MPDU in the PPDU and 2835 this MPDU gets filtered-in, this field will indicate the 2836 number of delimiters located after the last MPDU in the 2837 previous PPDU. 2838 2839 2840 2841 If this MPDU is located after the first received MPDU in 2842 an PPDU, this field will indicate the number of delimiters 2843 located between the previous MPDU and this MPDU. 2844 2845 2846 2847 In case of ndp or phy_err, this field will indicate the 2848 number of delimiters located after the last MPDU in the 2849 previous PPDU. 2850 2851 <legal all> 2852 */ 2853 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 2854 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 2855 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 2856 2857 /* Description RX_MPDU_INFO_12_AMPDU_FLAG 2858 2859 When set, received frame was part of an A-MPDU. 2860 2861 2862 2863 2864 <legal all> 2865 */ 2866 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 2867 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 2868 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 2869 2870 /* Description RX_MPDU_INFO_12_BAR_FRAME 2871 2872 In case of ndp or phy_err or AST_based_lookup_valid == 2873 0, this field will be set to 0 2874 2875 2876 2877 When set, received frame is a BAR frame 2878 2879 <legal all> 2880 */ 2881 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 2882 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 2883 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 2884 2885 /* Description RX_MPDU_INFO_12_RAW_MPDU 2886 2887 Consumer: SW 2888 2889 Producer: RXOLE 2890 2891 2892 2893 RXPCU sets this field to 0 and RXOLE overwrites it. 2894 2895 2896 2897 Set to 1 by RXOLE when it has not performed any 802.11 2898 to Ethernet/Natvie WiFi header conversion on this MPDU. 2899 2900 <legal all> 2901 */ 2902 #define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030 2903 #define RX_MPDU_INFO_12_RAW_MPDU_LSB 30 2904 #define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000 2905 2906 /* Description RX_MPDU_INFO_12_RESERVED_12 2907 2908 <legal 0> 2909 */ 2910 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 2911 #define RX_MPDU_INFO_12_RESERVED_12_LSB 31 2912 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000 2913 2914 /* Description RX_MPDU_INFO_13_MPDU_LENGTH 2915 2916 In case of ndp or phy_err this field will be set to 0 2917 2918 2919 2920 MPDU length before decapsulation. 2921 2922 <legal all> 2923 */ 2924 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 2925 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 2926 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 2927 2928 /* Description RX_MPDU_INFO_13_FIRST_MPDU 2929 2930 See definition in RX attention descriptor 2931 2932 2933 2934 In case of ndp or phy_err, this field will be set. Note 2935 however that there will not actually be any data contents in 2936 the MPDU. 2937 2938 <legal all> 2939 */ 2940 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 2941 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 2942 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 2943 2944 /* Description RX_MPDU_INFO_13_MCAST_BCAST 2945 2946 In case of ndp or phy_err or Phy_err_during_mpdu_header 2947 this field will be set to 0 2948 2949 2950 2951 See definition in RX attention descriptor 2952 2953 <legal all> 2954 */ 2955 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 2956 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 2957 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 2958 2959 /* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND 2960 2961 In case of ndp or phy_err or Phy_err_during_mpdu_header 2962 this field will be set to 0 2963 2964 2965 2966 See definition in RX attention descriptor 2967 2968 <legal all> 2969 */ 2970 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 2971 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 2972 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 2973 2974 /* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT 2975 2976 In case of ndp or phy_err or Phy_err_during_mpdu_header 2977 this field will be set to 0 2978 2979 2980 2981 See definition in RX attention descriptor 2982 2983 <legal all> 2984 */ 2985 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 2986 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 2987 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 2988 2989 /* Description RX_MPDU_INFO_13_POWER_MGMT 2990 2991 In case of ndp or phy_err or Phy_err_during_mpdu_header 2992 this field will be set to 0 2993 2994 2995 2996 See definition in RX attention descriptor 2997 2998 <legal all> 2999 */ 3000 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 3001 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 3002 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 3003 3004 /* Description RX_MPDU_INFO_13_NON_QOS 3005 3006 In case of ndp or phy_err or Phy_err_during_mpdu_header 3007 this field will be set to 1 3008 3009 3010 3011 See definition in RX attention descriptor 3012 3013 <legal all> 3014 */ 3015 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 3016 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 3017 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 3018 3019 /* Description RX_MPDU_INFO_13_NULL_DATA 3020 3021 In case of ndp or phy_err or Phy_err_during_mpdu_header 3022 this field will be set to 0 3023 3024 3025 3026 See definition in RX attention descriptor 3027 3028 <legal all> 3029 */ 3030 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 3031 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 3032 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 3033 3034 /* Description RX_MPDU_INFO_13_MGMT_TYPE 3035 3036 In case of ndp or phy_err or Phy_err_during_mpdu_header 3037 this field will be set to 0 3038 3039 3040 3041 See definition in RX attention descriptor 3042 3043 <legal all> 3044 */ 3045 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 3046 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 3047 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 3048 3049 /* Description RX_MPDU_INFO_13_CTRL_TYPE 3050 3051 In case of ndp or phy_err or Phy_err_during_mpdu_header 3052 this field will be set to 0 3053 3054 3055 3056 See definition in RX attention descriptor 3057 3058 <legal all> 3059 */ 3060 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 3061 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 3062 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 3063 3064 /* Description RX_MPDU_INFO_13_MORE_DATA 3065 3066 In case of ndp or phy_err or Phy_err_during_mpdu_header 3067 this field will be set to 0 3068 3069 3070 3071 See definition in RX attention descriptor 3072 3073 <legal all> 3074 */ 3075 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 3076 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 3077 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 3078 3079 /* Description RX_MPDU_INFO_13_EOSP 3080 3081 In case of ndp or phy_err or Phy_err_during_mpdu_header 3082 this field will be set to 0 3083 3084 3085 3086 See definition in RX attention descriptor 3087 3088 <legal all> 3089 */ 3090 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 3091 #define RX_MPDU_INFO_13_EOSP_LSB 24 3092 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 3093 3094 /* Description RX_MPDU_INFO_13_FRAGMENT_FLAG 3095 3096 In case of ndp or phy_err or Phy_err_during_mpdu_header 3097 this field will be set to 0 3098 3099 3100 3101 See definition in RX attention descriptor 3102 3103 <legal all> 3104 */ 3105 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 3106 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 3107 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 3108 3109 /* Description RX_MPDU_INFO_13_ORDER 3110 3111 In case of ndp or phy_err or Phy_err_during_mpdu_header 3112 this field will be set to 0 3113 3114 3115 3116 See definition in RX attention descriptor 3117 3118 3119 3120 <legal all> 3121 */ 3122 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 3123 #define RX_MPDU_INFO_13_ORDER_LSB 26 3124 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 3125 3126 /* Description RX_MPDU_INFO_13_U_APSD_TRIGGER 3127 3128 In case of ndp or phy_err or Phy_err_during_mpdu_header 3129 this field will be set to 0 3130 3131 3132 3133 See definition in RX attention descriptor 3134 3135 <legal all> 3136 */ 3137 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 3138 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 3139 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 3140 3141 /* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED 3142 3143 In case of ndp or phy_err or Phy_err_during_mpdu_header 3144 this field will be set to 0 3145 3146 3147 3148 See definition in RX attention descriptor 3149 3150 <legal all> 3151 */ 3152 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 3153 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 3154 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 3155 3156 /* Description RX_MPDU_INFO_13_DIRECTED 3157 3158 In case of ndp or phy_err or Phy_err_during_mpdu_header 3159 this field will be set to 0 3160 3161 3162 3163 See definition in RX attention descriptor 3164 3165 <legal all> 3166 */ 3167 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 3168 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 3169 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 3170 3171 /* Description RX_MPDU_INFO_13_AMSDU_PRESENT 3172 3173 Field only valid when Mpdu_qos_control_valid is set 3174 3175 3176 3177 The 'amsdu_present' bit within the QoS control field of 3178 the MPDU 3179 3180 <legal all> 3181 */ 3182 #define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 3183 #define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 3184 #define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 3185 3186 /* Description RX_MPDU_INFO_13_RESERVED_13 3187 3188 <legal 0> 3189 */ 3190 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 3191 #define RX_MPDU_INFO_13_RESERVED_13_LSB 31 3192 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 3193 3194 /* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD 3195 3196 Field only valid when Mpdu_frame_control_valid is set 3197 3198 3199 3200 The frame control field of this received MPDU. 3201 3202 3203 3204 Field only valid when Ndp_frame and phy_err are NOT set 3205 3206 3207 3208 Bytes 0 + 1 of the received MPDU 3209 3210 <legal all> 3211 */ 3212 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 3213 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 3214 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 3215 3216 /* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD 3217 3218 Field only valid when Mpdu_duration_valid is set 3219 3220 3221 3222 The duration field of this received MPDU. 3223 3224 <legal all> 3225 */ 3226 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 3227 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 3228 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 3229 3230 /* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 3231 3232 Field only valid when mac_addr_ad1_valid is set 3233 3234 3235 3236 The Least Significant 4 bytes of the Received Frames MAC 3237 Address AD1 3238 3239 <legal all> 3240 */ 3241 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 3242 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 3243 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 3244 3245 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 3246 3247 Field only valid when mac_addr_ad1_valid is set 3248 3249 3250 3251 The 2 most significant bytes of the Received Frames MAC 3252 Address AD1 3253 3254 <legal all> 3255 */ 3256 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 3257 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 3258 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 3259 3260 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 3261 3262 Field only valid when mac_addr_ad2_valid is set 3263 3264 3265 3266 The Least Significant 2 bytes of the Received Frames MAC 3267 Address AD2 3268 3269 <legal all> 3270 */ 3271 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 3272 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 3273 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 3274 3275 /* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 3276 3277 Field only valid when mac_addr_ad2_valid is set 3278 3279 3280 3281 The 4 most significant bytes of the Received Frames MAC 3282 Address AD2 3283 3284 <legal all> 3285 */ 3286 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 3287 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 3288 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 3289 3290 /* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 3291 3292 Field only valid when mac_addr_ad3_valid is set 3293 3294 3295 3296 The Least Significant 4 bytes of the Received Frames MAC 3297 Address AD3 3298 3299 <legal all> 3300 */ 3301 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 3302 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 3303 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 3304 3305 /* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 3306 3307 Field only valid when mac_addr_ad3_valid is set 3308 3309 3310 3311 The 2 most significant bytes of the Received Frames MAC 3312 Address AD3 3313 3314 <legal all> 3315 */ 3316 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 3317 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 3318 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 3319 3320 /* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD 3321 3322 3323 3324 3325 The sequence control field of the MPDU 3326 3327 <legal all> 3328 */ 3329 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 3330 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 3331 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 3332 3333 /* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 3334 3335 Field only valid when mac_addr_ad4_valid is set 3336 3337 3338 3339 The Least Significant 4 bytes of the Received Frames MAC 3340 Address AD4 3341 3342 <legal all> 3343 */ 3344 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 3345 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 3346 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 3347 3348 /* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 3349 3350 Field only valid when mac_addr_ad4_valid is set 3351 3352 3353 3354 The 2 most significant bytes of the Received Frames MAC 3355 Address AD4 3356 3357 <legal all> 3358 */ 3359 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 3360 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 3361 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 3362 3363 /* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD 3364 3365 Field only valid when mpdu_qos_control_valid is set 3366 3367 3368 3369 The sequence control field of the MPDU 3370 3371 <legal all> 3372 */ 3373 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 3374 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 3375 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 3376 3377 /* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD 3378 3379 Field only valid when mpdu_qos_control_valid is set 3380 3381 3382 3383 The HT control field of the MPDU 3384 3385 <legal all> 3386 */ 3387 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 3388 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 3389 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 3390 3391 3392 #endif // _RX_MPDU_INFO_H_ 3393