1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MSDU_END_H_ 25 #define _RX_MSDU_END_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 34 // 1 ip_hdr_chksum[15:0], reported_mpdu_length[29:16], reserved_1a[31:30] 35 // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], cumulative_l3_checksum[31:16] 36 // 3 rule_indication_31_0[31:0] 37 // 4 rule_indication_63_32[31:0] 38 // 5 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_5a[15:14], l3_type[31:16] 39 // 6 ipv6_options_crc[31:0] 40 // 7 tcp_seq_number[31:0] 41 // 8 tcp_ack_number[31:0] 42 // 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] 43 // 10 tcp_udp_chksum[15:0], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], first_msdu[28], last_msdu[29], tcp_udp_chksum_fail[30], ip_chksum_fail[31] 44 // 11 sa_idx[15:0], da_idx_or_sw_peer_id[31:16] 45 // 12 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_12a[31:26] 46 // 13 fse_metadata[31:0] 47 // 14 cce_metadata[15:0], sa_sw_peer_id[31:16] 48 // 15 aggregation_count[7:0], flow_aggregation_continuation[8], fisa_timeout[9], reserved_15a[31:10] 49 // 16 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16] 50 // 51 // ################ END SUMMARY ################# 52 53 #define NUM_OF_DWORDS_RX_MSDU_END 17 54 55 struct rx_msdu_end { 56 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 57 sw_frame_group_id : 7, //[8:2] 58 reserved_0 : 7, //[15:9] 59 phy_ppdu_id : 16; //[31:16] 60 uint32_t ip_hdr_chksum : 16, //[15:0] 61 reported_mpdu_length : 14, //[29:16] 62 reserved_1a : 2; //[31:30] 63 uint32_t key_id_octet : 8, //[7:0] 64 cce_super_rule : 6, //[13:8] 65 cce_classify_not_done_truncate : 1, //[14] 66 cce_classify_not_done_cce_dis : 1, //[15] 67 cumulative_l3_checksum : 16; //[31:16] 68 uint32_t rule_indication_31_0 : 32; //[31:0] 69 uint32_t rule_indication_63_32 : 32; //[31:0] 70 uint32_t da_offset : 6, //[5:0] 71 sa_offset : 6, //[11:6] 72 da_offset_valid : 1, //[12] 73 sa_offset_valid : 1, //[13] 74 reserved_5a : 2, //[15:14] 75 l3_type : 16; //[31:16] 76 uint32_t ipv6_options_crc : 32; //[31:0] 77 uint32_t tcp_seq_number : 32; //[31:0] 78 uint32_t tcp_ack_number : 32; //[31:0] 79 uint32_t tcp_flag : 9, //[8:0] 80 lro_eligible : 1, //[9] 81 reserved_9a : 6, //[15:10] 82 window_size : 16; //[31:16] 83 uint32_t tcp_udp_chksum : 16, //[15:0] 84 sa_idx_timeout : 1, //[16] 85 da_idx_timeout : 1, //[17] 86 msdu_limit_error : 1, //[18] 87 flow_idx_timeout : 1, //[19] 88 flow_idx_invalid : 1, //[20] 89 wifi_parser_error : 1, //[21] 90 amsdu_parser_error : 1, //[22] 91 sa_is_valid : 1, //[23] 92 da_is_valid : 1, //[24] 93 da_is_mcbc : 1, //[25] 94 l3_header_padding : 2, //[27:26] 95 first_msdu : 1, //[28] 96 last_msdu : 1, //[29] 97 tcp_udp_chksum_fail : 1, //[30] 98 ip_chksum_fail : 1; //[31] 99 uint32_t sa_idx : 16, //[15:0] 100 da_idx_or_sw_peer_id : 16; //[31:16] 101 uint32_t msdu_drop : 1, //[0] 102 reo_destination_indication : 5, //[5:1] 103 flow_idx : 20, //[25:6] 104 reserved_12a : 6; //[31:26] 105 uint32_t fse_metadata : 32; //[31:0] 106 uint32_t cce_metadata : 16, //[15:0] 107 sa_sw_peer_id : 16; //[31:16] 108 uint32_t aggregation_count : 8, //[7:0] 109 flow_aggregation_continuation : 1, //[8] 110 fisa_timeout : 1, //[9] 111 reserved_15a : 22; //[31:10] 112 uint32_t cumulative_l4_checksum : 16, //[15:0] 113 cumulative_ip_length : 16; //[31:16] 114 }; 115 116 /* 117 118 rxpcu_mpdu_filter_in_category 119 120 Field indicates what the reason was that this MPDU frame 121 was allowed to come into the receive path by RXPCU 122 123 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 124 frame filter programming of rxpcu 125 126 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 127 regular frame filter and would have been dropped, were it 128 not for the frame fitting into the 'monitor_client' 129 category. 130 131 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 132 regular frame filter and also did not pass the 133 rxpcu_monitor_client filter. It would have been dropped 134 accept that it did pass the 'monitor_other' category. 135 136 <legal 0-2> 137 138 sw_frame_group_id 139 140 SW processes frames based on certain classifications. 141 This field indicates to what sw classification this MPDU is 142 mapped. 143 144 The classification is given in priority order 145 146 147 148 <enum 0 sw_frame_group_NDP_frame> 149 150 151 152 <enum 1 sw_frame_group_Multicast_data> 153 154 <enum 2 sw_frame_group_Unicast_data> 155 156 <enum 3 sw_frame_group_Null_data > This includes mpdus 157 of type Data Null as well as QoS Data Null 158 159 160 161 <enum 4 sw_frame_group_mgmt_0000 > 162 163 <enum 5 sw_frame_group_mgmt_0001 > 164 165 <enum 6 sw_frame_group_mgmt_0010 > 166 167 <enum 7 sw_frame_group_mgmt_0011 > 168 169 <enum 8 sw_frame_group_mgmt_0100 > 170 171 <enum 9 sw_frame_group_mgmt_0101 > 172 173 <enum 10 sw_frame_group_mgmt_0110 > 174 175 <enum 11 sw_frame_group_mgmt_0111 > 176 177 <enum 12 sw_frame_group_mgmt_1000 > 178 179 <enum 13 sw_frame_group_mgmt_1001 > 180 181 <enum 14 sw_frame_group_mgmt_1010 > 182 183 <enum 15 sw_frame_group_mgmt_1011 > 184 185 <enum 16 sw_frame_group_mgmt_1100 > 186 187 <enum 17 sw_frame_group_mgmt_1101 > 188 189 <enum 18 sw_frame_group_mgmt_1110 > 190 191 <enum 19 sw_frame_group_mgmt_1111 > 192 193 194 195 <enum 20 sw_frame_group_ctrl_0000 > 196 197 <enum 21 sw_frame_group_ctrl_0001 > 198 199 <enum 22 sw_frame_group_ctrl_0010 > 200 201 <enum 23 sw_frame_group_ctrl_0011 > 202 203 <enum 24 sw_frame_group_ctrl_0100 > 204 205 <enum 25 sw_frame_group_ctrl_0101 > 206 207 <enum 26 sw_frame_group_ctrl_0110 > 208 209 <enum 27 sw_frame_group_ctrl_0111 > 210 211 <enum 28 sw_frame_group_ctrl_1000 > 212 213 <enum 29 sw_frame_group_ctrl_1001 > 214 215 <enum 30 sw_frame_group_ctrl_1010 > 216 217 <enum 31 sw_frame_group_ctrl_1011 > 218 219 <enum 32 sw_frame_group_ctrl_1100 > 220 221 <enum 33 sw_frame_group_ctrl_1101 > 222 223 <enum 34 sw_frame_group_ctrl_1110 > 224 225 <enum 35 sw_frame_group_ctrl_1111 > 226 227 228 229 <enum 36 sw_frame_group_unsupported> This covers type 3 230 and protocol version != 0 231 232 233 234 235 236 237 <legal 0-37> 238 239 reserved_0 240 241 <legal 0> 242 243 phy_ppdu_id 244 245 A ppdu counter value that PHY increments for every PPDU 246 received. The counter value wraps around 247 248 <legal all> 249 250 ip_hdr_chksum 251 252 This can include the IP header checksum or the pseudo 253 header checksum used by TCP/UDP checksum. 254 255 (with the first byte in the MSB and the second byte in 256 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 257 w.r.t. the byte order in a packet) 258 259 reported_mpdu_length 260 261 MPDU length before decapsulation. Only valid when 262 first_msdu is set. This field is taken directly from the 263 length field of the A-MPDU delimiter or the preamble length 264 field for non-A-MPDU frames. 265 266 reserved_1a 267 268 <legal 0> 269 270 key_id_octet 271 272 The key ID octet from the IV. Only valid when 273 first_msdu is set. 274 275 cce_super_rule 276 277 Indicates the super filter rule 278 279 cce_classify_not_done_truncate 280 281 Classification failed due to truncated frame 282 283 cce_classify_not_done_cce_dis 284 285 Classification failed due to CCE global disable 286 287 cumulative_l3_checksum 288 289 FISA: IP header checksum including the total MSDU length 290 that is part of this flow aggregated so far, reported if 291 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set 292 293 294 295 Set to zero in chips not supporting FISA, e.g. Pine 296 297 <legal all> 298 299 rule_indication_31_0 300 301 Bitmap indicating which of rules 31-0 have matched 302 303 rule_indication_63_32 304 305 Bitmap indicating which of rules 63-32 have matched 306 307 da_offset 308 309 Offset into MSDU buffer for DA 310 311 sa_offset 312 313 Offset into MSDU buffer for SA 314 315 da_offset_valid 316 317 da_offset field is valid. This will be set to 0 in case 318 of a dynamic A-MSDU when DA is compressed 319 320 sa_offset_valid 321 322 sa_offset field is valid. This will be set to 0 in case 323 of a dynamic A-MSDU when SA is compressed 324 325 reserved_5a 326 327 <legal 0> 328 329 l3_type 330 331 The 16-bit type value indicating the type of L3 later 332 extracted from LLC/SNAP, set to zero if SNAP is not 333 available 334 335 ipv6_options_crc 336 337 32 bit CRC computed out of IP v6 extension headers 338 339 tcp_seq_number 340 341 TCP sequence number (as a number assembled from a TCP 342 packet in big-endian order, i.e. requiring a byte-swap for 343 little-endian FW/SW w.r.t. the byte order in a packet) 344 345 346 347 In Pine, if 'RXOLE_R0_MISC_CONFIG. 348 OVERRIDE_MSDU_END_FIELDS' is set, toeplitz_hash_2_or_4 from 349 'RX_MSDU_START' will be reported here: 350 351 Controlled by multiple RxOLE registers for TCP/UDP over 352 IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 353 or IPv6 src/dest addresses is reported; or, Toeplitz hash 354 computed over 4-tuple IPv4 or IPv6 src/dest addresses and 355 src/dest ports is reported. The Flow_id_toeplitz hash can 356 also be reported here. Usually the hash reported here is the 357 one used for hash-based REO routing (see 358 use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO'). 359 Optionally the 3-tuple Toeplitz hash over IPv4 or IPv6 360 src/dest addresses and L4 protocol can be reported here. 361 362 (Unsupported in HastingsPrime) 363 364 tcp_ack_number 365 366 TCP acknowledge number (as a number assembled from a TCP 367 packet in big-endian order, i.e. requiring a byte-swap for 368 little-endian FW/SW w.r.t. the byte order in a packet) 369 370 371 372 In Pine, if 'RXOLE_R0_MISC_CONFIG. 373 OVERRIDE_MSDU_END_FIELDS' is set, flow_id_toeplitz from 374 'RX_MSDU_START' will be reported here: 375 376 Toeplitz hash of 5-tuple {IP source address, IP 377 destination address, IP source port, IP destination port, L4 378 protocol} in case of non-IPSec. In case of IPSec - Toeplitz 379 hash of 4-tuple {IP source address, IP destination address, 380 SPI, L4 protocol}. Optionally the 3-tuple Toeplitz hash over 381 IPv4 or IPv6 src/dest addresses and L4 protocol can be 382 reported here. 383 384 The relevant Toeplitz key registers are provided in 385 RxOLE's instance of common parser module. These registers 386 are separate from the Toeplitz keys used by ASE/FSE modules 387 inside RxOLE. The actual value will be passed on from common 388 parser module to RxOLE in one of the WHO_* TLVs. 389 390 (Unsupported in HastingsPrime) 391 392 tcp_flag 393 394 TCP flags 395 396 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 397 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 398 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 399 the byte order in a packet) 400 401 lro_eligible 402 403 Computed out of TCP and IP fields to indicate that this 404 MSDU is eligible for LRO 405 406 reserved_9a 407 408 NOTE: DO not assign a field... Internally used in 409 RXOLE.. 410 411 <legal 0> 412 413 window_size 414 415 TCP receive window size (as a number assembled from a 416 TCP packet in big-endian order, i.e. requiring a byte-swap 417 for little-endian FW/SW w.r.t. the byte order in a packet) 418 419 420 421 In Pine, if 'RXOLE_R0_MISC_CONFIG. 422 OVERRIDE_MSDU_END_FIELDS' is set, msdu_length from 423 'RX_MSDU_START' will be reported in the 14 LSBs here: 424 425 MSDU length in bytes after decapsulation. This field is 426 still valid for MPDU frames without A-MSDU. It still 427 represents MSDU length after decapsulation. 428 429 (Unsupported in HastingsPrime) 430 431 tcp_udp_chksum 432 433 The value of the computed TCP/UDP checksum. A mode bit 434 selects whether this checksum is the full checksum or the 435 partial checksum which does not include the pseudo header. 436 (with the first byte in the MSB and the second byte in the 437 LSB, i.e. requiring a byte-swap for little-endian FW/SW 438 w.r.t. the byte order in a packet) 439 440 sa_idx_timeout 441 442 Indicates an unsuccessful MAC source address search due 443 to the expiring of the search timer. 444 445 da_idx_timeout 446 447 Indicates an unsuccessful MAC destination address search 448 due to the expiring of the search timer. 449 450 msdu_limit_error 451 452 Indicates that the MSDU threshold was exceeded and thus 453 all the rest of the MSDUs will not be scattered and will not 454 be decapsulated but will be DMA'ed in RAW format as a single 455 MSDU buffer 456 457 flow_idx_timeout 458 459 Indicates an unsuccessful flow search due to the 460 expiring of the search timer. 461 462 <legal all> 463 464 flow_idx_invalid 465 466 flow id is not valid 467 468 <legal all> 469 470 wifi_parser_error 471 472 Indicates that the WiFi frame has one of the following 473 errors 474 475 o has less than minimum allowed bytes as per standard 476 477 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 478 479 <legal all> 480 481 amsdu_parser_error 482 483 A-MSDU could not be properly de-agregated. 484 485 <legal all> 486 487 sa_is_valid 488 489 Indicates that OLE found a valid SA entry 490 491 da_is_valid 492 493 Indicates that OLE found a valid DA entry 494 495 da_is_mcbc 496 497 Field Only valid if da_is_valid is set 498 499 500 501 Indicates the DA address was a Multicast of Broadcast 502 address. 503 504 l3_header_padding 505 506 Number of bytes padded to make sure that the L3 header 507 will always start of a Dword boundary 508 509 first_msdu 510 511 Indicates the first MSDU of A-MSDU. If both first_msdu 512 and last_msdu are set in the MSDU then this is a 513 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 514 A-MSDU shall have both first_mpdu and last_mpdu bits set to 515 0. 516 517 last_msdu 518 519 Indicates the last MSDU of the A-MSDU. MPDU end status 520 is only valid when last_msdu is set. 521 522 tcp_udp_chksum_fail 523 524 if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is 525 set, tcp_udp_chksum_fail from 'RX_ATTENTION' will be 526 reported here: 527 528 Indicates that the computed checksum (tcp_udp_chksum) 529 did not match the checksum in the TCP/UDP header. 530 531 (unsupported in HastingsPrime) 532 533 ip_chksum_fail 534 535 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is 536 set, ip_chksum_fail from 'RX_MSDU_START' will be reported in 537 the MSB here: 538 539 Indicates that the computed checksum (ip_hdr_chksum) did 540 not match the checksum in the IP header. 541 542 (unsupported in HastingsPrime) 543 544 sa_idx 545 546 The offset in the address table which matches the MAC 547 source address. 548 549 da_idx_or_sw_peer_id 550 551 Based on a register configuration in RXOLE, this field 552 will contain: 553 554 The offset in the address table which matches the MAC 555 destination address 556 557 OR: 558 559 sw_peer_id from the address search entry corresponding 560 to the destination address of the MSDU 561 562 msdu_drop 563 564 When set, REO shall drop this MSDU and not forward it to 565 any other ring... 566 567 <legal all> 568 569 reo_destination_indication 570 571 The ID of the REO exit ring where the MSDU frame shall 572 push after (MPDU level) reordering has finished. 573 574 575 576 <enum 0 reo_destination_tcl> Reo will push the frame 577 into the REO2TCL ring 578 579 <enum 1 reo_destination_sw1> Reo will push the frame 580 into the REO2SW1 ring 581 582 <enum 2 reo_destination_sw2> Reo will push the frame 583 into the REO2SW2 ring 584 585 <enum 3 reo_destination_sw3> Reo will push the frame 586 into the REO2SW3 ring 587 588 <enum 4 reo_destination_sw4> Reo will push the frame 589 into the REO2SW4 ring 590 591 <enum 5 reo_destination_release> Reo will push the frame 592 into the REO_release ring 593 594 <enum 6 reo_destination_fw> Reo will push the frame into 595 the REO2FW ring 596 597 <enum 7 reo_destination_sw5> Reo will push the frame 598 into the REO2SW5 ring (REO remaps this in chips without 599 REO2SW5 ring, e.g. Pine) 600 601 <enum 8 reo_destination_sw6> Reo will push the frame 602 into the REO2SW6 ring (REO remaps this in chips without 603 REO2SW6 ring, e.g. Pine) 604 605 <enum 9 reo_destination_9> REO remaps this <enum 10 606 reo_destination_10> REO remaps this 607 608 <enum 11 reo_destination_11> REO remaps this 609 610 <enum 12 reo_destination_12> REO remaps this <enum 13 611 reo_destination_13> REO remaps this 612 613 <enum 14 reo_destination_14> REO remaps this 614 615 <enum 15 reo_destination_15> REO remaps this 616 617 <enum 16 reo_destination_16> REO remaps this 618 619 <enum 17 reo_destination_17> REO remaps this 620 621 <enum 18 reo_destination_18> REO remaps this 622 623 <enum 19 reo_destination_19> REO remaps this 624 625 <enum 20 reo_destination_20> REO remaps this 626 627 <enum 21 reo_destination_21> REO remaps this 628 629 <enum 22 reo_destination_22> REO remaps this 630 631 <enum 23 reo_destination_23> REO remaps this 632 633 <enum 24 reo_destination_24> REO remaps this 634 635 <enum 25 reo_destination_25> REO remaps this 636 637 <enum 26 reo_destination_26> REO remaps this 638 639 <enum 27 reo_destination_27> REO remaps this 640 641 <enum 28 reo_destination_28> REO remaps this 642 643 <enum 29 reo_destination_29> REO remaps this 644 645 <enum 30 reo_destination_30> REO remaps this 646 647 <enum 31 reo_destination_31> REO remaps this 648 649 650 651 <legal all> 652 653 flow_idx 654 655 Flow table index 656 657 <legal all> 658 659 reserved_12a 660 661 <legal 0> 662 663 fse_metadata 664 665 FSE related meta data: 666 667 <legal all> 668 669 cce_metadata 670 671 CCE related meta data: 672 673 <legal all> 674 675 sa_sw_peer_id 676 677 sw_peer_id from the address search entry corresponding 678 to the source address of the MSDU 679 680 <legal all> 681 682 aggregation_count 683 684 FISA: Number of MSDU's aggregated so far 685 686 687 688 Set to zero in chips not supporting FISA, e.g. Pine 689 690 <legal all> 691 692 flow_aggregation_continuation 693 694 FISA: To indicate that this MSDU can be aggregated with 695 the previous packet with the same flow id 696 697 698 699 Set to zero in chips not supporting FISA, e.g. Pine 700 701 <legal all> 702 703 fisa_timeout 704 705 FISA: To indicate that the aggregation has restarted for 706 this flow due to timeout 707 708 709 710 Set to zero in chips not supporting FISA, e.g. Pine 711 712 <legal all> 713 714 reserved_15a 715 716 <legal 0> 717 718 cumulative_l4_checksum 719 720 FISA: checksum for MSDU's that is part of this flow 721 aggregated so far 722 723 724 725 Set to zero in chips not supporting FISA, e.g. Pine 726 727 <legal all> 728 729 cumulative_ip_length 730 731 FISA: Total MSDU length that is part of this flow 732 aggregated so far 733 734 735 736 Set to zero in chips not supporting FISA, e.g. Pine 737 738 <legal all> 739 */ 740 741 742 /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 743 744 Field indicates what the reason was that this MPDU frame 745 was allowed to come into the receive path by RXPCU 746 747 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 748 frame filter programming of rxpcu 749 750 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 751 regular frame filter and would have been dropped, were it 752 not for the frame fitting into the 'monitor_client' 753 category. 754 755 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 756 regular frame filter and also did not pass the 757 rxpcu_monitor_client filter. It would have been dropped 758 accept that it did pass the 'monitor_other' category. 759 760 <legal 0-2> 761 */ 762 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 763 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 764 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 765 766 /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID 767 768 SW processes frames based on certain classifications. 769 This field indicates to what sw classification this MPDU is 770 mapped. 771 772 The classification is given in priority order 773 774 775 776 <enum 0 sw_frame_group_NDP_frame> 777 778 779 780 <enum 1 sw_frame_group_Multicast_data> 781 782 <enum 2 sw_frame_group_Unicast_data> 783 784 <enum 3 sw_frame_group_Null_data > This includes mpdus 785 of type Data Null as well as QoS Data Null 786 787 788 789 <enum 4 sw_frame_group_mgmt_0000 > 790 791 <enum 5 sw_frame_group_mgmt_0001 > 792 793 <enum 6 sw_frame_group_mgmt_0010 > 794 795 <enum 7 sw_frame_group_mgmt_0011 > 796 797 <enum 8 sw_frame_group_mgmt_0100 > 798 799 <enum 9 sw_frame_group_mgmt_0101 > 800 801 <enum 10 sw_frame_group_mgmt_0110 > 802 803 <enum 11 sw_frame_group_mgmt_0111 > 804 805 <enum 12 sw_frame_group_mgmt_1000 > 806 807 <enum 13 sw_frame_group_mgmt_1001 > 808 809 <enum 14 sw_frame_group_mgmt_1010 > 810 811 <enum 15 sw_frame_group_mgmt_1011 > 812 813 <enum 16 sw_frame_group_mgmt_1100 > 814 815 <enum 17 sw_frame_group_mgmt_1101 > 816 817 <enum 18 sw_frame_group_mgmt_1110 > 818 819 <enum 19 sw_frame_group_mgmt_1111 > 820 821 822 823 <enum 20 sw_frame_group_ctrl_0000 > 824 825 <enum 21 sw_frame_group_ctrl_0001 > 826 827 <enum 22 sw_frame_group_ctrl_0010 > 828 829 <enum 23 sw_frame_group_ctrl_0011 > 830 831 <enum 24 sw_frame_group_ctrl_0100 > 832 833 <enum 25 sw_frame_group_ctrl_0101 > 834 835 <enum 26 sw_frame_group_ctrl_0110 > 836 837 <enum 27 sw_frame_group_ctrl_0111 > 838 839 <enum 28 sw_frame_group_ctrl_1000 > 840 841 <enum 29 sw_frame_group_ctrl_1001 > 842 843 <enum 30 sw_frame_group_ctrl_1010 > 844 845 <enum 31 sw_frame_group_ctrl_1011 > 846 847 <enum 32 sw_frame_group_ctrl_1100 > 848 849 <enum 33 sw_frame_group_ctrl_1101 > 850 851 <enum 34 sw_frame_group_ctrl_1110 > 852 853 <enum 35 sw_frame_group_ctrl_1111 > 854 855 856 857 <enum 36 sw_frame_group_unsupported> This covers type 3 858 and protocol version != 0 859 860 861 862 863 864 865 <legal 0-37> 866 */ 867 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 868 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 869 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 870 871 /* Description RX_MSDU_END_0_RESERVED_0 872 873 <legal 0> 874 */ 875 #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 876 #define RX_MSDU_END_0_RESERVED_0_LSB 9 877 #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 878 879 /* Description RX_MSDU_END_0_PHY_PPDU_ID 880 881 A ppdu counter value that PHY increments for every PPDU 882 received. The counter value wraps around 883 884 <legal all> 885 */ 886 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 887 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 888 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 889 890 /* Description RX_MSDU_END_1_IP_HDR_CHKSUM 891 892 This can include the IP header checksum or the pseudo 893 header checksum used by TCP/UDP checksum. 894 895 (with the first byte in the MSB and the second byte in 896 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 897 w.r.t. the byte order in a packet) 898 */ 899 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 900 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 901 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff 902 903 /* Description RX_MSDU_END_1_REPORTED_MPDU_LENGTH 904 905 MPDU length before decapsulation. Only valid when 906 first_msdu is set. This field is taken directly from the 907 length field of the A-MPDU delimiter or the preamble length 908 field for non-A-MPDU frames. 909 */ 910 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 911 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 912 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 913 914 /* Description RX_MSDU_END_1_RESERVED_1A 915 916 <legal 0> 917 */ 918 #define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 919 #define RX_MSDU_END_1_RESERVED_1A_LSB 30 920 #define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 921 922 /* Description RX_MSDU_END_2_KEY_ID_OCTET 923 924 The key ID octet from the IV. Only valid when 925 first_msdu is set. 926 */ 927 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 928 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 929 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff 930 931 /* Description RX_MSDU_END_2_CCE_SUPER_RULE 932 933 Indicates the super filter rule 934 */ 935 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 936 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 937 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 938 939 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE 940 941 Classification failed due to truncated frame 942 */ 943 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 944 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 945 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 946 947 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS 948 949 Classification failed due to CCE global disable 950 */ 951 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 952 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 953 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 954 955 /* Description RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM 956 957 FISA: IP header checksum including the total MSDU length 958 that is part of this flow aggregated so far, reported if 959 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set 960 961 962 963 Set to zero in chips not supporting FISA, e.g. Pine 964 965 <legal all> 966 */ 967 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 968 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16 969 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 970 971 /* Description RX_MSDU_END_3_RULE_INDICATION_31_0 972 973 Bitmap indicating which of rules 31-0 have matched 974 */ 975 #define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c 976 #define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0 977 #define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff 978 979 /* Description RX_MSDU_END_4_RULE_INDICATION_63_32 980 981 Bitmap indicating which of rules 63-32 have matched 982 */ 983 #define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010 984 #define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0 985 #define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff 986 987 /* Description RX_MSDU_END_5_DA_OFFSET 988 989 Offset into MSDU buffer for DA 990 */ 991 #define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 992 #define RX_MSDU_END_5_DA_OFFSET_LSB 0 993 #define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f 994 995 /* Description RX_MSDU_END_5_SA_OFFSET 996 997 Offset into MSDU buffer for SA 998 */ 999 #define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 1000 #define RX_MSDU_END_5_SA_OFFSET_LSB 6 1001 #define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 1002 1003 /* Description RX_MSDU_END_5_DA_OFFSET_VALID 1004 1005 da_offset field is valid. This will be set to 0 in case 1006 of a dynamic A-MSDU when DA is compressed 1007 */ 1008 #define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 1009 #define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 1010 #define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 1011 1012 /* Description RX_MSDU_END_5_SA_OFFSET_VALID 1013 1014 sa_offset field is valid. This will be set to 0 in case 1015 of a dynamic A-MSDU when SA is compressed 1016 */ 1017 #define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 1018 #define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 1019 #define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 1020 1021 /* Description RX_MSDU_END_5_RESERVED_5A 1022 1023 <legal 0> 1024 */ 1025 #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 1026 #define RX_MSDU_END_5_RESERVED_5A_LSB 14 1027 #define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000 1028 1029 /* Description RX_MSDU_END_5_L3_TYPE 1030 1031 The 16-bit type value indicating the type of L3 later 1032 extracted from LLC/SNAP, set to zero if SNAP is not 1033 available 1034 */ 1035 #define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 1036 #define RX_MSDU_END_5_L3_TYPE_LSB 16 1037 #define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 1038 1039 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC 1040 1041 32 bit CRC computed out of IP v6 extension headers 1042 */ 1043 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 1044 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 1045 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff 1046 1047 /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER 1048 1049 TCP sequence number (as a number assembled from a TCP 1050 packet in big-endian order, i.e. requiring a byte-swap for 1051 little-endian FW/SW w.r.t. the byte order in a packet) 1052 1053 1054 1055 In Pine, if 'RXOLE_R0_MISC_CONFIG. 1056 OVERRIDE_MSDU_END_FIELDS' is set, toeplitz_hash_2_or_4 from 1057 'RX_MSDU_START' will be reported here: 1058 1059 Controlled by multiple RxOLE registers for TCP/UDP over 1060 IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 1061 or IPv6 src/dest addresses is reported; or, Toeplitz hash 1062 computed over 4-tuple IPv4 or IPv6 src/dest addresses and 1063 src/dest ports is reported. The Flow_id_toeplitz hash can 1064 also be reported here. Usually the hash reported here is the 1065 one used for hash-based REO routing (see 1066 use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO'). 1067 Optionally the 3-tuple Toeplitz hash over IPv4 or IPv6 1068 src/dest addresses and L4 protocol can be reported here. 1069 1070 (Unsupported in HastingsPrime) 1071 */ 1072 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c 1073 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 1074 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff 1075 1076 /* Description RX_MSDU_END_8_TCP_ACK_NUMBER 1077 1078 TCP acknowledge number (as a number assembled from a TCP 1079 packet in big-endian order, i.e. requiring a byte-swap for 1080 little-endian FW/SW w.r.t. the byte order in a packet) 1081 1082 1083 1084 In Pine, if 'RXOLE_R0_MISC_CONFIG. 1085 OVERRIDE_MSDU_END_FIELDS' is set, flow_id_toeplitz from 1086 'RX_MSDU_START' will be reported here: 1087 1088 Toeplitz hash of 5-tuple {IP source address, IP 1089 destination address, IP source port, IP destination port, L4 1090 protocol} in case of non-IPSec. In case of IPSec - Toeplitz 1091 hash of 4-tuple {IP source address, IP destination address, 1092 SPI, L4 protocol}. Optionally the 3-tuple Toeplitz hash over 1093 IPv4 or IPv6 src/dest addresses and L4 protocol can be 1094 reported here. 1095 1096 The relevant Toeplitz key registers are provided in 1097 RxOLE's instance of common parser module. These registers 1098 are separate from the Toeplitz keys used by ASE/FSE modules 1099 inside RxOLE. The actual value will be passed on from common 1100 parser module to RxOLE in one of the WHO_* TLVs. 1101 1102 (Unsupported in HastingsPrime) 1103 */ 1104 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 1105 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 1106 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff 1107 1108 /* Description RX_MSDU_END_9_TCP_FLAG 1109 1110 TCP flags 1111 1112 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 1113 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 1114 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 1115 the byte order in a packet) 1116 */ 1117 #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 1118 #define RX_MSDU_END_9_TCP_FLAG_LSB 0 1119 #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff 1120 1121 /* Description RX_MSDU_END_9_LRO_ELIGIBLE 1122 1123 Computed out of TCP and IP fields to indicate that this 1124 MSDU is eligible for LRO 1125 */ 1126 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 1127 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 1128 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 1129 1130 /* Description RX_MSDU_END_9_RESERVED_9A 1131 1132 NOTE: DO not assign a field... Internally used in 1133 RXOLE.. 1134 1135 <legal 0> 1136 */ 1137 #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 1138 #define RX_MSDU_END_9_RESERVED_9A_LSB 10 1139 #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 1140 1141 /* Description RX_MSDU_END_9_WINDOW_SIZE 1142 1143 TCP receive window size (as a number assembled from a 1144 TCP packet in big-endian order, i.e. requiring a byte-swap 1145 for little-endian FW/SW w.r.t. the byte order in a packet) 1146 1147 1148 1149 In Pine, if 'RXOLE_R0_MISC_CONFIG. 1150 OVERRIDE_MSDU_END_FIELDS' is set, msdu_length from 1151 'RX_MSDU_START' will be reported in the 14 LSBs here: 1152 1153 MSDU length in bytes after decapsulation. This field is 1154 still valid for MPDU frames without A-MSDU. It still 1155 represents MSDU length after decapsulation. 1156 1157 (Unsupported in HastingsPrime) 1158 */ 1159 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 1160 #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 1161 #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 1162 1163 /* Description RX_MSDU_END_10_TCP_UDP_CHKSUM 1164 1165 The value of the computed TCP/UDP checksum. A mode bit 1166 selects whether this checksum is the full checksum or the 1167 partial checksum which does not include the pseudo header. 1168 (with the first byte in the MSB and the second byte in the 1169 LSB, i.e. requiring a byte-swap for little-endian FW/SW 1170 w.r.t. the byte order in a packet) 1171 */ 1172 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 1173 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 1174 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff 1175 1176 /* Description RX_MSDU_END_10_SA_IDX_TIMEOUT 1177 1178 Indicates an unsuccessful MAC source address search due 1179 to the expiring of the search timer. 1180 */ 1181 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 1182 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 1183 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 1184 1185 /* Description RX_MSDU_END_10_DA_IDX_TIMEOUT 1186 1187 Indicates an unsuccessful MAC destination address search 1188 due to the expiring of the search timer. 1189 */ 1190 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 1191 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 1192 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 1193 1194 /* Description RX_MSDU_END_10_MSDU_LIMIT_ERROR 1195 1196 Indicates that the MSDU threshold was exceeded and thus 1197 all the rest of the MSDUs will not be scattered and will not 1198 be decapsulated but will be DMA'ed in RAW format as a single 1199 MSDU buffer 1200 */ 1201 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 1202 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 1203 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 1204 1205 /* Description RX_MSDU_END_10_FLOW_IDX_TIMEOUT 1206 1207 Indicates an unsuccessful flow search due to the 1208 expiring of the search timer. 1209 1210 <legal all> 1211 */ 1212 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 1213 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 1214 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 1215 1216 /* Description RX_MSDU_END_10_FLOW_IDX_INVALID 1217 1218 flow id is not valid 1219 1220 <legal all> 1221 */ 1222 #define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 1223 #define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 1224 #define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 1225 1226 /* Description RX_MSDU_END_10_WIFI_PARSER_ERROR 1227 1228 Indicates that the WiFi frame has one of the following 1229 errors 1230 1231 o has less than minimum allowed bytes as per standard 1232 1233 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 1234 1235 <legal all> 1236 */ 1237 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 1238 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 1239 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 1240 1241 /* Description RX_MSDU_END_10_AMSDU_PARSER_ERROR 1242 1243 A-MSDU could not be properly de-agregated. 1244 1245 <legal all> 1246 */ 1247 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 1248 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 1249 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 1250 1251 /* Description RX_MSDU_END_10_SA_IS_VALID 1252 1253 Indicates that OLE found a valid SA entry 1254 */ 1255 #define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 1256 #define RX_MSDU_END_10_SA_IS_VALID_LSB 23 1257 #define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 1258 1259 /* Description RX_MSDU_END_10_DA_IS_VALID 1260 1261 Indicates that OLE found a valid DA entry 1262 */ 1263 #define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 1264 #define RX_MSDU_END_10_DA_IS_VALID_LSB 24 1265 #define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 1266 1267 /* Description RX_MSDU_END_10_DA_IS_MCBC 1268 1269 Field Only valid if da_is_valid is set 1270 1271 1272 1273 Indicates the DA address was a Multicast of Broadcast 1274 address. 1275 */ 1276 #define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 1277 #define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 1278 #define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 1279 1280 /* Description RX_MSDU_END_10_L3_HEADER_PADDING 1281 1282 Number of bytes padded to make sure that the L3 header 1283 will always start of a Dword boundary 1284 */ 1285 #define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 1286 #define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 1287 #define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 1288 1289 /* Description RX_MSDU_END_10_FIRST_MSDU 1290 1291 Indicates the first MSDU of A-MSDU. If both first_msdu 1292 and last_msdu are set in the MSDU then this is a 1293 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 1294 A-MSDU shall have both first_mpdu and last_mpdu bits set to 1295 0. 1296 */ 1297 #define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 1298 #define RX_MSDU_END_10_FIRST_MSDU_LSB 28 1299 #define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 1300 1301 /* Description RX_MSDU_END_10_LAST_MSDU 1302 1303 Indicates the last MSDU of the A-MSDU. MPDU end status 1304 is only valid when last_msdu is set. 1305 */ 1306 #define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 1307 #define RX_MSDU_END_10_LAST_MSDU_LSB 29 1308 #define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 1309 1310 /* Description RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL 1311 1312 if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is 1313 set, tcp_udp_chksum_fail from 'RX_ATTENTION' will be 1314 reported here: 1315 1316 Indicates that the computed checksum (tcp_udp_chksum) 1317 did not match the checksum in the TCP/UDP header. 1318 1319 (unsupported in HastingsPrime) 1320 */ 1321 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 1322 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30 1323 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000 1324 1325 /* Description RX_MSDU_END_10_IP_CHKSUM_FAIL 1326 1327 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is 1328 set, ip_chksum_fail from 'RX_MSDU_START' will be reported in 1329 the MSB here: 1330 1331 Indicates that the computed checksum (ip_hdr_chksum) did 1332 not match the checksum in the IP header. 1333 1334 (unsupported in HastingsPrime) 1335 */ 1336 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028 1337 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31 1338 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000 1339 1340 /* Description RX_MSDU_END_11_SA_IDX 1341 1342 The offset in the address table which matches the MAC 1343 source address. 1344 */ 1345 #define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c 1346 #define RX_MSDU_END_11_SA_IDX_LSB 0 1347 #define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff 1348 1349 /* Description RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID 1350 1351 Based on a register configuration in RXOLE, this field 1352 will contain: 1353 1354 The offset in the address table which matches the MAC 1355 destination address 1356 1357 OR: 1358 1359 sw_peer_id from the address search entry corresponding 1360 to the destination address of the MSDU 1361 */ 1362 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c 1363 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 1364 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 1365 1366 /* Description RX_MSDU_END_12_MSDU_DROP 1367 1368 When set, REO shall drop this MSDU and not forward it to 1369 any other ring... 1370 1371 <legal all> 1372 */ 1373 #define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 1374 #define RX_MSDU_END_12_MSDU_DROP_LSB 0 1375 #define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 1376 1377 /* Description RX_MSDU_END_12_REO_DESTINATION_INDICATION 1378 1379 The ID of the REO exit ring where the MSDU frame shall 1380 push after (MPDU level) reordering has finished. 1381 1382 1383 1384 <enum 0 reo_destination_tcl> Reo will push the frame 1385 into the REO2TCL ring 1386 1387 <enum 1 reo_destination_sw1> Reo will push the frame 1388 into the REO2SW1 ring 1389 1390 <enum 2 reo_destination_sw2> Reo will push the frame 1391 into the REO2SW2 ring 1392 1393 <enum 3 reo_destination_sw3> Reo will push the frame 1394 into the REO2SW3 ring 1395 1396 <enum 4 reo_destination_sw4> Reo will push the frame 1397 into the REO2SW4 ring 1398 1399 <enum 5 reo_destination_release> Reo will push the frame 1400 into the REO_release ring 1401 1402 <enum 6 reo_destination_fw> Reo will push the frame into 1403 the REO2FW ring 1404 1405 <enum 7 reo_destination_sw5> Reo will push the frame 1406 into the REO2SW5 ring (REO remaps this in chips without 1407 REO2SW5 ring, e.g. Pine) 1408 1409 <enum 8 reo_destination_sw6> Reo will push the frame 1410 into the REO2SW6 ring (REO remaps this in chips without 1411 REO2SW6 ring, e.g. Pine) 1412 1413 <enum 9 reo_destination_9> REO remaps this <enum 10 1414 reo_destination_10> REO remaps this 1415 1416 <enum 11 reo_destination_11> REO remaps this 1417 1418 <enum 12 reo_destination_12> REO remaps this <enum 13 1419 reo_destination_13> REO remaps this 1420 1421 <enum 14 reo_destination_14> REO remaps this 1422 1423 <enum 15 reo_destination_15> REO remaps this 1424 1425 <enum 16 reo_destination_16> REO remaps this 1426 1427 <enum 17 reo_destination_17> REO remaps this 1428 1429 <enum 18 reo_destination_18> REO remaps this 1430 1431 <enum 19 reo_destination_19> REO remaps this 1432 1433 <enum 20 reo_destination_20> REO remaps this 1434 1435 <enum 21 reo_destination_21> REO remaps this 1436 1437 <enum 22 reo_destination_22> REO remaps this 1438 1439 <enum 23 reo_destination_23> REO remaps this 1440 1441 <enum 24 reo_destination_24> REO remaps this 1442 1443 <enum 25 reo_destination_25> REO remaps this 1444 1445 <enum 26 reo_destination_26> REO remaps this 1446 1447 <enum 27 reo_destination_27> REO remaps this 1448 1449 <enum 28 reo_destination_28> REO remaps this 1450 1451 <enum 29 reo_destination_29> REO remaps this 1452 1453 <enum 30 reo_destination_30> REO remaps this 1454 1455 <enum 31 reo_destination_31> REO remaps this 1456 1457 1458 1459 <legal all> 1460 */ 1461 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 1462 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 1463 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e 1464 1465 /* Description RX_MSDU_END_12_FLOW_IDX 1466 1467 Flow table index 1468 1469 <legal all> 1470 */ 1471 #define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 1472 #define RX_MSDU_END_12_FLOW_IDX_LSB 6 1473 #define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 1474 1475 /* Description RX_MSDU_END_12_RESERVED_12A 1476 1477 <legal 0> 1478 */ 1479 #define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030 1480 #define RX_MSDU_END_12_RESERVED_12A_LSB 26 1481 #define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000 1482 1483 /* Description RX_MSDU_END_13_FSE_METADATA 1484 1485 FSE related meta data: 1486 1487 <legal all> 1488 */ 1489 #define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 1490 #define RX_MSDU_END_13_FSE_METADATA_LSB 0 1491 #define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff 1492 1493 /* Description RX_MSDU_END_14_CCE_METADATA 1494 1495 CCE related meta data: 1496 1497 <legal all> 1498 */ 1499 #define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 1500 #define RX_MSDU_END_14_CCE_METADATA_LSB 0 1501 #define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff 1502 1503 /* Description RX_MSDU_END_14_SA_SW_PEER_ID 1504 1505 sw_peer_id from the address search entry corresponding 1506 to the source address of the MSDU 1507 1508 <legal all> 1509 */ 1510 #define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 1511 #define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 1512 #define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 1513 1514 /* Description RX_MSDU_END_15_AGGREGATION_COUNT 1515 1516 FISA: Number of MSDU's aggregated so far 1517 1518 1519 1520 Set to zero in chips not supporting FISA, e.g. Pine 1521 1522 <legal all> 1523 */ 1524 #define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c 1525 #define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0 1526 #define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff 1527 1528 /* Description RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION 1529 1530 FISA: To indicate that this MSDU can be aggregated with 1531 the previous packet with the same flow id 1532 1533 1534 1535 Set to zero in chips not supporting FISA, e.g. Pine 1536 1537 <legal all> 1538 */ 1539 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c 1540 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8 1541 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 1542 1543 /* Description RX_MSDU_END_15_FISA_TIMEOUT 1544 1545 FISA: To indicate that the aggregation has restarted for 1546 this flow due to timeout 1547 1548 1549 1550 Set to zero in chips not supporting FISA, e.g. Pine 1551 1552 <legal all> 1553 */ 1554 #define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c 1555 #define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9 1556 #define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200 1557 1558 /* Description RX_MSDU_END_15_RESERVED_15A 1559 1560 <legal 0> 1561 */ 1562 #define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c 1563 #define RX_MSDU_END_15_RESERVED_15A_LSB 10 1564 #define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00 1565 1566 /* Description RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM 1567 1568 FISA: checksum for MSDU's that is part of this flow 1569 aggregated so far 1570 1571 1572 1573 Set to zero in chips not supporting FISA, e.g. Pine 1574 1575 <legal all> 1576 */ 1577 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040 1578 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0 1579 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff 1580 1581 /* Description RX_MSDU_END_16_CUMULATIVE_IP_LENGTH 1582 1583 FISA: Total MSDU length that is part of this flow 1584 aggregated so far 1585 1586 1587 1588 Set to zero in chips not supporting FISA, e.g. Pine 1589 1590 <legal all> 1591 */ 1592 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040 1593 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16 1594 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 1595 1596 1597 #endif // _RX_MSDU_END_H_ 1598