1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MSDU_LINK_H_ 25 #define _RX_MSDU_LINK_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_descriptor_header.h" 30 #include "buffer_addr_info.h" 31 #include "rx_msdu_details.h" 32 33 // ################ START SUMMARY ################# 34 // 35 // Dword Fields 36 // 0 struct uniform_descriptor_header descriptor_header; 37 // 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info; 38 // 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17] 39 // 4 pn_31_0[31:0] 40 // 5 pn_63_32[31:0] 41 // 6 pn_95_64[31:0] 42 // 7 pn_127_96[31:0] 43 // 8-11 struct rx_msdu_details msdu_0; 44 // 12-15 struct rx_msdu_details msdu_1; 45 // 16-19 struct rx_msdu_details msdu_2; 46 // 20-23 struct rx_msdu_details msdu_3; 47 // 24-27 struct rx_msdu_details msdu_4; 48 // 28-31 struct rx_msdu_details msdu_5; 49 // 50 // ################ END SUMMARY ################# 51 52 #define NUM_OF_DWORDS_RX_MSDU_LINK 32 53 54 struct rx_msdu_link { 55 struct uniform_descriptor_header descriptor_header; 56 struct buffer_addr_info next_msdu_link_desc_addr_info; 57 uint32_t receive_queue_number : 16, //[15:0] 58 first_rx_msdu_link_struct : 1, //[16] 59 reserved_3a : 15; //[31:17] 60 uint32_t pn_31_0 : 32; //[31:0] 61 uint32_t pn_63_32 : 32; //[31:0] 62 uint32_t pn_95_64 : 32; //[31:0] 63 uint32_t pn_127_96 : 32; //[31:0] 64 struct rx_msdu_details msdu_0; 65 struct rx_msdu_details msdu_1; 66 struct rx_msdu_details msdu_2; 67 struct rx_msdu_details msdu_3; 68 struct rx_msdu_details msdu_4; 69 struct rx_msdu_details msdu_5; 70 }; 71 72 /* 73 74 struct uniform_descriptor_header descriptor_header 75 76 Details about which module owns this struct. 77 78 Note that sub field Buffer_type shall be set to 79 Receive_MSDU_Link_descriptor 80 81 struct buffer_addr_info next_msdu_link_desc_addr_info 82 83 Details of the physical address of the next MSDU link 84 descriptor that contains info about additional MSDUs that 85 are part of this MPDU. 86 87 receive_queue_number 88 89 Indicates the Receive queue to which this MPDU 90 descriptor belongs 91 92 Used for tracking, finding bugs and debugging. 93 94 <legal all> 95 96 first_rx_msdu_link_struct 97 98 When set, this RX_MSDU_link descriptor is the first one 99 in the MSDU link list. Field MSDU_0 points to the very first 100 MSDU buffer descriptor in the MPDU 101 102 <legal all> 103 104 reserved_3a 105 106 <legal 0> 107 108 pn_31_0 109 110 111 112 113 31-0 bits of the 256-bit packet number bitmap. 114 115 <legal all> 116 117 pn_63_32 118 119 120 121 122 63-32 bits of the 256-bit packet number bitmap. 123 124 <legal all> 125 126 pn_95_64 127 128 129 130 131 95-64 bits of the 256-bit packet number bitmap. 132 133 <legal all> 134 135 pn_127_96 136 137 138 139 140 127-96 bits of the 256-bit packet number bitmap. 141 142 <legal all> 143 144 struct rx_msdu_details msdu_0 145 146 When First_RX_MSDU_link_struct is set, this MSDU is the 147 first in the MPDU 148 149 150 151 When First_RX_MSDU_link_struct is NOT set, this MSDU 152 follows the last MSDU in the previous RX_MSDU_link data 153 structure 154 155 struct rx_msdu_details msdu_1 156 157 Details of next MSDU in this (MSDU flow) linked list 158 159 struct rx_msdu_details msdu_2 160 161 Details of next MSDU in this (MSDU flow) linked list 162 163 struct rx_msdu_details msdu_3 164 165 Details of next MSDU in this (MSDU flow) linked list 166 167 struct rx_msdu_details msdu_4 168 169 Details of next MSDU in this (MSDU flow) linked list 170 171 struct rx_msdu_details msdu_5 172 173 Details of next MSDU in this (MSDU flow) linked list 174 */ 175 176 177 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 178 179 180 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER 181 182 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 183 184 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 185 186 187 188 The owner of this data structure: 189 190 <enum 0 WBM_owned> Buffer Manager currently owns this 191 data structure. 192 193 <enum 1 SW_OR_FW_owned> Software of FW currently owns 194 this data structure. 195 196 <enum 2 TQM_owned> Transmit Queue Manager currently owns 197 this data structure. 198 199 <enum 3 RXDMA_owned> Receive DMA currently owns this 200 data structure. 201 202 <enum 4 REO_owned> Reorder currently owns this data 203 structure. 204 205 <enum 5 SWITCH_owned> SWITCH currently owns this data 206 structure. 207 208 209 210 <legal 0-5> 211 */ 212 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 213 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0 214 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 215 216 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE 217 218 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 219 220 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 221 222 223 224 Field describing what contents format is of this 225 descriptor 226 227 228 229 <enum 0 Transmit_MSDU_Link_descriptor > 230 231 <enum 1 Transmit_MPDU_Link_descriptor > 232 233 <enum 2 Transmit_MPDU_Queue_head_descriptor> 234 235 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 236 237 <enum 4 Transmit_flow_descriptor> 238 239 <enum 5 Transmit_buffer > NOT TO BE USED: 240 241 242 243 <enum 6 Receive_MSDU_Link_descriptor > 244 245 <enum 7 Receive_MPDU_Link_descriptor > 246 247 <enum 8 Receive_REO_queue_descriptor > 248 249 <enum 9 Receive_REO_queue_ext_descriptor > 250 251 252 253 <enum 10 Receive_buffer > 254 255 256 257 <enum 11 Idle_link_list_entry> 258 259 260 261 <legal 0-11> 262 */ 263 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 264 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 265 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 266 267 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A 268 269 <legal 0> 270 */ 271 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 272 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 273 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 274 275 /* EXTERNAL REFERENCE : struct buffer_addr_info next_msdu_link_desc_addr_info */ 276 277 278 /* Description RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 279 280 Address (lower 32 bits) of the MSDU buffer OR 281 MSDU_EXTENSION descriptor OR Link Descriptor 282 283 284 285 In case of 'NULL' pointer, this field is set to 0 286 287 <legal all> 288 */ 289 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 290 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 291 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 292 293 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 294 295 Address (upper 8 bits) of the MSDU buffer OR 296 MSDU_EXTENSION descriptor OR Link Descriptor 297 298 299 300 In case of 'NULL' pointer, this field is set to 0 301 302 <legal all> 303 */ 304 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 305 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 306 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 307 308 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 309 310 Consumer: WBM 311 312 Producer: SW/FW 313 314 315 316 In case of 'NULL' pointer, this field is set to 0 317 318 319 320 Indicates to which buffer manager the buffer OR 321 MSDU_EXTENSION descriptor OR link descriptor that is being 322 pointed to shall be returned after the frame has been 323 processed. It is used by WBM for routing purposes. 324 325 326 327 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 328 to the WMB buffer idle list 329 330 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 331 returned to the WMB idle link descriptor idle list 332 333 <enum 2 FW_BM> This buffer shall be returned to the FW 334 335 <enum 3 SW0_BM> This buffer shall be returned to the SW, 336 ring 0 337 338 <enum 4 SW1_BM> This buffer shall be returned to the SW, 339 ring 1 340 341 <enum 5 SW2_BM> This buffer shall be returned to the SW, 342 ring 2 343 344 <enum 6 SW3_BM> This buffer shall be returned to the SW, 345 ring 3 346 347 <enum 7 SW4_BM> This buffer shall be returned to the SW, 348 ring 4 349 350 351 352 <legal all> 353 */ 354 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 355 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 356 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 357 358 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 359 360 Cookie field exclusively used by SW. 361 362 363 364 In case of 'NULL' pointer, this field is set to 0 365 366 367 368 HW ignores the contents, accept that it passes the 369 programmed value on to other descriptors together with the 370 physical address 371 372 373 374 Field can be used by SW to for example associate the 375 buffers physical address with the virtual address 376 377 The bit definitions as used by SW are within SW HLD 378 specification 379 380 381 382 NOTE: 383 384 The three most significant bits can have a special 385 meaning in case this struct is embedded in a TX_MPDU_DETAILS 386 STRUCT, and field transmit_bw_restriction is set 387 388 389 390 In case of NON punctured transmission: 391 392 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 393 394 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 395 396 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 397 398 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 399 400 401 402 In case of punctured transmission: 403 404 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 405 406 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 407 408 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 409 410 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 411 412 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 413 414 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 415 416 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 417 418 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 419 420 421 422 Note: a punctured transmission is indicated by the 423 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 424 TLV 425 426 427 428 <legal all> 429 */ 430 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 431 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 432 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 433 434 /* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER 435 436 Indicates the Receive queue to which this MPDU 437 descriptor belongs 438 439 Used for tracking, finding bugs and debugging. 440 441 <legal all> 442 */ 443 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 444 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 445 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 446 447 /* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT 448 449 When set, this RX_MSDU_link descriptor is the first one 450 in the MSDU link list. Field MSDU_0 points to the very first 451 MSDU buffer descriptor in the MPDU 452 453 <legal all> 454 */ 455 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c 456 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 457 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 458 459 /* Description RX_MSDU_LINK_3_RESERVED_3A 460 461 <legal 0> 462 */ 463 #define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c 464 #define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 465 #define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 466 467 /* Description RX_MSDU_LINK_4_PN_31_0 468 469 470 471 472 31-0 bits of the 256-bit packet number bitmap. 473 474 <legal all> 475 */ 476 #define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 477 #define RX_MSDU_LINK_4_PN_31_0_LSB 0 478 #define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff 479 480 /* Description RX_MSDU_LINK_5_PN_63_32 481 482 483 484 485 63-32 bits of the 256-bit packet number bitmap. 486 487 <legal all> 488 */ 489 #define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 490 #define RX_MSDU_LINK_5_PN_63_32_LSB 0 491 #define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff 492 493 /* Description RX_MSDU_LINK_6_PN_95_64 494 495 496 497 498 95-64 bits of the 256-bit packet number bitmap. 499 500 <legal all> 501 */ 502 #define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 503 #define RX_MSDU_LINK_6_PN_95_64_LSB 0 504 #define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff 505 506 /* Description RX_MSDU_LINK_7_PN_127_96 507 508 509 510 511 127-96 bits of the 256-bit packet number bitmap. 512 513 <legal all> 514 */ 515 #define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c 516 #define RX_MSDU_LINK_7_PN_127_96_LSB 0 517 #define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff 518 519 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_0 */ 520 521 522 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 523 524 525 /* Description RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 526 527 Address (lower 32 bits) of the MSDU buffer OR 528 MSDU_EXTENSION descriptor OR Link Descriptor 529 530 531 532 In case of 'NULL' pointer, this field is set to 0 533 534 <legal all> 535 */ 536 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 537 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 538 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 539 540 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 541 542 Address (upper 8 bits) of the MSDU buffer OR 543 MSDU_EXTENSION descriptor OR Link Descriptor 544 545 546 547 In case of 'NULL' pointer, this field is set to 0 548 549 <legal all> 550 */ 551 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 552 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 553 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 554 555 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 556 557 Consumer: WBM 558 559 Producer: SW/FW 560 561 562 563 In case of 'NULL' pointer, this field is set to 0 564 565 566 567 Indicates to which buffer manager the buffer OR 568 MSDU_EXTENSION descriptor OR link descriptor that is being 569 pointed to shall be returned after the frame has been 570 processed. It is used by WBM for routing purposes. 571 572 573 574 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 575 to the WMB buffer idle list 576 577 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 578 returned to the WMB idle link descriptor idle list 579 580 <enum 2 FW_BM> This buffer shall be returned to the FW 581 582 <enum 3 SW0_BM> This buffer shall be returned to the SW, 583 ring 0 584 585 <enum 4 SW1_BM> This buffer shall be returned to the SW, 586 ring 1 587 588 <enum 5 SW2_BM> This buffer shall be returned to the SW, 589 ring 2 590 591 <enum 6 SW3_BM> This buffer shall be returned to the SW, 592 ring 3 593 594 <enum 7 SW4_BM> This buffer shall be returned to the SW, 595 ring 4 596 597 598 599 <legal all> 600 */ 601 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 602 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 603 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 604 605 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 606 607 Cookie field exclusively used by SW. 608 609 610 611 In case of 'NULL' pointer, this field is set to 0 612 613 614 615 HW ignores the contents, accept that it passes the 616 programmed value on to other descriptors together with the 617 physical address 618 619 620 621 Field can be used by SW to for example associate the 622 buffers physical address with the virtual address 623 624 The bit definitions as used by SW are within SW HLD 625 specification 626 627 628 629 NOTE: 630 631 The three most significant bits can have a special 632 meaning in case this struct is embedded in a TX_MPDU_DETAILS 633 STRUCT, and field transmit_bw_restriction is set 634 635 636 637 In case of NON punctured transmission: 638 639 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 640 641 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 642 643 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 644 645 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 646 647 648 649 In case of punctured transmission: 650 651 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 652 653 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 654 655 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 656 657 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 658 659 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 660 661 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 662 663 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 664 665 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 666 667 668 669 Note: a punctured transmission is indicated by the 670 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 671 TLV 672 673 674 675 <legal all> 676 */ 677 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 678 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 679 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 680 681 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 682 683 684 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 685 686 Parsed from RX_MSDU_END TLV . In the case MSDU spans 687 over multiple buffers, this field will be valid in the Last 688 buffer used by the MSDU 689 690 691 692 <enum 0 Not_first_msdu> This is not the first MSDU in 693 the MPDU. 694 695 <enum 1 first_msdu> This MSDU is the first one in the 696 MPDU. 697 698 699 700 <legal all> 701 */ 702 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 703 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 704 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 705 706 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 707 708 Consumer: WBM/REO/SW/FW 709 710 Producer: RXDMA 711 712 713 714 Parsed from RX_MSDU_END TLV . In the case MSDU spans 715 over multiple buffers, this field will be valid in the Last 716 buffer used by the MSDU 717 718 719 720 <enum 0 Not_last_msdu> There are more MSDUs linked to 721 this MSDU that belongs to this MPDU 722 723 <enum 1 Last_msdu> this MSDU is the last one in the 724 MPDU. This setting is only allowed in combination with 725 'Msdu_continuation' set to 0. This implies that when an msdu 726 is spread out over multiple buffers and thus 727 msdu_continuation is set, only for the very last buffer of 728 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 729 730 731 732 When both first_msdu_in_mpdu_flag and 733 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 734 belongs to only contains a single MSDU. 735 736 737 738 739 740 <legal all> 741 */ 742 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 743 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 744 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 745 746 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 747 748 When set, this MSDU buffer was not able to hold the 749 entire MSDU. The next buffer will therefor contain 750 additional information related to this MSDU. 751 752 753 754 <legal all> 755 */ 756 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 757 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 758 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 759 760 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 761 762 Parsed from RX_MSDU_START TLV . In the case MSDU spans 763 over multiple buffers, this field will be valid in the First 764 buffer used by MSDU. 765 766 767 768 Full MSDU length in bytes after decapsulation. 769 770 771 772 This field is still valid for MPDU frames without 773 A-MSDU. It still represents MSDU length after decapsulation 774 775 776 777 Or in case of RAW MPDUs, it indicates the length of the 778 entire MPDU (without FCS field) 779 780 <legal all> 781 */ 782 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 783 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 784 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 785 786 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 787 788 Parsed from RX_MSDU_END TLV . In the case MSDU spans 789 over multiple buffers, this field will be valid in the Last 790 buffer used by the MSDU 791 792 793 794 The ID of the REO exit ring where the MSDU frame shall 795 push after (MPDU level) reordering has finished. 796 797 798 799 <enum 0 reo_destination_tcl> Reo will push the frame 800 into the REO2TCL ring 801 802 <enum 1 reo_destination_sw1> Reo will push the frame 803 into the REO2SW1 ring 804 805 <enum 2 reo_destination_sw2> Reo will push the frame 806 into the REO2SW2 ring 807 808 <enum 3 reo_destination_sw3> Reo will push the frame 809 into the REO2SW3 ring 810 811 <enum 4 reo_destination_sw4> Reo will push the frame 812 into the REO2SW4 ring 813 814 <enum 5 reo_destination_release> Reo will push the frame 815 into the REO_release ring 816 817 <enum 6 reo_destination_fw> Reo will push the frame into 818 the REO2FW ring 819 820 <enum 7 reo_destination_sw5> Reo will push the frame 821 into the REO2SW5 ring (REO remaps this in chips without 822 REO2SW5 ring, e.g. Pine) 823 824 <enum 8 reo_destination_sw6> Reo will push the frame 825 into the REO2SW6 ring (REO remaps this in chips without 826 REO2SW6 ring, e.g. Pine) 827 828 <enum 9 reo_destination_9> REO remaps this <enum 10 829 reo_destination_10> REO remaps this 830 831 <enum 11 reo_destination_11> REO remaps this 832 833 <enum 12 reo_destination_12> REO remaps this <enum 13 834 reo_destination_13> REO remaps this 835 836 <enum 14 reo_destination_14> REO remaps this 837 838 <enum 15 reo_destination_15> REO remaps this 839 840 <enum 16 reo_destination_16> REO remaps this 841 842 <enum 17 reo_destination_17> REO remaps this 843 844 <enum 18 reo_destination_18> REO remaps this 845 846 <enum 19 reo_destination_19> REO remaps this 847 848 <enum 20 reo_destination_20> REO remaps this 849 850 <enum 21 reo_destination_21> REO remaps this 851 852 <enum 22 reo_destination_22> REO remaps this 853 854 <enum 23 reo_destination_23> REO remaps this 855 856 <enum 24 reo_destination_24> REO remaps this 857 858 <enum 25 reo_destination_25> REO remaps this 859 860 <enum 26 reo_destination_26> REO remaps this 861 862 <enum 27 reo_destination_27> REO remaps this 863 864 <enum 28 reo_destination_28> REO remaps this 865 866 <enum 29 reo_destination_29> REO remaps this 867 868 <enum 30 reo_destination_30> REO remaps this 869 870 <enum 31 reo_destination_31> REO remaps this 871 872 873 874 <legal all> 875 */ 876 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028 877 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 878 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 879 880 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 881 882 Parsed from RX_MSDU_END TLV . In the case MSDU spans 883 over multiple buffers, this field will be valid in the Last 884 buffer used by the MSDU 885 886 887 888 When set, REO shall drop this MSDU and not forward it to 889 any other ring... 890 891 <legal all> 892 */ 893 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 894 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 895 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 896 897 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 898 899 Parsed from RX_MSDU_END TLV . In the case MSDU spans 900 over multiple buffers, this field will be valid in the Last 901 buffer used by the MSDU 902 903 904 905 Indicates that OLE found a valid SA entry for this MSDU 906 907 <legal all> 908 */ 909 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 910 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 911 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 912 913 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 914 915 Parsed from RX_MSDU_END TLV . In the case MSDU spans 916 over multiple buffers, this field will be valid in the Last 917 buffer used by the MSDU 918 919 920 921 Indicates an unsuccessful MAC source address search due 922 to the expiring of the search timer for this MSDU 923 924 <legal all> 925 */ 926 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028 927 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 928 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 929 930 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 931 932 Parsed from RX_MSDU_END TLV . In the case MSDU spans 933 over multiple buffers, this field will be valid in the Last 934 buffer used by the MSDU 935 936 937 938 Indicates that OLE found a valid DA entry for this MSDU 939 940 <legal all> 941 */ 942 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 943 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 944 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 945 946 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 947 948 Field Only valid if da_is_valid is set 949 950 951 952 Indicates the DA address was a Multicast of Broadcast 953 address for this MSDU 954 955 <legal all> 956 */ 957 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 958 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 959 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 960 961 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 962 963 Parsed from RX_MSDU_END TLV . In the case MSDU spans 964 over multiple buffers, this field will be valid in the Last 965 buffer used by the MSDU 966 967 968 969 Indicates an unsuccessful MAC destination address search 970 due to the expiring of the search timer for this MSDU 971 972 <legal all> 973 */ 974 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028 975 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 976 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 977 978 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 979 980 <legal 0> 981 */ 982 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000028 983 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 984 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 985 986 /* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 987 988 <legal 0> 989 */ 990 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000002c 991 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 992 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 993 994 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_1 */ 995 996 997 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 998 999 1000 /* Description RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1001 1002 Address (lower 32 bits) of the MSDU buffer OR 1003 MSDU_EXTENSION descriptor OR Link Descriptor 1004 1005 1006 1007 In case of 'NULL' pointer, this field is set to 0 1008 1009 <legal all> 1010 */ 1011 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 1012 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1013 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1014 1015 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1016 1017 Address (upper 8 bits) of the MSDU buffer OR 1018 MSDU_EXTENSION descriptor OR Link Descriptor 1019 1020 1021 1022 In case of 'NULL' pointer, this field is set to 0 1023 1024 <legal all> 1025 */ 1026 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 1027 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1028 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1029 1030 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1031 1032 Consumer: WBM 1033 1034 Producer: SW/FW 1035 1036 1037 1038 In case of 'NULL' pointer, this field is set to 0 1039 1040 1041 1042 Indicates to which buffer manager the buffer OR 1043 MSDU_EXTENSION descriptor OR link descriptor that is being 1044 pointed to shall be returned after the frame has been 1045 processed. It is used by WBM for routing purposes. 1046 1047 1048 1049 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1050 to the WMB buffer idle list 1051 1052 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1053 returned to the WMB idle link descriptor idle list 1054 1055 <enum 2 FW_BM> This buffer shall be returned to the FW 1056 1057 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1058 ring 0 1059 1060 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1061 ring 1 1062 1063 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1064 ring 2 1065 1066 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1067 ring 3 1068 1069 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1070 ring 4 1071 1072 1073 1074 <legal all> 1075 */ 1076 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1077 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1078 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 1079 1080 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 1081 1082 Cookie field exclusively used by SW. 1083 1084 1085 1086 In case of 'NULL' pointer, this field is set to 0 1087 1088 1089 1090 HW ignores the contents, accept that it passes the 1091 programmed value on to other descriptors together with the 1092 physical address 1093 1094 1095 1096 Field can be used by SW to for example associate the 1097 buffers physical address with the virtual address 1098 1099 The bit definitions as used by SW are within SW HLD 1100 specification 1101 1102 1103 1104 NOTE: 1105 1106 The three most significant bits can have a special 1107 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1108 STRUCT, and field transmit_bw_restriction is set 1109 1110 1111 1112 In case of NON punctured transmission: 1113 1114 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1115 1116 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1117 1118 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1119 1120 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1121 1122 1123 1124 In case of punctured transmission: 1125 1126 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1127 1128 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1129 1130 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1131 1132 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1133 1134 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1135 1136 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1137 1138 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1139 1140 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1141 1142 1143 1144 Note: a punctured transmission is indicated by the 1145 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1146 TLV 1147 1148 1149 1150 <legal all> 1151 */ 1152 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 1153 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 1154 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 1155 1156 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 1157 1158 1159 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 1160 1161 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1162 over multiple buffers, this field will be valid in the Last 1163 buffer used by the MSDU 1164 1165 1166 1167 <enum 0 Not_first_msdu> This is not the first MSDU in 1168 the MPDU. 1169 1170 <enum 1 first_msdu> This MSDU is the first one in the 1171 MPDU. 1172 1173 1174 1175 <legal all> 1176 */ 1177 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1178 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1179 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1180 1181 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 1182 1183 Consumer: WBM/REO/SW/FW 1184 1185 Producer: RXDMA 1186 1187 1188 1189 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1190 over multiple buffers, this field will be valid in the Last 1191 buffer used by the MSDU 1192 1193 1194 1195 <enum 0 Not_last_msdu> There are more MSDUs linked to 1196 this MSDU that belongs to this MPDU 1197 1198 <enum 1 Last_msdu> this MSDU is the last one in the 1199 MPDU. This setting is only allowed in combination with 1200 'Msdu_continuation' set to 0. This implies that when an msdu 1201 is spread out over multiple buffers and thus 1202 msdu_continuation is set, only for the very last buffer of 1203 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 1204 1205 1206 1207 When both first_msdu_in_mpdu_flag and 1208 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 1209 belongs to only contains a single MSDU. 1210 1211 1212 1213 1214 1215 <legal all> 1216 */ 1217 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1218 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1219 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1220 1221 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 1222 1223 When set, this MSDU buffer was not able to hold the 1224 entire MSDU. The next buffer will therefor contain 1225 additional information related to this MSDU. 1226 1227 1228 1229 <legal all> 1230 */ 1231 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 1232 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1233 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1234 1235 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 1236 1237 Parsed from RX_MSDU_START TLV . In the case MSDU spans 1238 over multiple buffers, this field will be valid in the First 1239 buffer used by MSDU. 1240 1241 1242 1243 Full MSDU length in bytes after decapsulation. 1244 1245 1246 1247 This field is still valid for MPDU frames without 1248 A-MSDU. It still represents MSDU length after decapsulation 1249 1250 1251 1252 Or in case of RAW MPDUs, it indicates the length of the 1253 entire MPDU (without FCS field) 1254 1255 <legal all> 1256 */ 1257 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 1258 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1259 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1260 1261 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 1262 1263 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1264 over multiple buffers, this field will be valid in the Last 1265 buffer used by the MSDU 1266 1267 1268 1269 The ID of the REO exit ring where the MSDU frame shall 1270 push after (MPDU level) reordering has finished. 1271 1272 1273 1274 <enum 0 reo_destination_tcl> Reo will push the frame 1275 into the REO2TCL ring 1276 1277 <enum 1 reo_destination_sw1> Reo will push the frame 1278 into the REO2SW1 ring 1279 1280 <enum 2 reo_destination_sw2> Reo will push the frame 1281 into the REO2SW2 ring 1282 1283 <enum 3 reo_destination_sw3> Reo will push the frame 1284 into the REO2SW3 ring 1285 1286 <enum 4 reo_destination_sw4> Reo will push the frame 1287 into the REO2SW4 ring 1288 1289 <enum 5 reo_destination_release> Reo will push the frame 1290 into the REO_release ring 1291 1292 <enum 6 reo_destination_fw> Reo will push the frame into 1293 the REO2FW ring 1294 1295 <enum 7 reo_destination_sw5> Reo will push the frame 1296 into the REO2SW5 ring (REO remaps this in chips without 1297 REO2SW5 ring, e.g. Pine) 1298 1299 <enum 8 reo_destination_sw6> Reo will push the frame 1300 into the REO2SW6 ring (REO remaps this in chips without 1301 REO2SW6 ring, e.g. Pine) 1302 1303 <enum 9 reo_destination_9> REO remaps this <enum 10 1304 reo_destination_10> REO remaps this 1305 1306 <enum 11 reo_destination_11> REO remaps this 1307 1308 <enum 12 reo_destination_12> REO remaps this <enum 13 1309 reo_destination_13> REO remaps this 1310 1311 <enum 14 reo_destination_14> REO remaps this 1312 1313 <enum 15 reo_destination_15> REO remaps this 1314 1315 <enum 16 reo_destination_16> REO remaps this 1316 1317 <enum 17 reo_destination_17> REO remaps this 1318 1319 <enum 18 reo_destination_18> REO remaps this 1320 1321 <enum 19 reo_destination_19> REO remaps this 1322 1323 <enum 20 reo_destination_20> REO remaps this 1324 1325 <enum 21 reo_destination_21> REO remaps this 1326 1327 <enum 22 reo_destination_22> REO remaps this 1328 1329 <enum 23 reo_destination_23> REO remaps this 1330 1331 <enum 24 reo_destination_24> REO remaps this 1332 1333 <enum 25 reo_destination_25> REO remaps this 1334 1335 <enum 26 reo_destination_26> REO remaps this 1336 1337 <enum 27 reo_destination_27> REO remaps this 1338 1339 <enum 28 reo_destination_28> REO remaps this 1340 1341 <enum 29 reo_destination_29> REO remaps this 1342 1343 <enum 30 reo_destination_30> REO remaps this 1344 1345 <enum 31 reo_destination_31> REO remaps this 1346 1347 1348 1349 <legal all> 1350 */ 1351 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038 1352 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1353 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1354 1355 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1356 1357 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1358 over multiple buffers, this field will be valid in the Last 1359 buffer used by the MSDU 1360 1361 1362 1363 When set, REO shall drop this MSDU and not forward it to 1364 any other ring... 1365 1366 <legal all> 1367 */ 1368 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 1369 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1370 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1371 1372 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1373 1374 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1375 over multiple buffers, this field will be valid in the Last 1376 buffer used by the MSDU 1377 1378 1379 1380 Indicates that OLE found a valid SA entry for this MSDU 1381 1382 <legal all> 1383 */ 1384 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 1385 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1386 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1387 1388 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1389 1390 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1391 over multiple buffers, this field will be valid in the Last 1392 buffer used by the MSDU 1393 1394 1395 1396 Indicates an unsuccessful MAC source address search due 1397 to the expiring of the search timer for this MSDU 1398 1399 <legal all> 1400 */ 1401 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038 1402 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1403 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1404 1405 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1406 1407 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1408 over multiple buffers, this field will be valid in the Last 1409 buffer used by the MSDU 1410 1411 1412 1413 Indicates that OLE found a valid DA entry for this MSDU 1414 1415 <legal all> 1416 */ 1417 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 1418 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1419 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1420 1421 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1422 1423 Field Only valid if da_is_valid is set 1424 1425 1426 1427 Indicates the DA address was a Multicast of Broadcast 1428 address for this MSDU 1429 1430 <legal all> 1431 */ 1432 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 1433 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1434 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1435 1436 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1437 1438 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1439 over multiple buffers, this field will be valid in the Last 1440 buffer used by the MSDU 1441 1442 1443 1444 Indicates an unsuccessful MAC destination address search 1445 due to the expiring of the search timer for this MSDU 1446 1447 <legal all> 1448 */ 1449 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038 1450 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1451 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1452 1453 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1454 1455 <legal 0> 1456 */ 1457 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000038 1458 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1459 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1460 1461 /* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1462 1463 <legal 0> 1464 */ 1465 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000003c 1466 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1467 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1468 1469 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_2 */ 1470 1471 1472 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 1473 1474 1475 /* Description RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1476 1477 Address (lower 32 bits) of the MSDU buffer OR 1478 MSDU_EXTENSION descriptor OR Link Descriptor 1479 1480 1481 1482 In case of 'NULL' pointer, this field is set to 0 1483 1484 <legal all> 1485 */ 1486 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 1487 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1488 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1489 1490 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1491 1492 Address (upper 8 bits) of the MSDU buffer OR 1493 MSDU_EXTENSION descriptor OR Link Descriptor 1494 1495 1496 1497 In case of 'NULL' pointer, this field is set to 0 1498 1499 <legal all> 1500 */ 1501 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 1502 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1503 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1504 1505 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1506 1507 Consumer: WBM 1508 1509 Producer: SW/FW 1510 1511 1512 1513 In case of 'NULL' pointer, this field is set to 0 1514 1515 1516 1517 Indicates to which buffer manager the buffer OR 1518 MSDU_EXTENSION descriptor OR link descriptor that is being 1519 pointed to shall be returned after the frame has been 1520 processed. It is used by WBM for routing purposes. 1521 1522 1523 1524 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1525 to the WMB buffer idle list 1526 1527 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1528 returned to the WMB idle link descriptor idle list 1529 1530 <enum 2 FW_BM> This buffer shall be returned to the FW 1531 1532 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1533 ring 0 1534 1535 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1536 ring 1 1537 1538 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1539 ring 2 1540 1541 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1542 ring 3 1543 1544 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1545 ring 4 1546 1547 1548 1549 <legal all> 1550 */ 1551 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1552 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1553 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 1554 1555 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 1556 1557 Cookie field exclusively used by SW. 1558 1559 1560 1561 In case of 'NULL' pointer, this field is set to 0 1562 1563 1564 1565 HW ignores the contents, accept that it passes the 1566 programmed value on to other descriptors together with the 1567 physical address 1568 1569 1570 1571 Field can be used by SW to for example associate the 1572 buffers physical address with the virtual address 1573 1574 The bit definitions as used by SW are within SW HLD 1575 specification 1576 1577 1578 1579 NOTE: 1580 1581 The three most significant bits can have a special 1582 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1583 STRUCT, and field transmit_bw_restriction is set 1584 1585 1586 1587 In case of NON punctured transmission: 1588 1589 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1590 1591 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1592 1593 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1594 1595 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1596 1597 1598 1599 In case of punctured transmission: 1600 1601 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1602 1603 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1604 1605 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1606 1607 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1608 1609 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1610 1611 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1612 1613 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1614 1615 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1616 1617 1618 1619 Note: a punctured transmission is indicated by the 1620 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1621 TLV 1622 1623 1624 1625 <legal all> 1626 */ 1627 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 1628 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 1629 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 1630 1631 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 1632 1633 1634 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 1635 1636 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1637 over multiple buffers, this field will be valid in the Last 1638 buffer used by the MSDU 1639 1640 1641 1642 <enum 0 Not_first_msdu> This is not the first MSDU in 1643 the MPDU. 1644 1645 <enum 1 first_msdu> This MSDU is the first one in the 1646 MPDU. 1647 1648 1649 1650 <legal all> 1651 */ 1652 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1653 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1654 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1655 1656 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 1657 1658 Consumer: WBM/REO/SW/FW 1659 1660 Producer: RXDMA 1661 1662 1663 1664 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1665 over multiple buffers, this field will be valid in the Last 1666 buffer used by the MSDU 1667 1668 1669 1670 <enum 0 Not_last_msdu> There are more MSDUs linked to 1671 this MSDU that belongs to this MPDU 1672 1673 <enum 1 Last_msdu> this MSDU is the last one in the 1674 MPDU. This setting is only allowed in combination with 1675 'Msdu_continuation' set to 0. This implies that when an msdu 1676 is spread out over multiple buffers and thus 1677 msdu_continuation is set, only for the very last buffer of 1678 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 1679 1680 1681 1682 When both first_msdu_in_mpdu_flag and 1683 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 1684 belongs to only contains a single MSDU. 1685 1686 1687 1688 1689 1690 <legal all> 1691 */ 1692 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1693 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1694 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1695 1696 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 1697 1698 When set, this MSDU buffer was not able to hold the 1699 entire MSDU. The next buffer will therefor contain 1700 additional information related to this MSDU. 1701 1702 1703 1704 <legal all> 1705 */ 1706 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 1707 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1708 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1709 1710 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 1711 1712 Parsed from RX_MSDU_START TLV . In the case MSDU spans 1713 over multiple buffers, this field will be valid in the First 1714 buffer used by MSDU. 1715 1716 1717 1718 Full MSDU length in bytes after decapsulation. 1719 1720 1721 1722 This field is still valid for MPDU frames without 1723 A-MSDU. It still represents MSDU length after decapsulation 1724 1725 1726 1727 Or in case of RAW MPDUs, it indicates the length of the 1728 entire MPDU (without FCS field) 1729 1730 <legal all> 1731 */ 1732 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 1733 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1734 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1735 1736 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 1737 1738 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1739 over multiple buffers, this field will be valid in the Last 1740 buffer used by the MSDU 1741 1742 1743 1744 The ID of the REO exit ring where the MSDU frame shall 1745 push after (MPDU level) reordering has finished. 1746 1747 1748 1749 <enum 0 reo_destination_tcl> Reo will push the frame 1750 into the REO2TCL ring 1751 1752 <enum 1 reo_destination_sw1> Reo will push the frame 1753 into the REO2SW1 ring 1754 1755 <enum 2 reo_destination_sw2> Reo will push the frame 1756 into the REO2SW2 ring 1757 1758 <enum 3 reo_destination_sw3> Reo will push the frame 1759 into the REO2SW3 ring 1760 1761 <enum 4 reo_destination_sw4> Reo will push the frame 1762 into the REO2SW4 ring 1763 1764 <enum 5 reo_destination_release> Reo will push the frame 1765 into the REO_release ring 1766 1767 <enum 6 reo_destination_fw> Reo will push the frame into 1768 the REO2FW ring 1769 1770 <enum 7 reo_destination_sw5> Reo will push the frame 1771 into the REO2SW5 ring (REO remaps this in chips without 1772 REO2SW5 ring, e.g. Pine) 1773 1774 <enum 8 reo_destination_sw6> Reo will push the frame 1775 into the REO2SW6 ring (REO remaps this in chips without 1776 REO2SW6 ring, e.g. Pine) 1777 1778 <enum 9 reo_destination_9> REO remaps this <enum 10 1779 reo_destination_10> REO remaps this 1780 1781 <enum 11 reo_destination_11> REO remaps this 1782 1783 <enum 12 reo_destination_12> REO remaps this <enum 13 1784 reo_destination_13> REO remaps this 1785 1786 <enum 14 reo_destination_14> REO remaps this 1787 1788 <enum 15 reo_destination_15> REO remaps this 1789 1790 <enum 16 reo_destination_16> REO remaps this 1791 1792 <enum 17 reo_destination_17> REO remaps this 1793 1794 <enum 18 reo_destination_18> REO remaps this 1795 1796 <enum 19 reo_destination_19> REO remaps this 1797 1798 <enum 20 reo_destination_20> REO remaps this 1799 1800 <enum 21 reo_destination_21> REO remaps this 1801 1802 <enum 22 reo_destination_22> REO remaps this 1803 1804 <enum 23 reo_destination_23> REO remaps this 1805 1806 <enum 24 reo_destination_24> REO remaps this 1807 1808 <enum 25 reo_destination_25> REO remaps this 1809 1810 <enum 26 reo_destination_26> REO remaps this 1811 1812 <enum 27 reo_destination_27> REO remaps this 1813 1814 <enum 28 reo_destination_28> REO remaps this 1815 1816 <enum 29 reo_destination_29> REO remaps this 1817 1818 <enum 30 reo_destination_30> REO remaps this 1819 1820 <enum 31 reo_destination_31> REO remaps this 1821 1822 1823 1824 <legal all> 1825 */ 1826 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048 1827 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1828 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1829 1830 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1831 1832 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1833 over multiple buffers, this field will be valid in the Last 1834 buffer used by the MSDU 1835 1836 1837 1838 When set, REO shall drop this MSDU and not forward it to 1839 any other ring... 1840 1841 <legal all> 1842 */ 1843 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 1844 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1845 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1846 1847 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1848 1849 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1850 over multiple buffers, this field will be valid in the Last 1851 buffer used by the MSDU 1852 1853 1854 1855 Indicates that OLE found a valid SA entry for this MSDU 1856 1857 <legal all> 1858 */ 1859 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 1860 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1861 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1862 1863 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1864 1865 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1866 over multiple buffers, this field will be valid in the Last 1867 buffer used by the MSDU 1868 1869 1870 1871 Indicates an unsuccessful MAC source address search due 1872 to the expiring of the search timer for this MSDU 1873 1874 <legal all> 1875 */ 1876 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048 1877 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1878 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1879 1880 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1881 1882 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1883 over multiple buffers, this field will be valid in the Last 1884 buffer used by the MSDU 1885 1886 1887 1888 Indicates that OLE found a valid DA entry for this MSDU 1889 1890 <legal all> 1891 */ 1892 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 1893 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1894 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1895 1896 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1897 1898 Field Only valid if da_is_valid is set 1899 1900 1901 1902 Indicates the DA address was a Multicast of Broadcast 1903 address for this MSDU 1904 1905 <legal all> 1906 */ 1907 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 1908 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1909 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1910 1911 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1912 1913 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1914 over multiple buffers, this field will be valid in the Last 1915 buffer used by the MSDU 1916 1917 1918 1919 Indicates an unsuccessful MAC destination address search 1920 due to the expiring of the search timer for this MSDU 1921 1922 <legal all> 1923 */ 1924 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048 1925 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1926 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1927 1928 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1929 1930 <legal 0> 1931 */ 1932 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000048 1933 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1934 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1935 1936 /* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1937 1938 <legal 0> 1939 */ 1940 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000004c 1941 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1942 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1943 1944 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_3 */ 1945 1946 1947 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 1948 1949 1950 /* Description RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1951 1952 Address (lower 32 bits) of the MSDU buffer OR 1953 MSDU_EXTENSION descriptor OR Link Descriptor 1954 1955 1956 1957 In case of 'NULL' pointer, this field is set to 0 1958 1959 <legal all> 1960 */ 1961 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 1962 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1963 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1964 1965 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1966 1967 Address (upper 8 bits) of the MSDU buffer OR 1968 MSDU_EXTENSION descriptor OR Link Descriptor 1969 1970 1971 1972 In case of 'NULL' pointer, this field is set to 0 1973 1974 <legal all> 1975 */ 1976 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 1977 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1978 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1979 1980 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1981 1982 Consumer: WBM 1983 1984 Producer: SW/FW 1985 1986 1987 1988 In case of 'NULL' pointer, this field is set to 0 1989 1990 1991 1992 Indicates to which buffer manager the buffer OR 1993 MSDU_EXTENSION descriptor OR link descriptor that is being 1994 pointed to shall be returned after the frame has been 1995 processed. It is used by WBM for routing purposes. 1996 1997 1998 1999 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2000 to the WMB buffer idle list 2001 2002 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2003 returned to the WMB idle link descriptor idle list 2004 2005 <enum 2 FW_BM> This buffer shall be returned to the FW 2006 2007 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2008 ring 0 2009 2010 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2011 ring 1 2012 2013 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2014 ring 2 2015 2016 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2017 ring 3 2018 2019 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2020 ring 4 2021 2022 2023 2024 <legal all> 2025 */ 2026 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 2027 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2028 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2029 2030 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2031 2032 Cookie field exclusively used by SW. 2033 2034 2035 2036 In case of 'NULL' pointer, this field is set to 0 2037 2038 2039 2040 HW ignores the contents, accept that it passes the 2041 programmed value on to other descriptors together with the 2042 physical address 2043 2044 2045 2046 Field can be used by SW to for example associate the 2047 buffers physical address with the virtual address 2048 2049 The bit definitions as used by SW are within SW HLD 2050 specification 2051 2052 2053 2054 NOTE: 2055 2056 The three most significant bits can have a special 2057 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2058 STRUCT, and field transmit_bw_restriction is set 2059 2060 2061 2062 In case of NON punctured transmission: 2063 2064 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2065 2066 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2067 2068 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2069 2070 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2071 2072 2073 2074 In case of punctured transmission: 2075 2076 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2077 2078 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2079 2080 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2081 2082 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2083 2084 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2085 2086 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2087 2088 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2089 2090 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2091 2092 2093 2094 Note: a punctured transmission is indicated by the 2095 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2096 TLV 2097 2098 2099 2100 <legal all> 2101 */ 2102 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 2103 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 2104 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 2105 2106 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 2107 2108 2109 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 2110 2111 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2112 over multiple buffers, this field will be valid in the Last 2113 buffer used by the MSDU 2114 2115 2116 2117 <enum 0 Not_first_msdu> This is not the first MSDU in 2118 the MPDU. 2119 2120 <enum 1 first_msdu> This MSDU is the first one in the 2121 MPDU. 2122 2123 2124 2125 <legal all> 2126 */ 2127 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2128 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2129 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2130 2131 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 2132 2133 Consumer: WBM/REO/SW/FW 2134 2135 Producer: RXDMA 2136 2137 2138 2139 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2140 over multiple buffers, this field will be valid in the Last 2141 buffer used by the MSDU 2142 2143 2144 2145 <enum 0 Not_last_msdu> There are more MSDUs linked to 2146 this MSDU that belongs to this MPDU 2147 2148 <enum 1 Last_msdu> this MSDU is the last one in the 2149 MPDU. This setting is only allowed in combination with 2150 'Msdu_continuation' set to 0. This implies that when an msdu 2151 is spread out over multiple buffers and thus 2152 msdu_continuation is set, only for the very last buffer of 2153 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 2154 2155 2156 2157 When both first_msdu_in_mpdu_flag and 2158 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 2159 belongs to only contains a single MSDU. 2160 2161 2162 2163 2164 2165 <legal all> 2166 */ 2167 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2168 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2169 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2170 2171 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 2172 2173 When set, this MSDU buffer was not able to hold the 2174 entire MSDU. The next buffer will therefor contain 2175 additional information related to this MSDU. 2176 2177 2178 2179 <legal all> 2180 */ 2181 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 2182 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2183 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2184 2185 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 2186 2187 Parsed from RX_MSDU_START TLV . In the case MSDU spans 2188 over multiple buffers, this field will be valid in the First 2189 buffer used by MSDU. 2190 2191 2192 2193 Full MSDU length in bytes after decapsulation. 2194 2195 2196 2197 This field is still valid for MPDU frames without 2198 A-MSDU. It still represents MSDU length after decapsulation 2199 2200 2201 2202 Or in case of RAW MPDUs, it indicates the length of the 2203 entire MPDU (without FCS field) 2204 2205 <legal all> 2206 */ 2207 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 2208 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2209 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2210 2211 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 2212 2213 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2214 over multiple buffers, this field will be valid in the Last 2215 buffer used by the MSDU 2216 2217 2218 2219 The ID of the REO exit ring where the MSDU frame shall 2220 push after (MPDU level) reordering has finished. 2221 2222 2223 2224 <enum 0 reo_destination_tcl> Reo will push the frame 2225 into the REO2TCL ring 2226 2227 <enum 1 reo_destination_sw1> Reo will push the frame 2228 into the REO2SW1 ring 2229 2230 <enum 2 reo_destination_sw2> Reo will push the frame 2231 into the REO2SW2 ring 2232 2233 <enum 3 reo_destination_sw3> Reo will push the frame 2234 into the REO2SW3 ring 2235 2236 <enum 4 reo_destination_sw4> Reo will push the frame 2237 into the REO2SW4 ring 2238 2239 <enum 5 reo_destination_release> Reo will push the frame 2240 into the REO_release ring 2241 2242 <enum 6 reo_destination_fw> Reo will push the frame into 2243 the REO2FW ring 2244 2245 <enum 7 reo_destination_sw5> Reo will push the frame 2246 into the REO2SW5 ring (REO remaps this in chips without 2247 REO2SW5 ring, e.g. Pine) 2248 2249 <enum 8 reo_destination_sw6> Reo will push the frame 2250 into the REO2SW6 ring (REO remaps this in chips without 2251 REO2SW6 ring, e.g. Pine) 2252 2253 <enum 9 reo_destination_9> REO remaps this <enum 10 2254 reo_destination_10> REO remaps this 2255 2256 <enum 11 reo_destination_11> REO remaps this 2257 2258 <enum 12 reo_destination_12> REO remaps this <enum 13 2259 reo_destination_13> REO remaps this 2260 2261 <enum 14 reo_destination_14> REO remaps this 2262 2263 <enum 15 reo_destination_15> REO remaps this 2264 2265 <enum 16 reo_destination_16> REO remaps this 2266 2267 <enum 17 reo_destination_17> REO remaps this 2268 2269 <enum 18 reo_destination_18> REO remaps this 2270 2271 <enum 19 reo_destination_19> REO remaps this 2272 2273 <enum 20 reo_destination_20> REO remaps this 2274 2275 <enum 21 reo_destination_21> REO remaps this 2276 2277 <enum 22 reo_destination_22> REO remaps this 2278 2279 <enum 23 reo_destination_23> REO remaps this 2280 2281 <enum 24 reo_destination_24> REO remaps this 2282 2283 <enum 25 reo_destination_25> REO remaps this 2284 2285 <enum 26 reo_destination_26> REO remaps this 2286 2287 <enum 27 reo_destination_27> REO remaps this 2288 2289 <enum 28 reo_destination_28> REO remaps this 2290 2291 <enum 29 reo_destination_29> REO remaps this 2292 2293 <enum 30 reo_destination_30> REO remaps this 2294 2295 <enum 31 reo_destination_31> REO remaps this 2296 2297 2298 2299 <legal all> 2300 */ 2301 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058 2302 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 2303 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 2304 2305 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 2306 2307 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2308 over multiple buffers, this field will be valid in the Last 2309 buffer used by the MSDU 2310 2311 2312 2313 When set, REO shall drop this MSDU and not forward it to 2314 any other ring... 2315 2316 <legal all> 2317 */ 2318 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 2319 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 2320 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 2321 2322 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 2323 2324 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2325 over multiple buffers, this field will be valid in the Last 2326 buffer used by the MSDU 2327 2328 2329 2330 Indicates that OLE found a valid SA entry for this MSDU 2331 2332 <legal all> 2333 */ 2334 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 2335 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 2336 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 2337 2338 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 2339 2340 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2341 over multiple buffers, this field will be valid in the Last 2342 buffer used by the MSDU 2343 2344 2345 2346 Indicates an unsuccessful MAC source address search due 2347 to the expiring of the search timer for this MSDU 2348 2349 <legal all> 2350 */ 2351 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058 2352 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 2353 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 2354 2355 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 2356 2357 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2358 over multiple buffers, this field will be valid in the Last 2359 buffer used by the MSDU 2360 2361 2362 2363 Indicates that OLE found a valid DA entry for this MSDU 2364 2365 <legal all> 2366 */ 2367 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 2368 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 2369 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 2370 2371 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 2372 2373 Field Only valid if da_is_valid is set 2374 2375 2376 2377 Indicates the DA address was a Multicast of Broadcast 2378 address for this MSDU 2379 2380 <legal all> 2381 */ 2382 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 2383 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 2384 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 2385 2386 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 2387 2388 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2389 over multiple buffers, this field will be valid in the Last 2390 buffer used by the MSDU 2391 2392 2393 2394 Indicates an unsuccessful MAC destination address search 2395 due to the expiring of the search timer for this MSDU 2396 2397 <legal all> 2398 */ 2399 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058 2400 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 2401 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 2402 2403 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 2404 2405 <legal 0> 2406 */ 2407 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000058 2408 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 2409 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 2410 2411 /* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 2412 2413 <legal 0> 2414 */ 2415 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000005c 2416 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 2417 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 2418 2419 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_4 */ 2420 2421 2422 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 2423 2424 2425 /* Description RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 2426 2427 Address (lower 32 bits) of the MSDU buffer OR 2428 MSDU_EXTENSION descriptor OR Link Descriptor 2429 2430 2431 2432 In case of 'NULL' pointer, this field is set to 0 2433 2434 <legal all> 2435 */ 2436 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 2437 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2438 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2439 2440 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 2441 2442 Address (upper 8 bits) of the MSDU buffer OR 2443 MSDU_EXTENSION descriptor OR Link Descriptor 2444 2445 2446 2447 In case of 'NULL' pointer, this field is set to 0 2448 2449 <legal all> 2450 */ 2451 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 2452 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2453 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2454 2455 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 2456 2457 Consumer: WBM 2458 2459 Producer: SW/FW 2460 2461 2462 2463 In case of 'NULL' pointer, this field is set to 0 2464 2465 2466 2467 Indicates to which buffer manager the buffer OR 2468 MSDU_EXTENSION descriptor OR link descriptor that is being 2469 pointed to shall be returned after the frame has been 2470 processed. It is used by WBM for routing purposes. 2471 2472 2473 2474 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2475 to the WMB buffer idle list 2476 2477 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2478 returned to the WMB idle link descriptor idle list 2479 2480 <enum 2 FW_BM> This buffer shall be returned to the FW 2481 2482 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2483 ring 0 2484 2485 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2486 ring 1 2487 2488 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2489 ring 2 2490 2491 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2492 ring 3 2493 2494 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2495 ring 4 2496 2497 2498 2499 <legal all> 2500 */ 2501 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2502 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2503 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2504 2505 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2506 2507 Cookie field exclusively used by SW. 2508 2509 2510 2511 In case of 'NULL' pointer, this field is set to 0 2512 2513 2514 2515 HW ignores the contents, accept that it passes the 2516 programmed value on to other descriptors together with the 2517 physical address 2518 2519 2520 2521 Field can be used by SW to for example associate the 2522 buffers physical address with the virtual address 2523 2524 The bit definitions as used by SW are within SW HLD 2525 specification 2526 2527 2528 2529 NOTE: 2530 2531 The three most significant bits can have a special 2532 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2533 STRUCT, and field transmit_bw_restriction is set 2534 2535 2536 2537 In case of NON punctured transmission: 2538 2539 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2540 2541 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2542 2543 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2544 2545 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2546 2547 2548 2549 In case of punctured transmission: 2550 2551 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2552 2553 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2554 2555 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2556 2557 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2558 2559 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2560 2561 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2562 2563 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2564 2565 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2566 2567 2568 2569 Note: a punctured transmission is indicated by the 2570 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2571 TLV 2572 2573 2574 2575 <legal all> 2576 */ 2577 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 2578 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 2579 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 2580 2581 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 2582 2583 2584 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 2585 2586 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2587 over multiple buffers, this field will be valid in the Last 2588 buffer used by the MSDU 2589 2590 2591 2592 <enum 0 Not_first_msdu> This is not the first MSDU in 2593 the MPDU. 2594 2595 <enum 1 first_msdu> This MSDU is the first one in the 2596 MPDU. 2597 2598 2599 2600 <legal all> 2601 */ 2602 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 2603 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2604 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2605 2606 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 2607 2608 Consumer: WBM/REO/SW/FW 2609 2610 Producer: RXDMA 2611 2612 2613 2614 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2615 over multiple buffers, this field will be valid in the Last 2616 buffer used by the MSDU 2617 2618 2619 2620 <enum 0 Not_last_msdu> There are more MSDUs linked to 2621 this MSDU that belongs to this MPDU 2622 2623 <enum 1 Last_msdu> this MSDU is the last one in the 2624 MPDU. This setting is only allowed in combination with 2625 'Msdu_continuation' set to 0. This implies that when an msdu 2626 is spread out over multiple buffers and thus 2627 msdu_continuation is set, only for the very last buffer of 2628 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 2629 2630 2631 2632 When both first_msdu_in_mpdu_flag and 2633 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 2634 belongs to only contains a single MSDU. 2635 2636 2637 2638 2639 2640 <legal all> 2641 */ 2642 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 2643 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2644 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2645 2646 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 2647 2648 When set, this MSDU buffer was not able to hold the 2649 entire MSDU. The next buffer will therefor contain 2650 additional information related to this MSDU. 2651 2652 2653 2654 <legal all> 2655 */ 2656 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 2657 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2658 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2659 2660 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 2661 2662 Parsed from RX_MSDU_START TLV . In the case MSDU spans 2663 over multiple buffers, this field will be valid in the First 2664 buffer used by MSDU. 2665 2666 2667 2668 Full MSDU length in bytes after decapsulation. 2669 2670 2671 2672 This field is still valid for MPDU frames without 2673 A-MSDU. It still represents MSDU length after decapsulation 2674 2675 2676 2677 Or in case of RAW MPDUs, it indicates the length of the 2678 entire MPDU (without FCS field) 2679 2680 <legal all> 2681 */ 2682 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 2683 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2684 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2685 2686 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 2687 2688 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2689 over multiple buffers, this field will be valid in the Last 2690 buffer used by the MSDU 2691 2692 2693 2694 The ID of the REO exit ring where the MSDU frame shall 2695 push after (MPDU level) reordering has finished. 2696 2697 2698 2699 <enum 0 reo_destination_tcl> Reo will push the frame 2700 into the REO2TCL ring 2701 2702 <enum 1 reo_destination_sw1> Reo will push the frame 2703 into the REO2SW1 ring 2704 2705 <enum 2 reo_destination_sw2> Reo will push the frame 2706 into the REO2SW2 ring 2707 2708 <enum 3 reo_destination_sw3> Reo will push the frame 2709 into the REO2SW3 ring 2710 2711 <enum 4 reo_destination_sw4> Reo will push the frame 2712 into the REO2SW4 ring 2713 2714 <enum 5 reo_destination_release> Reo will push the frame 2715 into the REO_release ring 2716 2717 <enum 6 reo_destination_fw> Reo will push the frame into 2718 the REO2FW ring 2719 2720 <enum 7 reo_destination_sw5> Reo will push the frame 2721 into the REO2SW5 ring (REO remaps this in chips without 2722 REO2SW5 ring, e.g. Pine) 2723 2724 <enum 8 reo_destination_sw6> Reo will push the frame 2725 into the REO2SW6 ring (REO remaps this in chips without 2726 REO2SW6 ring, e.g. Pine) 2727 2728 <enum 9 reo_destination_9> REO remaps this <enum 10 2729 reo_destination_10> REO remaps this 2730 2731 <enum 11 reo_destination_11> REO remaps this 2732 2733 <enum 12 reo_destination_12> REO remaps this <enum 13 2734 reo_destination_13> REO remaps this 2735 2736 <enum 14 reo_destination_14> REO remaps this 2737 2738 <enum 15 reo_destination_15> REO remaps this 2739 2740 <enum 16 reo_destination_16> REO remaps this 2741 2742 <enum 17 reo_destination_17> REO remaps this 2743 2744 <enum 18 reo_destination_18> REO remaps this 2745 2746 <enum 19 reo_destination_19> REO remaps this 2747 2748 <enum 20 reo_destination_20> REO remaps this 2749 2750 <enum 21 reo_destination_21> REO remaps this 2751 2752 <enum 22 reo_destination_22> REO remaps this 2753 2754 <enum 23 reo_destination_23> REO remaps this 2755 2756 <enum 24 reo_destination_24> REO remaps this 2757 2758 <enum 25 reo_destination_25> REO remaps this 2759 2760 <enum 26 reo_destination_26> REO remaps this 2761 2762 <enum 27 reo_destination_27> REO remaps this 2763 2764 <enum 28 reo_destination_28> REO remaps this 2765 2766 <enum 29 reo_destination_29> REO remaps this 2767 2768 <enum 30 reo_destination_30> REO remaps this 2769 2770 <enum 31 reo_destination_31> REO remaps this 2771 2772 2773 2774 <legal all> 2775 */ 2776 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068 2777 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 2778 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 2779 2780 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 2781 2782 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2783 over multiple buffers, this field will be valid in the Last 2784 buffer used by the MSDU 2785 2786 2787 2788 When set, REO shall drop this MSDU and not forward it to 2789 any other ring... 2790 2791 <legal all> 2792 */ 2793 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 2794 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 2795 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 2796 2797 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 2798 2799 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2800 over multiple buffers, this field will be valid in the Last 2801 buffer used by the MSDU 2802 2803 2804 2805 Indicates that OLE found a valid SA entry for this MSDU 2806 2807 <legal all> 2808 */ 2809 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 2810 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 2811 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 2812 2813 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 2814 2815 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2816 over multiple buffers, this field will be valid in the Last 2817 buffer used by the MSDU 2818 2819 2820 2821 Indicates an unsuccessful MAC source address search due 2822 to the expiring of the search timer for this MSDU 2823 2824 <legal all> 2825 */ 2826 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068 2827 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 2828 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 2829 2830 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 2831 2832 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2833 over multiple buffers, this field will be valid in the Last 2834 buffer used by the MSDU 2835 2836 2837 2838 Indicates that OLE found a valid DA entry for this MSDU 2839 2840 <legal all> 2841 */ 2842 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 2843 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 2844 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 2845 2846 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 2847 2848 Field Only valid if da_is_valid is set 2849 2850 2851 2852 Indicates the DA address was a Multicast of Broadcast 2853 address for this MSDU 2854 2855 <legal all> 2856 */ 2857 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 2858 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 2859 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 2860 2861 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 2862 2863 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2864 over multiple buffers, this field will be valid in the Last 2865 buffer used by the MSDU 2866 2867 2868 2869 Indicates an unsuccessful MAC destination address search 2870 due to the expiring of the search timer for this MSDU 2871 2872 <legal all> 2873 */ 2874 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068 2875 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 2876 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 2877 2878 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 2879 2880 <legal 0> 2881 */ 2882 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000068 2883 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 2884 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 2885 2886 /* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 2887 2888 <legal 0> 2889 */ 2890 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000006c 2891 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 2892 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 2893 2894 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_5 */ 2895 2896 2897 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 2898 2899 2900 /* Description RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 2901 2902 Address (lower 32 bits) of the MSDU buffer OR 2903 MSDU_EXTENSION descriptor OR Link Descriptor 2904 2905 2906 2907 In case of 'NULL' pointer, this field is set to 0 2908 2909 <legal all> 2910 */ 2911 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 2912 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2913 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2914 2915 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 2916 2917 Address (upper 8 bits) of the MSDU buffer OR 2918 MSDU_EXTENSION descriptor OR Link Descriptor 2919 2920 2921 2922 In case of 'NULL' pointer, this field is set to 0 2923 2924 <legal all> 2925 */ 2926 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 2927 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2928 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2929 2930 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 2931 2932 Consumer: WBM 2933 2934 Producer: SW/FW 2935 2936 2937 2938 In case of 'NULL' pointer, this field is set to 0 2939 2940 2941 2942 Indicates to which buffer manager the buffer OR 2943 MSDU_EXTENSION descriptor OR link descriptor that is being 2944 pointed to shall be returned after the frame has been 2945 processed. It is used by WBM for routing purposes. 2946 2947 2948 2949 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2950 to the WMB buffer idle list 2951 2952 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2953 returned to the WMB idle link descriptor idle list 2954 2955 <enum 2 FW_BM> This buffer shall be returned to the FW 2956 2957 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2958 ring 0 2959 2960 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2961 ring 1 2962 2963 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2964 ring 2 2965 2966 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2967 ring 3 2968 2969 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2970 ring 4 2971 2972 2973 2974 <legal all> 2975 */ 2976 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2977 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2978 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2979 2980 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2981 2982 Cookie field exclusively used by SW. 2983 2984 2985 2986 In case of 'NULL' pointer, this field is set to 0 2987 2988 2989 2990 HW ignores the contents, accept that it passes the 2991 programmed value on to other descriptors together with the 2992 physical address 2993 2994 2995 2996 Field can be used by SW to for example associate the 2997 buffers physical address with the virtual address 2998 2999 The bit definitions as used by SW are within SW HLD 3000 specification 3001 3002 3003 3004 NOTE: 3005 3006 The three most significant bits can have a special 3007 meaning in case this struct is embedded in a TX_MPDU_DETAILS 3008 STRUCT, and field transmit_bw_restriction is set 3009 3010 3011 3012 In case of NON punctured transmission: 3013 3014 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 3015 3016 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 3017 3018 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 3019 3020 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 3021 3022 3023 3024 In case of punctured transmission: 3025 3026 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 3027 3028 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 3029 3030 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 3031 3032 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 3033 3034 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 3035 3036 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 3037 3038 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 3039 3040 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 3041 3042 3043 3044 Note: a punctured transmission is indicated by the 3045 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 3046 TLV 3047 3048 3049 3050 <legal all> 3051 */ 3052 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 3053 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 3054 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 3055 3056 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 3057 3058 3059 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 3060 3061 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3062 over multiple buffers, this field will be valid in the Last 3063 buffer used by the MSDU 3064 3065 3066 3067 <enum 0 Not_first_msdu> This is not the first MSDU in 3068 the MPDU. 3069 3070 <enum 1 first_msdu> This MSDU is the first one in the 3071 MPDU. 3072 3073 3074 3075 <legal all> 3076 */ 3077 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3078 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3079 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3080 3081 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 3082 3083 Consumer: WBM/REO/SW/FW 3084 3085 Producer: RXDMA 3086 3087 3088 3089 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3090 over multiple buffers, this field will be valid in the Last 3091 buffer used by the MSDU 3092 3093 3094 3095 <enum 0 Not_last_msdu> There are more MSDUs linked to 3096 this MSDU that belongs to this MPDU 3097 3098 <enum 1 Last_msdu> this MSDU is the last one in the 3099 MPDU. This setting is only allowed in combination with 3100 'Msdu_continuation' set to 0. This implies that when an msdu 3101 is spread out over multiple buffers and thus 3102 msdu_continuation is set, only for the very last buffer of 3103 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 3104 3105 3106 3107 When both first_msdu_in_mpdu_flag and 3108 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 3109 belongs to only contains a single MSDU. 3110 3111 3112 3113 3114 3115 <legal all> 3116 */ 3117 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3118 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3119 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3120 3121 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 3122 3123 When set, this MSDU buffer was not able to hold the 3124 entire MSDU. The next buffer will therefor contain 3125 additional information related to this MSDU. 3126 3127 3128 3129 <legal all> 3130 */ 3131 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 3132 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3133 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3134 3135 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 3136 3137 Parsed from RX_MSDU_START TLV . In the case MSDU spans 3138 over multiple buffers, this field will be valid in the First 3139 buffer used by MSDU. 3140 3141 3142 3143 Full MSDU length in bytes after decapsulation. 3144 3145 3146 3147 This field is still valid for MPDU frames without 3148 A-MSDU. It still represents MSDU length after decapsulation 3149 3150 3151 3152 Or in case of RAW MPDUs, it indicates the length of the 3153 entire MPDU (without FCS field) 3154 3155 <legal all> 3156 */ 3157 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 3158 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3159 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3160 3161 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 3162 3163 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3164 over multiple buffers, this field will be valid in the Last 3165 buffer used by the MSDU 3166 3167 3168 3169 The ID of the REO exit ring where the MSDU frame shall 3170 push after (MPDU level) reordering has finished. 3171 3172 3173 3174 <enum 0 reo_destination_tcl> Reo will push the frame 3175 into the REO2TCL ring 3176 3177 <enum 1 reo_destination_sw1> Reo will push the frame 3178 into the REO2SW1 ring 3179 3180 <enum 2 reo_destination_sw2> Reo will push the frame 3181 into the REO2SW2 ring 3182 3183 <enum 3 reo_destination_sw3> Reo will push the frame 3184 into the REO2SW3 ring 3185 3186 <enum 4 reo_destination_sw4> Reo will push the frame 3187 into the REO2SW4 ring 3188 3189 <enum 5 reo_destination_release> Reo will push the frame 3190 into the REO_release ring 3191 3192 <enum 6 reo_destination_fw> Reo will push the frame into 3193 the REO2FW ring 3194 3195 <enum 7 reo_destination_sw5> Reo will push the frame 3196 into the REO2SW5 ring (REO remaps this in chips without 3197 REO2SW5 ring, e.g. Pine) 3198 3199 <enum 8 reo_destination_sw6> Reo will push the frame 3200 into the REO2SW6 ring (REO remaps this in chips without 3201 REO2SW6 ring, e.g. Pine) 3202 3203 <enum 9 reo_destination_9> REO remaps this <enum 10 3204 reo_destination_10> REO remaps this 3205 3206 <enum 11 reo_destination_11> REO remaps this 3207 3208 <enum 12 reo_destination_12> REO remaps this <enum 13 3209 reo_destination_13> REO remaps this 3210 3211 <enum 14 reo_destination_14> REO remaps this 3212 3213 <enum 15 reo_destination_15> REO remaps this 3214 3215 <enum 16 reo_destination_16> REO remaps this 3216 3217 <enum 17 reo_destination_17> REO remaps this 3218 3219 <enum 18 reo_destination_18> REO remaps this 3220 3221 <enum 19 reo_destination_19> REO remaps this 3222 3223 <enum 20 reo_destination_20> REO remaps this 3224 3225 <enum 21 reo_destination_21> REO remaps this 3226 3227 <enum 22 reo_destination_22> REO remaps this 3228 3229 <enum 23 reo_destination_23> REO remaps this 3230 3231 <enum 24 reo_destination_24> REO remaps this 3232 3233 <enum 25 reo_destination_25> REO remaps this 3234 3235 <enum 26 reo_destination_26> REO remaps this 3236 3237 <enum 27 reo_destination_27> REO remaps this 3238 3239 <enum 28 reo_destination_28> REO remaps this 3240 3241 <enum 29 reo_destination_29> REO remaps this 3242 3243 <enum 30 reo_destination_30> REO remaps this 3244 3245 <enum 31 reo_destination_31> REO remaps this 3246 3247 3248 3249 <legal all> 3250 */ 3251 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078 3252 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 3253 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 3254 3255 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 3256 3257 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3258 over multiple buffers, this field will be valid in the Last 3259 buffer used by the MSDU 3260 3261 3262 3263 When set, REO shall drop this MSDU and not forward it to 3264 any other ring... 3265 3266 <legal all> 3267 */ 3268 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 3269 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 3270 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 3271 3272 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 3273 3274 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3275 over multiple buffers, this field will be valid in the Last 3276 buffer used by the MSDU 3277 3278 3279 3280 Indicates that OLE found a valid SA entry for this MSDU 3281 3282 <legal all> 3283 */ 3284 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 3285 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 3286 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 3287 3288 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 3289 3290 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3291 over multiple buffers, this field will be valid in the Last 3292 buffer used by the MSDU 3293 3294 3295 3296 Indicates an unsuccessful MAC source address search due 3297 to the expiring of the search timer for this MSDU 3298 3299 <legal all> 3300 */ 3301 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078 3302 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 3303 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 3304 3305 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 3306 3307 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3308 over multiple buffers, this field will be valid in the Last 3309 buffer used by the MSDU 3310 3311 3312 3313 Indicates that OLE found a valid DA entry for this MSDU 3314 3315 <legal all> 3316 */ 3317 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 3318 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 3319 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 3320 3321 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 3322 3323 Field Only valid if da_is_valid is set 3324 3325 3326 3327 Indicates the DA address was a Multicast of Broadcast 3328 address for this MSDU 3329 3330 <legal all> 3331 */ 3332 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 3333 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 3334 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 3335 3336 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 3337 3338 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3339 over multiple buffers, this field will be valid in the Last 3340 buffer used by the MSDU 3341 3342 3343 3344 Indicates an unsuccessful MAC destination address search 3345 due to the expiring of the search timer for this MSDU 3346 3347 <legal all> 3348 */ 3349 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078 3350 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 3351 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 3352 3353 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 3354 3355 <legal 0> 3356 */ 3357 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000078 3358 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 3359 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 3360 3361 /* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 3362 3363 <legal 0> 3364 */ 3365 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000007c 3366 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 3367 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 3368 3369 3370 #endif // _RX_MSDU_LINK_H_ 3371