1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_REO_QUEUE_H_ 25 #define _RX_REO_QUEUE_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_descriptor_header.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct uniform_descriptor_header descriptor_header; 35 // 1 receive_queue_number[15:0], reserved_1b[31:16] 36 // 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26] 37 // 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31] 38 // 4 pn_31_0[31:0] 39 // 5 pn_63_32[31:0] 40 // 6 pn_95_64[31:0] 41 // 7 pn_127_96[31:0] 42 // 8 last_rx_enqueue_timestamp[31:0] 43 // 9 last_rx_dequeue_timestamp[31:0] 44 // 10 ptr_to_next_aging_queue_31_0[31:0] 45 // 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8] 46 // 12 ptr_to_previous_aging_queue_31_0[31:0] 47 // 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8] 48 // 14 rx_bitmap_31_0[31:0] 49 // 15 rx_bitmap_63_32[31:0] 50 // 16 rx_bitmap_95_64[31:0] 51 // 17 rx_bitmap_127_96[31:0] 52 // 18 rx_bitmap_159_128[31:0] 53 // 19 rx_bitmap_191_160[31:0] 54 // 20 rx_bitmap_223_192[31:0] 55 // 21 rx_bitmap_255_224[31:0] 56 // 22 current_mpdu_count[6:0], current_msdu_count[31:7] 57 // 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] 58 // 24 frames_in_order_count[23:0], bar_received_count[31:24] 59 // 25 mpdu_frames_processed_count[31:0] 60 // 26 msdu_frames_processed_count[31:0] 61 // 27 total_processed_byte_count[31:0] 62 // 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] 63 // 29 reserved_29[31:0] 64 // 30 reserved_30[31:0] 65 // 31 reserved_31[31:0] 66 // 67 // ################ END SUMMARY ################# 68 69 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 70 71 struct rx_reo_queue { 72 struct uniform_descriptor_header descriptor_header; 73 uint32_t receive_queue_number : 16, //[15:0] 74 reserved_1b : 16; //[31:16] 75 uint32_t vld : 1, //[0] 76 associated_link_descriptor_counter: 2, //[2:1] 77 disable_duplicate_detection : 1, //[3] 78 soft_reorder_enable : 1, //[4] 79 ac : 2, //[6:5] 80 bar : 1, //[7] 81 rty : 1, //[8] 82 chk_2k_mode : 1, //[9] 83 oor_mode : 1, //[10] 84 ba_window_size : 8, //[18:11] 85 pn_check_needed : 1, //[19] 86 pn_shall_be_even : 1, //[20] 87 pn_shall_be_uneven : 1, //[21] 88 pn_handling_enable : 1, //[22] 89 pn_size : 2, //[24:23] 90 ignore_ampdu_flag : 1, //[25] 91 reserved_2b : 6; //[31:26] 92 uint32_t svld : 1, //[0] 93 ssn : 12, //[12:1] 94 current_index : 8, //[20:13] 95 seq_2k_error_detected_flag : 1, //[21] 96 pn_error_detected_flag : 1, //[22] 97 reserved_3a : 8, //[30:23] 98 pn_valid : 1; //[31] 99 uint32_t pn_31_0 : 32; //[31:0] 100 uint32_t pn_63_32 : 32; //[31:0] 101 uint32_t pn_95_64 : 32; //[31:0] 102 uint32_t pn_127_96 : 32; //[31:0] 103 uint32_t last_rx_enqueue_timestamp : 32; //[31:0] 104 uint32_t last_rx_dequeue_timestamp : 32; //[31:0] 105 uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0] 106 uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0] 107 reserved_11a : 24; //[31:8] 108 uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0] 109 uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0] 110 reserved_13a : 24; //[31:8] 111 uint32_t rx_bitmap_31_0 : 32; //[31:0] 112 uint32_t rx_bitmap_63_32 : 32; //[31:0] 113 uint32_t rx_bitmap_95_64 : 32; //[31:0] 114 uint32_t rx_bitmap_127_96 : 32; //[31:0] 115 uint32_t rx_bitmap_159_128 : 32; //[31:0] 116 uint32_t rx_bitmap_191_160 : 32; //[31:0] 117 uint32_t rx_bitmap_223_192 : 32; //[31:0] 118 uint32_t rx_bitmap_255_224 : 32; //[31:0] 119 uint32_t current_mpdu_count : 7, //[6:0] 120 current_msdu_count : 25; //[31:7] 121 uint32_t reserved_23 : 4, //[3:0] 122 timeout_count : 6, //[9:4] 123 forward_due_to_bar_count : 6, //[15:10] 124 duplicate_count : 16; //[31:16] 125 uint32_t frames_in_order_count : 24, //[23:0] 126 bar_received_count : 8; //[31:24] 127 uint32_t mpdu_frames_processed_count : 32; //[31:0] 128 uint32_t msdu_frames_processed_count : 32; //[31:0] 129 uint32_t total_processed_byte_count : 32; //[31:0] 130 uint32_t late_receive_mpdu_count : 12, //[11:0] 131 window_jump_2k : 4, //[15:12] 132 hole_count : 16; //[31:16] 133 uint32_t reserved_29 : 32; //[31:0] 134 uint32_t reserved_30 : 32; //[31:0] 135 uint32_t reserved_31 : 32; //[31:0] 136 }; 137 138 /* 139 140 struct uniform_descriptor_header descriptor_header 141 142 Details about which module owns this struct. 143 144 Note that sub field Buffer_type shall be set to 145 Receive_REO_queue_descriptor 146 147 receive_queue_number 148 149 Indicates the MPDU queue ID to which this MPDU link 150 descriptor belongs 151 152 Used for tracking and debugging 153 154 <legal all> 155 156 reserved_1b 157 158 <legal 0> 159 160 vld 161 162 Valid bit indicating a session is established and the 163 queue descriptor is valid(Filled by SW) 164 165 <legal all> 166 167 associated_link_descriptor_counter 168 169 Indicates which of the 3 link descriptor counters shall 170 be incremented or decremented when link descriptors are 171 added or removed from this flow queue. 172 173 MSDU link descriptors related with MPDUs stored in the 174 re-order buffer shall also be included in this count. 175 176 177 178 <legal 0-2> 179 180 disable_duplicate_detection 181 182 When set, do not perform any duplicate detection. 183 184 185 186 <legal all> 187 188 soft_reorder_enable 189 190 When set, REO has been instructed to not perform the 191 actual re-ordering of frames for this queue, but just to 192 insert the reorder opcodes. 193 194 195 196 Note that this implies that REO is also not going to 197 perform any MSDU level operations, and the entire MPDU (and 198 thus pointer to the MSDU link descriptor) will be pushed to 199 a destination ring that SW has programmed in a SW 200 programmable configuration register in REO 201 202 203 204 <legal all> 205 206 ac 207 208 Indicates which access category the queue descriptor 209 belongs to(filled by SW) 210 211 <legal all> 212 213 bar 214 215 Indicates if BAR has been received (mostly used for 216 debug purpose and this is filled by REO) 217 218 <legal all> 219 220 rty 221 222 Retry bit is checked if this bit is set. 223 224 <legal all> 225 226 chk_2k_mode 227 228 Indicates what type of operation is expected from Reo 229 when the received frame SN falls within the 2K window 230 231 232 233 See REO MLD document for programming details. 234 235 <legal all> 236 237 oor_mode 238 239 Out of Order mode: 240 241 Indicates what type of operation is expected when the 242 received frame falls within the OOR window. 243 244 245 246 See REO MLD document for programming details. 247 248 <legal all> 249 250 ba_window_size 251 252 Indicates the negotiated (window size + 1). 253 254 It can go up to Max of 256bits. 255 256 257 258 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 259 (means non-BA session, with window size of 0). The 3 values 260 here are the main values validated, but other values should 261 work as well. 262 263 264 265 A BA window size of 0 (=> one frame entry bitmat), means 266 that there is NO RX_REO_QUEUE_EXT descriptor following this 267 RX_REO_QUEUE STRUCT in memory 268 269 270 271 A BA window size of 1 - 105, means that there is 1 272 RX_REO_QUEUE_EXT descriptor directly following this 273 RX_REO_QUEUE STRUCT in memory. 274 275 276 277 A BA window size of 106 - 210, means that there are 2 278 RX_REO_QUEUE_EXT descriptors directly following this 279 RX_REO_QUEUE STRUCT in memory 280 281 282 283 A BA window size of 211 - 256, means that there are 3 284 RX_REO_QUEUE_EXT descriptors directly following this 285 RX_REO_QUEUE STRUCT in memory 286 287 288 289 <legal 0 - 255> 290 291 pn_check_needed 292 293 When set, REO shall perform the PN increment check 294 295 <legal all> 296 297 pn_shall_be_even 298 299 Field only valid when 'pn_check_needed' is set. 300 301 302 303 When set, REO shall confirm that the received PN number 304 is not only incremented, but also always an even number 305 306 <legal all> 307 308 pn_shall_be_uneven 309 310 Field only valid when 'pn_check_needed' is set. 311 312 313 314 When set, REO shall confirm that the received PN number 315 is not only incremented, but also always an uneven number 316 317 <legal all> 318 319 pn_handling_enable 320 321 Field only valid when 'pn_check_needed' is set. 322 323 324 325 When set, and REO detected a PN error, HW shall set the 326 'pn_error_detected_flag'. 327 328 <legal all> 329 330 pn_size 331 332 Size of the PN field check. 333 334 Needed for wrap around handling... 335 336 337 338 <enum 0 pn_size_24> 339 340 <enum 1 pn_size_48> 341 342 <enum 2 pn_size_128> 343 344 345 346 <legal 0-2> 347 348 ignore_ampdu_flag 349 350 When set, REO shall ignore the ampdu_flag on the 351 entrance descriptor for this queue. 352 353 <legal all> 354 355 reserved_2b 356 357 <legal 0> 358 359 svld 360 361 Sequence number in next field is valid one. It can be 362 filled by SW if the want to fill in the any negotiated SSN, 363 otherwise REO will fill the sequence number of first 364 received packet and set this bit to 1. 365 366 <legal all> 367 368 ssn 369 370 Starting Sequence number of the session, this changes 371 whenever window moves. (can be filled by SW then maintained 372 by REO) 373 374 <legal all> 375 376 current_index 377 378 Points to last forwarded packet 379 380 <legal all> 381 382 seq_2k_error_detected_flag 383 384 Set by REO, can only be cleared by SW 385 386 387 388 When set, REO has detected a 2k error jump in the 389 sequence number and from that moment forward, all new frames 390 are forwarded directly to FW, without duplicate detect, 391 reordering, etc. 392 393 <legal all> 394 395 pn_error_detected_flag 396 397 Set by REO, can only be cleared by SW 398 399 400 401 When set, REO has detected a PN error and from that 402 moment forward, all new frames are forwarded directly to FW, 403 without duplicate detect, reordering, etc. 404 405 <legal all> 406 407 reserved_3a 408 409 <legal 0> 410 411 pn_valid 412 413 PN number in next fields are valid. It can be filled by 414 SW if it wants to fill in the any negotiated SSN, otherwise 415 REO will fill the pn based on the first received packet and 416 set this bit to 1. 417 418 <legal all> 419 420 pn_31_0 421 422 423 <legal all> 424 425 pn_63_32 426 427 Bits [63:32] of the PN number. 428 429 <legal all> 430 431 pn_95_64 432 433 Bits [95:64] of the PN number. 434 435 <legal all> 436 437 pn_127_96 438 439 Bits [127:96] of the PN number. 440 441 <legal all> 442 443 last_rx_enqueue_timestamp 444 445 This timestamp is updated when an MPDU is received and 446 accesses this Queue Descriptor. It does not include the 447 access due to Command TLVs or Aging (which will be updated 448 in Last_rx_dequeue_timestamp). 449 450 <legal all> 451 452 last_rx_dequeue_timestamp 453 454 This timestamp is used for Aging. When an MPDU or 455 multiple MPDUs are forwarded, either due to window movement, 456 bar, aging or command flush, this timestamp is updated. Also 457 when the bitmap is all zero and the first time an MPDU is 458 queued (opcode=QCUR), this timestamp is updated for aging. 459 460 <legal all> 461 462 ptr_to_next_aging_queue_31_0 463 464 Address (address bits 31-0)of next RX_REO_QUEUE 465 descriptor in the 'receive timestamp' ordered list. 466 467 From it the Position of this queue descriptor in the per 468 AC aging waitlist can be derived. 469 470 Value 0x0 indicates the 'NULL' pointer which implies 471 that this is the last entry in the list. 472 473 <legal all> 474 475 ptr_to_next_aging_queue_39_32 476 477 Address (address bits 39-32)of next RX_REO_QUEUE 478 descriptor in the 'receive timestamp' ordered list. 479 480 From it the Position of this queue descriptor in the per 481 AC aging waitlist can be derived. 482 483 Value 0x0 indicates the 'NULL' pointer which implies 484 that this is the last entry in the list. 485 486 <legal all> 487 488 reserved_11a 489 490 <legal 0> 491 492 ptr_to_previous_aging_queue_31_0 493 494 Address (address bits 31-0)of next RX_REO_QUEUE 495 descriptor in the 'receive timestamp' ordered list. 496 497 From it the Position of this queue descriptor in the per 498 AC aging waitlist can be derived. 499 500 Value 0x0 indicates the 'NULL' pointer which implies 501 that this is the first entry in the list. 502 503 <legal all> 504 505 ptr_to_previous_aging_queue_39_32 506 507 Address (address bits 39-32)of next RX_REO_QUEUE 508 descriptor in the 'receive timestamp' ordered list. 509 510 From it the Position of this queue descriptor in the per 511 AC aging waitlist can be derived. 512 513 Value 0x0 indicates the 'NULL' pointer which implies 514 that this is the first entry in the list. 515 516 <legal all> 517 518 reserved_13a 519 520 <legal 0> 521 522 rx_bitmap_31_0 523 524 When a bit is set, the corresponding frame is currently 525 held in the re-order queue. 526 527 The bitmap is Fully managed by HW. 528 529 SW shall init this to 0, and then never ever change it 530 531 <legal all> 532 533 rx_bitmap_63_32 534 535 See Rx_bitmap_31_0 description 536 537 <legal all> 538 539 rx_bitmap_95_64 540 541 See Rx_bitmap_31_0 description 542 543 <legal all> 544 545 rx_bitmap_127_96 546 547 See Rx_bitmap_31_0 description 548 549 <legal all> 550 551 rx_bitmap_159_128 552 553 See Rx_bitmap_31_0 description 554 555 <legal all> 556 557 rx_bitmap_191_160 558 559 See Rx_bitmap_31_0 description 560 561 <legal all> 562 563 rx_bitmap_223_192 564 565 See Rx_bitmap_31_0 description 566 567 <legal all> 568 569 rx_bitmap_255_224 570 571 See Rx_bitmap_31_0 description 572 573 <legal all> 574 575 current_mpdu_count 576 577 The number of MPDUs in the queue. 578 579 580 581 <legal all> 582 583 current_msdu_count 584 585 The number of MSDUs in the queue. 586 587 <legal all> 588 589 reserved_23 590 591 <legal 0> 592 593 timeout_count 594 595 The number of times that REO started forwarding frames 596 even though there is a hole in the bitmap. Forwarding reason 597 is Timeout 598 599 600 601 The counter saturates and freezes at 0x3F 602 603 604 605 <legal all> 606 607 forward_due_to_bar_count 608 609 The number of times that REO started forwarding frames 610 even though there is a hole in the bitmap. Forwarding reason 611 is reception of BAR frame. 612 613 614 615 The counter saturates and freezes at 0x3F 616 617 618 619 <legal all> 620 621 duplicate_count 622 623 The number of duplicate frames that have been detected 624 625 <legal all> 626 627 frames_in_order_count 628 629 The number of frames that have been received in order 630 (without a hole that prevented them from being forwarded 631 immediately) 632 633 634 635 This corresponds to the Reorder opcodes: 636 637 'FWDCUR' and 'FWD BUF' 638 639 640 641 <legal all> 642 643 bar_received_count 644 645 The number of times a BAR frame is received. 646 647 648 649 This corresponds to the Reorder opcodes with 'DROP' 650 651 652 653 The counter saturates and freezes at 0xFF 654 655 <legal all> 656 657 mpdu_frames_processed_count 658 659 The total number of MPDU frames that have been processed 660 by REO. 'Processing' here means that REO has received them 661 out of the entrance ring, and retrieved the corresponding 662 RX_REO_QUEUE Descriptor. 663 664 665 666 Note that this count includes duplicates, frames that 667 later had errors, etc. 668 669 670 671 Note that field 'Duplicate_count' indicates how many of 672 these MPDUs were duplicates. 673 674 675 676 <legal all> 677 678 msdu_frames_processed_count 679 680 The total number of MSDU frames that have been processed 681 by REO. 'Processing' here means that REO has received them 682 out of the entrance ring, and retrieved the corresponding 683 RX_REO_QUEUE Descriptor. 684 685 686 687 Note that this count includes duplicates, frames that 688 later had errors, etc. 689 690 691 692 <legal all> 693 694 total_processed_byte_count 695 696 An approximation of the number of bytes processed for 697 this queue. 698 699 'Processing' here means that REO has received them out 700 of the entrance ring, and retrieved the corresponding 701 RX_REO_QUEUE Descriptor. 702 703 704 705 Note that this count includes duplicates, frames that 706 later had errors, etc. 707 708 709 710 In 64 byte units 711 712 <legal all> 713 714 late_receive_mpdu_count 715 716 The number of MPDUs received after the window had 717 already moved on. The 'late' sequence window is defined as 718 (Window SSN - 256) - (Window SSN - 1) 719 720 721 722 This corresponds with Out of order detection in 723 duplicate detect FSM 724 725 726 727 The counter saturates and freezes at 0xFFF 728 729 730 731 <legal all> 732 733 window_jump_2k 734 735 The number of times the window moved more then 2K 736 737 738 739 The counter saturates and freezes at 0xF 740 741 742 743 (Note: field name can not start with number: previous 744 2k_window_jump) 745 746 747 748 <legal all> 749 750 hole_count 751 752 The number of times a hole was created in the receive 753 bitmap. 754 755 756 757 This corresponds to the Reorder opcodes with 'QCUR' 758 759 760 761 <legal all> 762 763 reserved_29 764 765 <legal 0> 766 767 reserved_30 768 769 <legal 0> 770 771 reserved_31 772 773 <legal 0> 774 */ 775 776 777 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 778 779 780 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER 781 782 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 783 784 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 785 786 787 788 The owner of this data structure: 789 790 <enum 0 WBM_owned> Buffer Manager currently owns this 791 data structure. 792 793 <enum 1 SW_OR_FW_owned> Software of FW currently owns 794 this data structure. 795 796 <enum 2 TQM_owned> Transmit Queue Manager currently owns 797 this data structure. 798 799 <enum 3 RXDMA_owned> Receive DMA currently owns this 800 data structure. 801 802 <enum 4 REO_owned> Reorder currently owns this data 803 structure. 804 805 <enum 5 SWITCH_owned> SWITCH currently owns this data 806 structure. 807 808 809 810 <legal 0-5> 811 */ 812 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 813 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0 814 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 815 816 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE 817 818 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 819 820 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 821 822 823 824 Field describing what contents format is of this 825 descriptor 826 827 828 829 <enum 0 Transmit_MSDU_Link_descriptor > 830 831 <enum 1 Transmit_MPDU_Link_descriptor > 832 833 <enum 2 Transmit_MPDU_Queue_head_descriptor> 834 835 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 836 837 <enum 4 Transmit_flow_descriptor> 838 839 <enum 5 Transmit_buffer > NOT TO BE USED: 840 841 842 843 <enum 6 Receive_MSDU_Link_descriptor > 844 845 <enum 7 Receive_MPDU_Link_descriptor > 846 847 <enum 8 Receive_REO_queue_descriptor > 848 849 <enum 9 Receive_REO_queue_ext_descriptor > 850 851 852 853 <enum 10 Receive_buffer > 854 855 856 857 <enum 11 Idle_link_list_entry> 858 859 860 861 <legal 0-11> 862 */ 863 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 864 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 865 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 866 867 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A 868 869 <legal 0> 870 */ 871 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 872 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 873 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 874 875 /* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER 876 877 Indicates the MPDU queue ID to which this MPDU link 878 descriptor belongs 879 880 Used for tracking and debugging 881 882 <legal all> 883 */ 884 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 885 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 886 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 887 888 /* Description RX_REO_QUEUE_1_RESERVED_1B 889 890 <legal 0> 891 */ 892 #define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 893 #define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 894 #define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 895 896 /* Description RX_REO_QUEUE_2_VLD 897 898 Valid bit indicating a session is established and the 899 queue descriptor is valid(Filled by SW) 900 901 <legal all> 902 */ 903 #define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 904 #define RX_REO_QUEUE_2_VLD_LSB 0 905 #define RX_REO_QUEUE_2_VLD_MASK 0x00000001 906 907 /* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 908 909 Indicates which of the 3 link descriptor counters shall 910 be incremented or decremented when link descriptors are 911 added or removed from this flow queue. 912 913 MSDU link descriptors related with MPDUs stored in the 914 re-order buffer shall also be included in this count. 915 916 917 918 <legal 0-2> 919 */ 920 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 921 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 922 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 923 924 /* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION 925 926 When set, do not perform any duplicate detection. 927 928 929 930 <legal all> 931 */ 932 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 933 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 934 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 935 936 /* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE 937 938 When set, REO has been instructed to not perform the 939 actual re-ordering of frames for this queue, but just to 940 insert the reorder opcodes. 941 942 943 944 Note that this implies that REO is also not going to 945 perform any MSDU level operations, and the entire MPDU (and 946 thus pointer to the MSDU link descriptor) will be pushed to 947 a destination ring that SW has programmed in a SW 948 programmable configuration register in REO 949 950 951 952 <legal all> 953 */ 954 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 955 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 956 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 957 958 /* Description RX_REO_QUEUE_2_AC 959 960 Indicates which access category the queue descriptor 961 belongs to(filled by SW) 962 963 <legal all> 964 */ 965 #define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 966 #define RX_REO_QUEUE_2_AC_LSB 5 967 #define RX_REO_QUEUE_2_AC_MASK 0x00000060 968 969 /* Description RX_REO_QUEUE_2_BAR 970 971 Indicates if BAR has been received (mostly used for 972 debug purpose and this is filled by REO) 973 974 <legal all> 975 */ 976 #define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 977 #define RX_REO_QUEUE_2_BAR_LSB 7 978 #define RX_REO_QUEUE_2_BAR_MASK 0x00000080 979 980 /* Description RX_REO_QUEUE_2_RTY 981 982 Retry bit is checked if this bit is set. 983 984 <legal all> 985 */ 986 #define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 987 #define RX_REO_QUEUE_2_RTY_LSB 8 988 #define RX_REO_QUEUE_2_RTY_MASK 0x00000100 989 990 /* Description RX_REO_QUEUE_2_CHK_2K_MODE 991 992 Indicates what type of operation is expected from Reo 993 when the received frame SN falls within the 2K window 994 995 996 997 See REO MLD document for programming details. 998 999 <legal all> 1000 */ 1001 #define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 1002 #define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 1003 #define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 1004 1005 /* Description RX_REO_QUEUE_2_OOR_MODE 1006 1007 Out of Order mode: 1008 1009 Indicates what type of operation is expected when the 1010 received frame falls within the OOR window. 1011 1012 1013 1014 See REO MLD document for programming details. 1015 1016 <legal all> 1017 */ 1018 #define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 1019 #define RX_REO_QUEUE_2_OOR_MODE_LSB 10 1020 #define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 1021 1022 /* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE 1023 1024 Indicates the negotiated (window size + 1). 1025 1026 It can go up to Max of 256bits. 1027 1028 1029 1030 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 1031 (means non-BA session, with window size of 0). The 3 values 1032 here are the main values validated, but other values should 1033 work as well. 1034 1035 1036 1037 A BA window size of 0 (=> one frame entry bitmat), means 1038 that there is NO RX_REO_QUEUE_EXT descriptor following this 1039 RX_REO_QUEUE STRUCT in memory 1040 1041 1042 1043 A BA window size of 1 - 105, means that there is 1 1044 RX_REO_QUEUE_EXT descriptor directly following this 1045 RX_REO_QUEUE STRUCT in memory. 1046 1047 1048 1049 A BA window size of 106 - 210, means that there are 2 1050 RX_REO_QUEUE_EXT descriptors directly following this 1051 RX_REO_QUEUE STRUCT in memory 1052 1053 1054 1055 A BA window size of 211 - 256, means that there are 3 1056 RX_REO_QUEUE_EXT descriptors directly following this 1057 RX_REO_QUEUE STRUCT in memory 1058 1059 1060 1061 <legal 0 - 255> 1062 */ 1063 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 1064 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 1065 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 1066 1067 /* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED 1068 1069 When set, REO shall perform the PN increment check 1070 1071 <legal all> 1072 */ 1073 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 1074 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 1075 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 1076 1077 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN 1078 1079 Field only valid when 'pn_check_needed' is set. 1080 1081 1082 1083 When set, REO shall confirm that the received PN number 1084 is not only incremented, but also always an even number 1085 1086 <legal all> 1087 */ 1088 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 1089 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 1090 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 1091 1092 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN 1093 1094 Field only valid when 'pn_check_needed' is set. 1095 1096 1097 1098 When set, REO shall confirm that the received PN number 1099 is not only incremented, but also always an uneven number 1100 1101 <legal all> 1102 */ 1103 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 1104 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 1105 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 1106 1107 /* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE 1108 1109 Field only valid when 'pn_check_needed' is set. 1110 1111 1112 1113 When set, and REO detected a PN error, HW shall set the 1114 'pn_error_detected_flag'. 1115 1116 <legal all> 1117 */ 1118 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 1119 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 1120 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 1121 1122 /* Description RX_REO_QUEUE_2_PN_SIZE 1123 1124 Size of the PN field check. 1125 1126 Needed for wrap around handling... 1127 1128 1129 1130 <enum 0 pn_size_24> 1131 1132 <enum 1 pn_size_48> 1133 1134 <enum 2 pn_size_128> 1135 1136 1137 1138 <legal 0-2> 1139 */ 1140 #define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 1141 #define RX_REO_QUEUE_2_PN_SIZE_LSB 23 1142 #define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 1143 1144 /* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG 1145 1146 When set, REO shall ignore the ampdu_flag on the 1147 entrance descriptor for this queue. 1148 1149 <legal all> 1150 */ 1151 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 1152 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 1153 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 1154 1155 /* Description RX_REO_QUEUE_2_RESERVED_2B 1156 1157 <legal 0> 1158 */ 1159 #define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 1160 #define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 1161 #define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 1162 1163 /* Description RX_REO_QUEUE_3_SVLD 1164 1165 Sequence number in next field is valid one. It can be 1166 filled by SW if the want to fill in the any negotiated SSN, 1167 otherwise REO will fill the sequence number of first 1168 received packet and set this bit to 1. 1169 1170 <legal all> 1171 */ 1172 #define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c 1173 #define RX_REO_QUEUE_3_SVLD_LSB 0 1174 #define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 1175 1176 /* Description RX_REO_QUEUE_3_SSN 1177 1178 Starting Sequence number of the session, this changes 1179 whenever window moves. (can be filled by SW then maintained 1180 by REO) 1181 1182 <legal all> 1183 */ 1184 #define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c 1185 #define RX_REO_QUEUE_3_SSN_LSB 1 1186 #define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe 1187 1188 /* Description RX_REO_QUEUE_3_CURRENT_INDEX 1189 1190 Points to last forwarded packet 1191 1192 <legal all> 1193 */ 1194 #define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c 1195 #define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 1196 #define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 1197 1198 /* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG 1199 1200 Set by REO, can only be cleared by SW 1201 1202 1203 1204 When set, REO has detected a 2k error jump in the 1205 sequence number and from that moment forward, all new frames 1206 are forwarded directly to FW, without duplicate detect, 1207 reordering, etc. 1208 1209 <legal all> 1210 */ 1211 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1212 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 1213 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 1214 1215 /* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG 1216 1217 Set by REO, can only be cleared by SW 1218 1219 1220 1221 When set, REO has detected a PN error and from that 1222 moment forward, all new frames are forwarded directly to FW, 1223 without duplicate detect, reordering, etc. 1224 1225 <legal all> 1226 */ 1227 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1228 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 1229 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 1230 1231 /* Description RX_REO_QUEUE_3_RESERVED_3A 1232 1233 <legal 0> 1234 */ 1235 #define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 1236 #define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 1237 #define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 1238 1239 /* Description RX_REO_QUEUE_3_PN_VALID 1240 1241 PN number in next fields are valid. It can be filled by 1242 SW if it wants to fill in the any negotiated SSN, otherwise 1243 REO will fill the pn based on the first received packet and 1244 set this bit to 1. 1245 1246 <legal all> 1247 */ 1248 #define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c 1249 #define RX_REO_QUEUE_3_PN_VALID_LSB 31 1250 #define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 1251 1252 /* Description RX_REO_QUEUE_4_PN_31_0 1253 1254 1255 <legal all> 1256 */ 1257 #define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 1258 #define RX_REO_QUEUE_4_PN_31_0_LSB 0 1259 #define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff 1260 1261 /* Description RX_REO_QUEUE_5_PN_63_32 1262 1263 Bits [63:32] of the PN number. 1264 1265 <legal all> 1266 */ 1267 #define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 1268 #define RX_REO_QUEUE_5_PN_63_32_LSB 0 1269 #define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff 1270 1271 /* Description RX_REO_QUEUE_6_PN_95_64 1272 1273 Bits [95:64] of the PN number. 1274 1275 <legal all> 1276 */ 1277 #define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 1278 #define RX_REO_QUEUE_6_PN_95_64_LSB 0 1279 #define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff 1280 1281 /* Description RX_REO_QUEUE_7_PN_127_96 1282 1283 Bits [127:96] of the PN number. 1284 1285 <legal all> 1286 */ 1287 #define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c 1288 #define RX_REO_QUEUE_7_PN_127_96_LSB 0 1289 #define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff 1290 1291 /* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP 1292 1293 This timestamp is updated when an MPDU is received and 1294 accesses this Queue Descriptor. It does not include the 1295 access due to Command TLVs or Aging (which will be updated 1296 in Last_rx_dequeue_timestamp). 1297 1298 <legal all> 1299 */ 1300 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 1301 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 1302 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 1303 1304 /* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP 1305 1306 This timestamp is used for Aging. When an MPDU or 1307 multiple MPDUs are forwarded, either due to window movement, 1308 bar, aging or command flush, this timestamp is updated. Also 1309 when the bitmap is all zero and the first time an MPDU is 1310 queued (opcode=QCUR), this timestamp is updated for aging. 1311 1312 <legal all> 1313 */ 1314 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 1315 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 1316 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 1317 1318 /* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0 1319 1320 Address (address bits 31-0)of next RX_REO_QUEUE 1321 descriptor in the 'receive timestamp' ordered list. 1322 1323 From it the Position of this queue descriptor in the per 1324 AC aging waitlist can be derived. 1325 1326 Value 0x0 indicates the 'NULL' pointer which implies 1327 that this is the last entry in the list. 1328 1329 <legal all> 1330 */ 1331 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 1332 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 1333 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 1334 1335 /* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32 1336 1337 Address (address bits 39-32)of next RX_REO_QUEUE 1338 descriptor in the 'receive timestamp' ordered list. 1339 1340 From it the Position of this queue descriptor in the per 1341 AC aging waitlist can be derived. 1342 1343 Value 0x0 indicates the 'NULL' pointer which implies 1344 that this is the last entry in the list. 1345 1346 <legal all> 1347 */ 1348 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 1349 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 1350 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 1351 1352 /* Description RX_REO_QUEUE_11_RESERVED_11A 1353 1354 <legal 0> 1355 */ 1356 #define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c 1357 #define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 1358 #define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 1359 1360 /* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0 1361 1362 Address (address bits 31-0)of next RX_REO_QUEUE 1363 descriptor in the 'receive timestamp' ordered list. 1364 1365 From it the Position of this queue descriptor in the per 1366 AC aging waitlist can be derived. 1367 1368 Value 0x0 indicates the 'NULL' pointer which implies 1369 that this is the first entry in the list. 1370 1371 <legal all> 1372 */ 1373 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 1374 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 1375 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 1376 1377 /* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32 1378 1379 Address (address bits 39-32)of next RX_REO_QUEUE 1380 descriptor in the 'receive timestamp' ordered list. 1381 1382 From it the Position of this queue descriptor in the per 1383 AC aging waitlist can be derived. 1384 1385 Value 0x0 indicates the 'NULL' pointer which implies 1386 that this is the first entry in the list. 1387 1388 <legal all> 1389 */ 1390 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 1391 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 1392 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 1393 1394 /* Description RX_REO_QUEUE_13_RESERVED_13A 1395 1396 <legal 0> 1397 */ 1398 #define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 1399 #define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 1400 #define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 1401 1402 /* Description RX_REO_QUEUE_14_RX_BITMAP_31_0 1403 1404 When a bit is set, the corresponding frame is currently 1405 held in the re-order queue. 1406 1407 The bitmap is Fully managed by HW. 1408 1409 SW shall init this to 0, and then never ever change it 1410 1411 <legal all> 1412 */ 1413 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 1414 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 1415 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff 1416 1417 /* Description RX_REO_QUEUE_15_RX_BITMAP_63_32 1418 1419 See Rx_bitmap_31_0 description 1420 1421 <legal all> 1422 */ 1423 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c 1424 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 1425 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff 1426 1427 /* Description RX_REO_QUEUE_16_RX_BITMAP_95_64 1428 1429 See Rx_bitmap_31_0 description 1430 1431 <legal all> 1432 */ 1433 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 1434 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 1435 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff 1436 1437 /* Description RX_REO_QUEUE_17_RX_BITMAP_127_96 1438 1439 See Rx_bitmap_31_0 description 1440 1441 <legal all> 1442 */ 1443 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 1444 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 1445 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff 1446 1447 /* Description RX_REO_QUEUE_18_RX_BITMAP_159_128 1448 1449 See Rx_bitmap_31_0 description 1450 1451 <legal all> 1452 */ 1453 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 1454 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 1455 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff 1456 1457 /* Description RX_REO_QUEUE_19_RX_BITMAP_191_160 1458 1459 See Rx_bitmap_31_0 description 1460 1461 <legal all> 1462 */ 1463 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c 1464 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 1465 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff 1466 1467 /* Description RX_REO_QUEUE_20_RX_BITMAP_223_192 1468 1469 See Rx_bitmap_31_0 description 1470 1471 <legal all> 1472 */ 1473 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 1474 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 1475 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff 1476 1477 /* Description RX_REO_QUEUE_21_RX_BITMAP_255_224 1478 1479 See Rx_bitmap_31_0 description 1480 1481 <legal all> 1482 */ 1483 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 1484 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 1485 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff 1486 1487 /* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT 1488 1489 The number of MPDUs in the queue. 1490 1491 1492 1493 <legal all> 1494 */ 1495 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 1496 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 1497 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f 1498 1499 /* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT 1500 1501 The number of MSDUs in the queue. 1502 1503 <legal all> 1504 */ 1505 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 1506 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 1507 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 1508 1509 /* Description RX_REO_QUEUE_23_RESERVED_23 1510 1511 <legal 0> 1512 */ 1513 #define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c 1514 #define RX_REO_QUEUE_23_RESERVED_23_LSB 0 1515 #define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f 1516 1517 /* Description RX_REO_QUEUE_23_TIMEOUT_COUNT 1518 1519 The number of times that REO started forwarding frames 1520 even though there is a hole in the bitmap. Forwarding reason 1521 is Timeout 1522 1523 1524 1525 The counter saturates and freezes at 0x3F 1526 1527 1528 1529 <legal all> 1530 */ 1531 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c 1532 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 1533 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 1534 1535 /* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT 1536 1537 The number of times that REO started forwarding frames 1538 even though there is a hole in the bitmap. Forwarding reason 1539 is reception of BAR frame. 1540 1541 1542 1543 The counter saturates and freezes at 0x3F 1544 1545 1546 1547 <legal all> 1548 */ 1549 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c 1550 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 1551 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 1552 1553 /* Description RX_REO_QUEUE_23_DUPLICATE_COUNT 1554 1555 The number of duplicate frames that have been detected 1556 1557 <legal all> 1558 */ 1559 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c 1560 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 1561 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 1562 1563 /* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT 1564 1565 The number of frames that have been received in order 1566 (without a hole that prevented them from being forwarded 1567 immediately) 1568 1569 1570 1571 This corresponds to the Reorder opcodes: 1572 1573 'FWDCUR' and 'FWD BUF' 1574 1575 1576 1577 <legal all> 1578 */ 1579 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 1580 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 1581 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 1582 1583 /* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT 1584 1585 The number of times a BAR frame is received. 1586 1587 1588 1589 This corresponds to the Reorder opcodes with 'DROP' 1590 1591 1592 1593 The counter saturates and freezes at 0xFF 1594 1595 <legal all> 1596 */ 1597 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 1598 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 1599 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 1600 1601 /* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT 1602 1603 The total number of MPDU frames that have been processed 1604 by REO. 'Processing' here means that REO has received them 1605 out of the entrance ring, and retrieved the corresponding 1606 RX_REO_QUEUE Descriptor. 1607 1608 1609 1610 Note that this count includes duplicates, frames that 1611 later had errors, etc. 1612 1613 1614 1615 Note that field 'Duplicate_count' indicates how many of 1616 these MPDUs were duplicates. 1617 1618 1619 1620 <legal all> 1621 */ 1622 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 1623 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 1624 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1625 1626 /* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT 1627 1628 The total number of MSDU frames that have been processed 1629 by REO. 'Processing' here means that REO has received them 1630 out of the entrance ring, and retrieved the corresponding 1631 RX_REO_QUEUE Descriptor. 1632 1633 1634 1635 Note that this count includes duplicates, frames that 1636 later had errors, etc. 1637 1638 1639 1640 <legal all> 1641 */ 1642 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 1643 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 1644 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1645 1646 /* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT 1647 1648 An approximation of the number of bytes processed for 1649 this queue. 1650 1651 'Processing' here means that REO has received them out 1652 of the entrance ring, and retrieved the corresponding 1653 RX_REO_QUEUE Descriptor. 1654 1655 1656 1657 Note that this count includes duplicates, frames that 1658 later had errors, etc. 1659 1660 1661 1662 In 64 byte units 1663 1664 <legal all> 1665 */ 1666 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c 1667 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 1668 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 1669 1670 /* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT 1671 1672 The number of MPDUs received after the window had 1673 already moved on. The 'late' sequence window is defined as 1674 (Window SSN - 256) - (Window SSN - 1) 1675 1676 1677 1678 This corresponds with Out of order detection in 1679 duplicate detect FSM 1680 1681 1682 1683 The counter saturates and freezes at 0xFFF 1684 1685 1686 1687 <legal all> 1688 */ 1689 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 1690 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 1691 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 1692 1693 /* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K 1694 1695 The number of times the window moved more then 2K 1696 1697 1698 1699 The counter saturates and freezes at 0xF 1700 1701 1702 1703 (Note: field name can not start with number: previous 1704 2k_window_jump) 1705 1706 1707 1708 <legal all> 1709 */ 1710 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 1711 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 1712 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 1713 1714 /* Description RX_REO_QUEUE_28_HOLE_COUNT 1715 1716 The number of times a hole was created in the receive 1717 bitmap. 1718 1719 1720 1721 This corresponds to the Reorder opcodes with 'QCUR' 1722 1723 1724 1725 <legal all> 1726 */ 1727 #define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 1728 #define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 1729 #define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 1730 1731 /* Description RX_REO_QUEUE_29_RESERVED_29 1732 1733 <legal 0> 1734 */ 1735 #define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 1736 #define RX_REO_QUEUE_29_RESERVED_29_LSB 0 1737 #define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff 1738 1739 /* Description RX_REO_QUEUE_30_RESERVED_30 1740 1741 <legal 0> 1742 */ 1743 #define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 1744 #define RX_REO_QUEUE_30_RESERVED_30_LSB 0 1745 #define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff 1746 1747 /* Description RX_REO_QUEUE_31_RESERVED_31 1748 1749 <legal 0> 1750 */ 1751 #define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c 1752 #define RX_REO_QUEUE_31_RESERVED_31_LSB 0 1753 #define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff 1754 1755 1756 #endif // _RX_REO_QUEUE_H_ 1757