1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_REO_QUEUE_EXT_H_ 25 #define _RX_REO_QUEUE_EXT_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_descriptor_header.h" 30 #include "rx_mpdu_link_ptr.h" 31 32 // ################ START SUMMARY ################# 33 // 34 // Dword Fields 35 // 0 struct uniform_descriptor_header descriptor_header; 36 // 1 reserved_1a[31:0] 37 // 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 38 // 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 39 // 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 40 // 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 41 // 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 42 // 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 43 // 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 44 // 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 45 // 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 46 // 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 47 // 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 48 // 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 49 // 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 50 // 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 51 // 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 52 // 53 // ################ END SUMMARY ################# 54 55 #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 56 57 struct rx_reo_queue_ext { 58 struct uniform_descriptor_header descriptor_header; 59 uint32_t reserved_1a : 32; //[31:0] 60 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 61 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 62 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 63 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 64 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 65 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 66 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 67 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 68 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 69 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 70 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 71 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 72 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 73 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 74 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 75 }; 76 77 /* 78 79 struct uniform_descriptor_header descriptor_header 80 81 Details about which module owns this struct. 82 83 Note that sub field Buffer_type shall be set to 84 Receive_REO_queue_ext_descriptor 85 86 reserved_1a 87 88 <legal 0> 89 90 struct rx_mpdu_link_ptr mpdu_link_pointer_0 91 92 Consumer: REO 93 94 Producer: REO 95 96 97 98 Pointer to the next MPDU_link descriptor in the MPDU 99 queue 100 101 struct rx_mpdu_link_ptr mpdu_link_pointer_1 102 103 Consumer: REO 104 105 Producer: REO 106 107 108 109 Pointer to the next MPDU_link descriptor in the MPDU 110 queue 111 112 struct rx_mpdu_link_ptr mpdu_link_pointer_2 113 114 Consumer: REO 115 116 Producer: REO 117 118 119 120 Pointer to the next MPDU_link descriptor in the MPDU 121 queue 122 123 struct rx_mpdu_link_ptr mpdu_link_pointer_3 124 125 Consumer: REO 126 127 Producer: REO 128 129 130 131 Pointer to the next MPDU_link descriptor in the MPDU 132 queue 133 134 struct rx_mpdu_link_ptr mpdu_link_pointer_4 135 136 Consumer: REO 137 138 Producer: REO 139 140 141 142 Pointer to the next MPDU_link descriptor in the MPDU 143 queue 144 145 struct rx_mpdu_link_ptr mpdu_link_pointer_5 146 147 Consumer: REO 148 149 Producer: REO 150 151 152 153 Pointer to the next MPDU_link descriptor in the MPDU 154 queue 155 156 struct rx_mpdu_link_ptr mpdu_link_pointer_6 157 158 Consumer: REO 159 160 Producer: REO 161 162 163 164 Pointer to the next MPDU_link descriptor in the MPDU 165 queue 166 167 struct rx_mpdu_link_ptr mpdu_link_pointer_7 168 169 Consumer: REO 170 171 Producer: REO 172 173 174 175 Pointer to the next MPDU_link descriptor in the MPDU 176 queue 177 178 struct rx_mpdu_link_ptr mpdu_link_pointer_8 179 180 Consumer: REO 181 182 Producer: REO 183 184 185 186 Pointer to the next MPDU_link descriptor in the MPDU 187 queue 188 189 struct rx_mpdu_link_ptr mpdu_link_pointer_9 190 191 Consumer: REO 192 193 Producer: REO 194 195 196 197 Pointer to the next MPDU_link descriptor in the MPDU 198 queue 199 200 struct rx_mpdu_link_ptr mpdu_link_pointer_10 201 202 Consumer: REO 203 204 Producer: REO 205 206 207 208 Pointer to the next MPDU_link descriptor in the MPDU 209 queue 210 211 struct rx_mpdu_link_ptr mpdu_link_pointer_11 212 213 Consumer: REO 214 215 Producer: REO 216 217 218 219 Pointer to the next MPDU_link descriptor in the MPDU 220 queue 221 222 struct rx_mpdu_link_ptr mpdu_link_pointer_12 223 224 Consumer: REO 225 226 Producer: REO 227 228 229 230 Pointer to the next MPDU_link descriptor in the MPDU 231 queue 232 233 struct rx_mpdu_link_ptr mpdu_link_pointer_13 234 235 Consumer: REO 236 237 Producer: REO 238 239 240 241 Pointer to the next MPDU_link descriptor in the MPDU 242 queue 243 244 struct rx_mpdu_link_ptr mpdu_link_pointer_14 245 246 Consumer: REO 247 248 Producer: REO 249 250 251 252 Pointer to the next MPDU_link descriptor in the MPDU 253 queue 254 */ 255 256 257 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 258 259 260 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER 261 262 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 263 264 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 265 266 267 268 The owner of this data structure: 269 270 <enum 0 WBM_owned> Buffer Manager currently owns this 271 data structure. 272 273 <enum 1 SW_OR_FW_owned> Software of FW currently owns 274 this data structure. 275 276 <enum 2 TQM_owned> Transmit Queue Manager currently owns 277 this data structure. 278 279 <enum 3 RXDMA_owned> Receive DMA currently owns this 280 data structure. 281 282 <enum 4 REO_owned> Reorder currently owns this data 283 structure. 284 285 <enum 5 SWITCH_owned> SWITCH currently owns this data 286 structure. 287 288 289 290 <legal 0-5> 291 */ 292 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 293 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0 294 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 295 296 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE 297 298 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 299 300 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 301 302 303 304 Field describing what contents format is of this 305 descriptor 306 307 308 309 <enum 0 Transmit_MSDU_Link_descriptor > 310 311 <enum 1 Transmit_MPDU_Link_descriptor > 312 313 <enum 2 Transmit_MPDU_Queue_head_descriptor> 314 315 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 316 317 <enum 4 Transmit_flow_descriptor> 318 319 <enum 5 Transmit_buffer > NOT TO BE USED: 320 321 322 323 <enum 6 Receive_MSDU_Link_descriptor > 324 325 <enum 7 Receive_MPDU_Link_descriptor > 326 327 <enum 8 Receive_REO_queue_descriptor > 328 329 <enum 9 Receive_REO_queue_ext_descriptor > 330 331 332 333 <enum 10 Receive_buffer > 334 335 336 337 <enum 11 Idle_link_list_entry> 338 339 340 341 <legal 0-11> 342 */ 343 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 344 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 345 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 346 347 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A 348 349 <legal 0> 350 */ 351 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 352 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 353 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 354 355 /* Description RX_REO_QUEUE_EXT_1_RESERVED_1A 356 357 <legal 0> 358 */ 359 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 360 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 361 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff 362 363 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_0 */ 364 365 366 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 367 368 369 /* Description RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 370 371 Address (lower 32 bits) of the MSDU buffer OR 372 MSDU_EXTENSION descriptor OR Link Descriptor 373 374 375 376 In case of 'NULL' pointer, this field is set to 0 377 378 <legal all> 379 */ 380 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 381 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 382 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 383 384 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 385 386 Address (upper 8 bits) of the MSDU buffer OR 387 MSDU_EXTENSION descriptor OR Link Descriptor 388 389 390 391 In case of 'NULL' pointer, this field is set to 0 392 393 <legal all> 394 */ 395 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c 396 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 397 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 398 399 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 400 401 Consumer: WBM 402 403 Producer: SW/FW 404 405 406 407 In case of 'NULL' pointer, this field is set to 0 408 409 410 411 Indicates to which buffer manager the buffer OR 412 MSDU_EXTENSION descriptor OR link descriptor that is being 413 pointed to shall be returned after the frame has been 414 processed. It is used by WBM for routing purposes. 415 416 417 418 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 419 to the WMB buffer idle list 420 421 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 422 returned to the WMB idle link descriptor idle list 423 424 <enum 2 FW_BM> This buffer shall be returned to the FW 425 426 <enum 3 SW0_BM> This buffer shall be returned to the SW, 427 ring 0 428 429 <enum 4 SW1_BM> This buffer shall be returned to the SW, 430 ring 1 431 432 <enum 5 SW2_BM> This buffer shall be returned to the SW, 433 ring 2 434 435 <enum 6 SW3_BM> This buffer shall be returned to the SW, 436 ring 3 437 438 <enum 7 SW4_BM> This buffer shall be returned to the SW, 439 ring 4 440 441 442 443 <legal all> 444 */ 445 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c 446 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 447 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 448 449 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 450 451 Cookie field exclusively used by SW. 452 453 454 455 In case of 'NULL' pointer, this field is set to 0 456 457 458 459 HW ignores the contents, accept that it passes the 460 programmed value on to other descriptors together with the 461 physical address 462 463 464 465 Field can be used by SW to for example associate the 466 buffers physical address with the virtual address 467 468 The bit definitions as used by SW are within SW HLD 469 specification 470 471 472 473 NOTE: 474 475 The three most significant bits can have a special 476 meaning in case this struct is embedded in a TX_MPDU_DETAILS 477 STRUCT, and field transmit_bw_restriction is set 478 479 480 481 In case of NON punctured transmission: 482 483 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 484 485 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 486 487 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 488 489 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 490 491 492 493 In case of punctured transmission: 494 495 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 496 497 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 498 499 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 500 501 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 502 503 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 504 505 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 506 507 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 508 509 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 510 511 512 513 Note: a punctured transmission is indicated by the 514 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 515 TLV 516 517 518 519 <legal all> 520 */ 521 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c 522 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 523 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 524 525 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_1 */ 526 527 528 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 529 530 531 /* Description RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 532 533 Address (lower 32 bits) of the MSDU buffer OR 534 MSDU_EXTENSION descriptor OR Link Descriptor 535 536 537 538 In case of 'NULL' pointer, this field is set to 0 539 540 <legal all> 541 */ 542 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 543 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 544 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 545 546 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 547 548 Address (upper 8 bits) of the MSDU buffer OR 549 MSDU_EXTENSION descriptor OR Link Descriptor 550 551 552 553 In case of 'NULL' pointer, this field is set to 0 554 555 <legal all> 556 */ 557 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 558 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 559 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 560 561 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 562 563 Consumer: WBM 564 565 Producer: SW/FW 566 567 568 569 In case of 'NULL' pointer, this field is set to 0 570 571 572 573 Indicates to which buffer manager the buffer OR 574 MSDU_EXTENSION descriptor OR link descriptor that is being 575 pointed to shall be returned after the frame has been 576 processed. It is used by WBM for routing purposes. 577 578 579 580 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 581 to the WMB buffer idle list 582 583 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 584 returned to the WMB idle link descriptor idle list 585 586 <enum 2 FW_BM> This buffer shall be returned to the FW 587 588 <enum 3 SW0_BM> This buffer shall be returned to the SW, 589 ring 0 590 591 <enum 4 SW1_BM> This buffer shall be returned to the SW, 592 ring 1 593 594 <enum 5 SW2_BM> This buffer shall be returned to the SW, 595 ring 2 596 597 <enum 6 SW3_BM> This buffer shall be returned to the SW, 598 ring 3 599 600 <enum 7 SW4_BM> This buffer shall be returned to the SW, 601 ring 4 602 603 604 605 <legal all> 606 */ 607 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 608 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 609 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 610 611 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 612 613 Cookie field exclusively used by SW. 614 615 616 617 In case of 'NULL' pointer, this field is set to 0 618 619 620 621 HW ignores the contents, accept that it passes the 622 programmed value on to other descriptors together with the 623 physical address 624 625 626 627 Field can be used by SW to for example associate the 628 buffers physical address with the virtual address 629 630 The bit definitions as used by SW are within SW HLD 631 specification 632 633 634 635 NOTE: 636 637 The three most significant bits can have a special 638 meaning in case this struct is embedded in a TX_MPDU_DETAILS 639 STRUCT, and field transmit_bw_restriction is set 640 641 642 643 In case of NON punctured transmission: 644 645 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 646 647 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 648 649 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 650 651 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 652 653 654 655 In case of punctured transmission: 656 657 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 658 659 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 660 661 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 662 663 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 664 665 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 666 667 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 668 669 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 670 671 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 672 673 674 675 Note: a punctured transmission is indicated by the 676 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 677 TLV 678 679 680 681 <legal all> 682 */ 683 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 684 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 685 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 686 687 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_2 */ 688 689 690 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 691 692 693 /* Description RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 694 695 Address (lower 32 bits) of the MSDU buffer OR 696 MSDU_EXTENSION descriptor OR Link Descriptor 697 698 699 700 In case of 'NULL' pointer, this field is set to 0 701 702 <legal all> 703 */ 704 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 705 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 706 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 707 708 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 709 710 Address (upper 8 bits) of the MSDU buffer OR 711 MSDU_EXTENSION descriptor OR Link Descriptor 712 713 714 715 In case of 'NULL' pointer, this field is set to 0 716 717 <legal all> 718 */ 719 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c 720 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 721 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 722 723 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 724 725 Consumer: WBM 726 727 Producer: SW/FW 728 729 730 731 In case of 'NULL' pointer, this field is set to 0 732 733 734 735 Indicates to which buffer manager the buffer OR 736 MSDU_EXTENSION descriptor OR link descriptor that is being 737 pointed to shall be returned after the frame has been 738 processed. It is used by WBM for routing purposes. 739 740 741 742 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 743 to the WMB buffer idle list 744 745 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 746 returned to the WMB idle link descriptor idle list 747 748 <enum 2 FW_BM> This buffer shall be returned to the FW 749 750 <enum 3 SW0_BM> This buffer shall be returned to the SW, 751 ring 0 752 753 <enum 4 SW1_BM> This buffer shall be returned to the SW, 754 ring 1 755 756 <enum 5 SW2_BM> This buffer shall be returned to the SW, 757 ring 2 758 759 <enum 6 SW3_BM> This buffer shall be returned to the SW, 760 ring 3 761 762 <enum 7 SW4_BM> This buffer shall be returned to the SW, 763 ring 4 764 765 766 767 <legal all> 768 */ 769 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c 770 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 771 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 772 773 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 774 775 Cookie field exclusively used by SW. 776 777 778 779 In case of 'NULL' pointer, this field is set to 0 780 781 782 783 HW ignores the contents, accept that it passes the 784 programmed value on to other descriptors together with the 785 physical address 786 787 788 789 Field can be used by SW to for example associate the 790 buffers physical address with the virtual address 791 792 The bit definitions as used by SW are within SW HLD 793 specification 794 795 796 797 NOTE: 798 799 The three most significant bits can have a special 800 meaning in case this struct is embedded in a TX_MPDU_DETAILS 801 STRUCT, and field transmit_bw_restriction is set 802 803 804 805 In case of NON punctured transmission: 806 807 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 808 809 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 810 811 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 812 813 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 814 815 816 817 In case of punctured transmission: 818 819 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 820 821 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 822 823 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 824 825 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 826 827 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 828 829 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 830 831 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 832 833 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 834 835 836 837 Note: a punctured transmission is indicated by the 838 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 839 TLV 840 841 842 843 <legal all> 844 */ 845 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c 846 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 847 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 848 849 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_3 */ 850 851 852 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 853 854 855 /* Description RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 856 857 Address (lower 32 bits) of the MSDU buffer OR 858 MSDU_EXTENSION descriptor OR Link Descriptor 859 860 861 862 In case of 'NULL' pointer, this field is set to 0 863 864 <legal all> 865 */ 866 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 867 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 868 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 869 870 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 871 872 Address (upper 8 bits) of the MSDU buffer OR 873 MSDU_EXTENSION descriptor OR Link Descriptor 874 875 876 877 In case of 'NULL' pointer, this field is set to 0 878 879 <legal all> 880 */ 881 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 882 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 883 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 884 885 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 886 887 Consumer: WBM 888 889 Producer: SW/FW 890 891 892 893 In case of 'NULL' pointer, this field is set to 0 894 895 896 897 Indicates to which buffer manager the buffer OR 898 MSDU_EXTENSION descriptor OR link descriptor that is being 899 pointed to shall be returned after the frame has been 900 processed. It is used by WBM for routing purposes. 901 902 903 904 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 905 to the WMB buffer idle list 906 907 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 908 returned to the WMB idle link descriptor idle list 909 910 <enum 2 FW_BM> This buffer shall be returned to the FW 911 912 <enum 3 SW0_BM> This buffer shall be returned to the SW, 913 ring 0 914 915 <enum 4 SW1_BM> This buffer shall be returned to the SW, 916 ring 1 917 918 <enum 5 SW2_BM> This buffer shall be returned to the SW, 919 ring 2 920 921 <enum 6 SW3_BM> This buffer shall be returned to the SW, 922 ring 3 923 924 <enum 7 SW4_BM> This buffer shall be returned to the SW, 925 ring 4 926 927 928 929 <legal all> 930 */ 931 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 932 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 933 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 934 935 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 936 937 Cookie field exclusively used by SW. 938 939 940 941 In case of 'NULL' pointer, this field is set to 0 942 943 944 945 HW ignores the contents, accept that it passes the 946 programmed value on to other descriptors together with the 947 physical address 948 949 950 951 Field can be used by SW to for example associate the 952 buffers physical address with the virtual address 953 954 The bit definitions as used by SW are within SW HLD 955 specification 956 957 958 959 NOTE: 960 961 The three most significant bits can have a special 962 meaning in case this struct is embedded in a TX_MPDU_DETAILS 963 STRUCT, and field transmit_bw_restriction is set 964 965 966 967 In case of NON punctured transmission: 968 969 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 970 971 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 972 973 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 974 975 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 976 977 978 979 In case of punctured transmission: 980 981 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 982 983 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 984 985 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 986 987 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 988 989 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 990 991 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 992 993 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 994 995 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 996 997 998 999 Note: a punctured transmission is indicated by the 1000 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1001 TLV 1002 1003 1004 1005 <legal all> 1006 */ 1007 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 1008 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1009 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1010 1011 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_4 */ 1012 1013 1014 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1015 1016 1017 /* Description RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1018 1019 Address (lower 32 bits) of the MSDU buffer OR 1020 MSDU_EXTENSION descriptor OR Link Descriptor 1021 1022 1023 1024 In case of 'NULL' pointer, this field is set to 0 1025 1026 <legal all> 1027 */ 1028 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 1029 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1030 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1031 1032 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1033 1034 Address (upper 8 bits) of the MSDU buffer OR 1035 MSDU_EXTENSION descriptor OR Link Descriptor 1036 1037 1038 1039 In case of 'NULL' pointer, this field is set to 0 1040 1041 <legal all> 1042 */ 1043 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c 1044 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1045 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1046 1047 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1048 1049 Consumer: WBM 1050 1051 Producer: SW/FW 1052 1053 1054 1055 In case of 'NULL' pointer, this field is set to 0 1056 1057 1058 1059 Indicates to which buffer manager the buffer OR 1060 MSDU_EXTENSION descriptor OR link descriptor that is being 1061 pointed to shall be returned after the frame has been 1062 processed. It is used by WBM for routing purposes. 1063 1064 1065 1066 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1067 to the WMB buffer idle list 1068 1069 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1070 returned to the WMB idle link descriptor idle list 1071 1072 <enum 2 FW_BM> This buffer shall be returned to the FW 1073 1074 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1075 ring 0 1076 1077 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1078 ring 1 1079 1080 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1081 ring 2 1082 1083 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1084 ring 3 1085 1086 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1087 ring 4 1088 1089 1090 1091 <legal all> 1092 */ 1093 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c 1094 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1095 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1096 1097 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1098 1099 Cookie field exclusively used by SW. 1100 1101 1102 1103 In case of 'NULL' pointer, this field is set to 0 1104 1105 1106 1107 HW ignores the contents, accept that it passes the 1108 programmed value on to other descriptors together with the 1109 physical address 1110 1111 1112 1113 Field can be used by SW to for example associate the 1114 buffers physical address with the virtual address 1115 1116 The bit definitions as used by SW are within SW HLD 1117 specification 1118 1119 1120 1121 NOTE: 1122 1123 The three most significant bits can have a special 1124 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1125 STRUCT, and field transmit_bw_restriction is set 1126 1127 1128 1129 In case of NON punctured transmission: 1130 1131 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1132 1133 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1134 1135 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1136 1137 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1138 1139 1140 1141 In case of punctured transmission: 1142 1143 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1144 1145 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1146 1147 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1148 1149 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1150 1151 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1152 1153 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1154 1155 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1156 1157 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1158 1159 1160 1161 Note: a punctured transmission is indicated by the 1162 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1163 TLV 1164 1165 1166 1167 <legal all> 1168 */ 1169 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c 1170 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1171 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1172 1173 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_5 */ 1174 1175 1176 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1177 1178 1179 /* Description RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1180 1181 Address (lower 32 bits) of the MSDU buffer OR 1182 MSDU_EXTENSION descriptor OR Link Descriptor 1183 1184 1185 1186 In case of 'NULL' pointer, this field is set to 0 1187 1188 <legal all> 1189 */ 1190 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 1191 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1192 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1193 1194 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1195 1196 Address (upper 8 bits) of the MSDU buffer OR 1197 MSDU_EXTENSION descriptor OR Link Descriptor 1198 1199 1200 1201 In case of 'NULL' pointer, this field is set to 0 1202 1203 <legal all> 1204 */ 1205 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 1206 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1207 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1208 1209 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1210 1211 Consumer: WBM 1212 1213 Producer: SW/FW 1214 1215 1216 1217 In case of 'NULL' pointer, this field is set to 0 1218 1219 1220 1221 Indicates to which buffer manager the buffer OR 1222 MSDU_EXTENSION descriptor OR link descriptor that is being 1223 pointed to shall be returned after the frame has been 1224 processed. It is used by WBM for routing purposes. 1225 1226 1227 1228 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1229 to the WMB buffer idle list 1230 1231 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1232 returned to the WMB idle link descriptor idle list 1233 1234 <enum 2 FW_BM> This buffer shall be returned to the FW 1235 1236 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1237 ring 0 1238 1239 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1240 ring 1 1241 1242 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1243 ring 2 1244 1245 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1246 ring 3 1247 1248 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1249 ring 4 1250 1251 1252 1253 <legal all> 1254 */ 1255 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1256 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1257 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1258 1259 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1260 1261 Cookie field exclusively used by SW. 1262 1263 1264 1265 In case of 'NULL' pointer, this field is set to 0 1266 1267 1268 1269 HW ignores the contents, accept that it passes the 1270 programmed value on to other descriptors together with the 1271 physical address 1272 1273 1274 1275 Field can be used by SW to for example associate the 1276 buffers physical address with the virtual address 1277 1278 The bit definitions as used by SW are within SW HLD 1279 specification 1280 1281 1282 1283 NOTE: 1284 1285 The three most significant bits can have a special 1286 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1287 STRUCT, and field transmit_bw_restriction is set 1288 1289 1290 1291 In case of NON punctured transmission: 1292 1293 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1294 1295 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1296 1297 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1298 1299 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1300 1301 1302 1303 In case of punctured transmission: 1304 1305 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1306 1307 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1308 1309 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1310 1311 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1312 1313 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1314 1315 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1316 1317 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1318 1319 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1320 1321 1322 1323 Note: a punctured transmission is indicated by the 1324 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1325 TLV 1326 1327 1328 1329 <legal all> 1330 */ 1331 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 1332 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1333 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1334 1335 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_6 */ 1336 1337 1338 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1339 1340 1341 /* Description RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1342 1343 Address (lower 32 bits) of the MSDU buffer OR 1344 MSDU_EXTENSION descriptor OR Link Descriptor 1345 1346 1347 1348 In case of 'NULL' pointer, this field is set to 0 1349 1350 <legal all> 1351 */ 1352 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 1353 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1354 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1355 1356 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1357 1358 Address (upper 8 bits) of the MSDU buffer OR 1359 MSDU_EXTENSION descriptor OR Link Descriptor 1360 1361 1362 1363 In case of 'NULL' pointer, this field is set to 0 1364 1365 <legal all> 1366 */ 1367 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c 1368 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1369 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1370 1371 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1372 1373 Consumer: WBM 1374 1375 Producer: SW/FW 1376 1377 1378 1379 In case of 'NULL' pointer, this field is set to 0 1380 1381 1382 1383 Indicates to which buffer manager the buffer OR 1384 MSDU_EXTENSION descriptor OR link descriptor that is being 1385 pointed to shall be returned after the frame has been 1386 processed. It is used by WBM for routing purposes. 1387 1388 1389 1390 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1391 to the WMB buffer idle list 1392 1393 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1394 returned to the WMB idle link descriptor idle list 1395 1396 <enum 2 FW_BM> This buffer shall be returned to the FW 1397 1398 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1399 ring 0 1400 1401 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1402 ring 1 1403 1404 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1405 ring 2 1406 1407 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1408 ring 3 1409 1410 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1411 ring 4 1412 1413 1414 1415 <legal all> 1416 */ 1417 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c 1418 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1419 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1420 1421 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1422 1423 Cookie field exclusively used by SW. 1424 1425 1426 1427 In case of 'NULL' pointer, this field is set to 0 1428 1429 1430 1431 HW ignores the contents, accept that it passes the 1432 programmed value on to other descriptors together with the 1433 physical address 1434 1435 1436 1437 Field can be used by SW to for example associate the 1438 buffers physical address with the virtual address 1439 1440 The bit definitions as used by SW are within SW HLD 1441 specification 1442 1443 1444 1445 NOTE: 1446 1447 The three most significant bits can have a special 1448 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1449 STRUCT, and field transmit_bw_restriction is set 1450 1451 1452 1453 In case of NON punctured transmission: 1454 1455 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1456 1457 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1458 1459 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1460 1461 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1462 1463 1464 1465 In case of punctured transmission: 1466 1467 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1468 1469 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1470 1471 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1472 1473 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1474 1475 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1476 1477 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1478 1479 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1480 1481 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1482 1483 1484 1485 Note: a punctured transmission is indicated by the 1486 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1487 TLV 1488 1489 1490 1491 <legal all> 1492 */ 1493 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c 1494 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1495 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1496 1497 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_7 */ 1498 1499 1500 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1501 1502 1503 /* Description RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1504 1505 Address (lower 32 bits) of the MSDU buffer OR 1506 MSDU_EXTENSION descriptor OR Link Descriptor 1507 1508 1509 1510 In case of 'NULL' pointer, this field is set to 0 1511 1512 <legal all> 1513 */ 1514 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 1515 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1516 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1517 1518 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1519 1520 Address (upper 8 bits) of the MSDU buffer OR 1521 MSDU_EXTENSION descriptor OR Link Descriptor 1522 1523 1524 1525 In case of 'NULL' pointer, this field is set to 0 1526 1527 <legal all> 1528 */ 1529 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 1530 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1531 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1532 1533 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1534 1535 Consumer: WBM 1536 1537 Producer: SW/FW 1538 1539 1540 1541 In case of 'NULL' pointer, this field is set to 0 1542 1543 1544 1545 Indicates to which buffer manager the buffer OR 1546 MSDU_EXTENSION descriptor OR link descriptor that is being 1547 pointed to shall be returned after the frame has been 1548 processed. It is used by WBM for routing purposes. 1549 1550 1551 1552 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1553 to the WMB buffer idle list 1554 1555 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1556 returned to the WMB idle link descriptor idle list 1557 1558 <enum 2 FW_BM> This buffer shall be returned to the FW 1559 1560 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1561 ring 0 1562 1563 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1564 ring 1 1565 1566 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1567 ring 2 1568 1569 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1570 ring 3 1571 1572 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1573 ring 4 1574 1575 1576 1577 <legal all> 1578 */ 1579 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1580 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1581 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1582 1583 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1584 1585 Cookie field exclusively used by SW. 1586 1587 1588 1589 In case of 'NULL' pointer, this field is set to 0 1590 1591 1592 1593 HW ignores the contents, accept that it passes the 1594 programmed value on to other descriptors together with the 1595 physical address 1596 1597 1598 1599 Field can be used by SW to for example associate the 1600 buffers physical address with the virtual address 1601 1602 The bit definitions as used by SW are within SW HLD 1603 specification 1604 1605 1606 1607 NOTE: 1608 1609 The three most significant bits can have a special 1610 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1611 STRUCT, and field transmit_bw_restriction is set 1612 1613 1614 1615 In case of NON punctured transmission: 1616 1617 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1618 1619 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1620 1621 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1622 1623 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1624 1625 1626 1627 In case of punctured transmission: 1628 1629 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1630 1631 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1632 1633 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1634 1635 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1636 1637 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1638 1639 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1640 1641 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1642 1643 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1644 1645 1646 1647 Note: a punctured transmission is indicated by the 1648 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1649 TLV 1650 1651 1652 1653 <legal all> 1654 */ 1655 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 1656 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1657 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1658 1659 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_8 */ 1660 1661 1662 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1663 1664 1665 /* Description RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1666 1667 Address (lower 32 bits) of the MSDU buffer OR 1668 MSDU_EXTENSION descriptor OR Link Descriptor 1669 1670 1671 1672 In case of 'NULL' pointer, this field is set to 0 1673 1674 <legal all> 1675 */ 1676 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 1677 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1678 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1679 1680 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1681 1682 Address (upper 8 bits) of the MSDU buffer OR 1683 MSDU_EXTENSION descriptor OR Link Descriptor 1684 1685 1686 1687 In case of 'NULL' pointer, this field is set to 0 1688 1689 <legal all> 1690 */ 1691 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c 1692 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1693 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1694 1695 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1696 1697 Consumer: WBM 1698 1699 Producer: SW/FW 1700 1701 1702 1703 In case of 'NULL' pointer, this field is set to 0 1704 1705 1706 1707 Indicates to which buffer manager the buffer OR 1708 MSDU_EXTENSION descriptor OR link descriptor that is being 1709 pointed to shall be returned after the frame has been 1710 processed. It is used by WBM for routing purposes. 1711 1712 1713 1714 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1715 to the WMB buffer idle list 1716 1717 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1718 returned to the WMB idle link descriptor idle list 1719 1720 <enum 2 FW_BM> This buffer shall be returned to the FW 1721 1722 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1723 ring 0 1724 1725 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1726 ring 1 1727 1728 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1729 ring 2 1730 1731 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1732 ring 3 1733 1734 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1735 ring 4 1736 1737 1738 1739 <legal all> 1740 */ 1741 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c 1742 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1743 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1744 1745 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1746 1747 Cookie field exclusively used by SW. 1748 1749 1750 1751 In case of 'NULL' pointer, this field is set to 0 1752 1753 1754 1755 HW ignores the contents, accept that it passes the 1756 programmed value on to other descriptors together with the 1757 physical address 1758 1759 1760 1761 Field can be used by SW to for example associate the 1762 buffers physical address with the virtual address 1763 1764 The bit definitions as used by SW are within SW HLD 1765 specification 1766 1767 1768 1769 NOTE: 1770 1771 The three most significant bits can have a special 1772 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1773 STRUCT, and field transmit_bw_restriction is set 1774 1775 1776 1777 In case of NON punctured transmission: 1778 1779 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1780 1781 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1782 1783 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1784 1785 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1786 1787 1788 1789 In case of punctured transmission: 1790 1791 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1792 1793 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1794 1795 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1796 1797 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1798 1799 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1800 1801 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1802 1803 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1804 1805 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1806 1807 1808 1809 Note: a punctured transmission is indicated by the 1810 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1811 TLV 1812 1813 1814 1815 <legal all> 1816 */ 1817 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c 1818 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1819 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1820 1821 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_9 */ 1822 1823 1824 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1825 1826 1827 /* Description RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1828 1829 Address (lower 32 bits) of the MSDU buffer OR 1830 MSDU_EXTENSION descriptor OR Link Descriptor 1831 1832 1833 1834 In case of 'NULL' pointer, this field is set to 0 1835 1836 <legal all> 1837 */ 1838 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 1839 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1840 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1841 1842 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1843 1844 Address (upper 8 bits) of the MSDU buffer OR 1845 MSDU_EXTENSION descriptor OR Link Descriptor 1846 1847 1848 1849 In case of 'NULL' pointer, this field is set to 0 1850 1851 <legal all> 1852 */ 1853 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 1854 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1855 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1856 1857 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1858 1859 Consumer: WBM 1860 1861 Producer: SW/FW 1862 1863 1864 1865 In case of 'NULL' pointer, this field is set to 0 1866 1867 1868 1869 Indicates to which buffer manager the buffer OR 1870 MSDU_EXTENSION descriptor OR link descriptor that is being 1871 pointed to shall be returned after the frame has been 1872 processed. It is used by WBM for routing purposes. 1873 1874 1875 1876 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1877 to the WMB buffer idle list 1878 1879 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1880 returned to the WMB idle link descriptor idle list 1881 1882 <enum 2 FW_BM> This buffer shall be returned to the FW 1883 1884 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1885 ring 0 1886 1887 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1888 ring 1 1889 1890 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1891 ring 2 1892 1893 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1894 ring 3 1895 1896 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1897 ring 4 1898 1899 1900 1901 <legal all> 1902 */ 1903 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 1904 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1905 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1906 1907 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1908 1909 Cookie field exclusively used by SW. 1910 1911 1912 1913 In case of 'NULL' pointer, this field is set to 0 1914 1915 1916 1917 HW ignores the contents, accept that it passes the 1918 programmed value on to other descriptors together with the 1919 physical address 1920 1921 1922 1923 Field can be used by SW to for example associate the 1924 buffers physical address with the virtual address 1925 1926 The bit definitions as used by SW are within SW HLD 1927 specification 1928 1929 1930 1931 NOTE: 1932 1933 The three most significant bits can have a special 1934 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1935 STRUCT, and field transmit_bw_restriction is set 1936 1937 1938 1939 In case of NON punctured transmission: 1940 1941 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1942 1943 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1944 1945 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1946 1947 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1948 1949 1950 1951 In case of punctured transmission: 1952 1953 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1954 1955 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1956 1957 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1958 1959 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1960 1961 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1962 1963 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1964 1965 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1966 1967 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1968 1969 1970 1971 Note: a punctured transmission is indicated by the 1972 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1973 TLV 1974 1975 1976 1977 <legal all> 1978 */ 1979 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 1980 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1981 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1982 1983 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_10 */ 1984 1985 1986 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1987 1988 1989 /* Description RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1990 1991 Address (lower 32 bits) of the MSDU buffer OR 1992 MSDU_EXTENSION descriptor OR Link Descriptor 1993 1994 1995 1996 In case of 'NULL' pointer, this field is set to 0 1997 1998 <legal all> 1999 */ 2000 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 2001 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2002 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2003 2004 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2005 2006 Address (upper 8 bits) of the MSDU buffer OR 2007 MSDU_EXTENSION descriptor OR Link Descriptor 2008 2009 2010 2011 In case of 'NULL' pointer, this field is set to 0 2012 2013 <legal all> 2014 */ 2015 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c 2016 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2017 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2018 2019 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2020 2021 Consumer: WBM 2022 2023 Producer: SW/FW 2024 2025 2026 2027 In case of 'NULL' pointer, this field is set to 0 2028 2029 2030 2031 Indicates to which buffer manager the buffer OR 2032 MSDU_EXTENSION descriptor OR link descriptor that is being 2033 pointed to shall be returned after the frame has been 2034 processed. It is used by WBM for routing purposes. 2035 2036 2037 2038 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2039 to the WMB buffer idle list 2040 2041 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2042 returned to the WMB idle link descriptor idle list 2043 2044 <enum 2 FW_BM> This buffer shall be returned to the FW 2045 2046 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2047 ring 0 2048 2049 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2050 ring 1 2051 2052 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2053 ring 2 2054 2055 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2056 ring 3 2057 2058 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2059 ring 4 2060 2061 2062 2063 <legal all> 2064 */ 2065 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c 2066 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2067 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2068 2069 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2070 2071 Cookie field exclusively used by SW. 2072 2073 2074 2075 In case of 'NULL' pointer, this field is set to 0 2076 2077 2078 2079 HW ignores the contents, accept that it passes the 2080 programmed value on to other descriptors together with the 2081 physical address 2082 2083 2084 2085 Field can be used by SW to for example associate the 2086 buffers physical address with the virtual address 2087 2088 The bit definitions as used by SW are within SW HLD 2089 specification 2090 2091 2092 2093 NOTE: 2094 2095 The three most significant bits can have a special 2096 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2097 STRUCT, and field transmit_bw_restriction is set 2098 2099 2100 2101 In case of NON punctured transmission: 2102 2103 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2104 2105 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2106 2107 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2108 2109 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2110 2111 2112 2113 In case of punctured transmission: 2114 2115 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2116 2117 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2118 2119 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2120 2121 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2122 2123 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2124 2125 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2126 2127 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2128 2129 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2130 2131 2132 2133 Note: a punctured transmission is indicated by the 2134 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2135 TLV 2136 2137 2138 2139 <legal all> 2140 */ 2141 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c 2142 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2143 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2144 2145 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_11 */ 2146 2147 2148 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2149 2150 2151 /* Description RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2152 2153 Address (lower 32 bits) of the MSDU buffer OR 2154 MSDU_EXTENSION descriptor OR Link Descriptor 2155 2156 2157 2158 In case of 'NULL' pointer, this field is set to 0 2159 2160 <legal all> 2161 */ 2162 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 2163 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2164 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2165 2166 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2167 2168 Address (upper 8 bits) of the MSDU buffer OR 2169 MSDU_EXTENSION descriptor OR Link Descriptor 2170 2171 2172 2173 In case of 'NULL' pointer, this field is set to 0 2174 2175 <legal all> 2176 */ 2177 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 2178 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2179 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2180 2181 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2182 2183 Consumer: WBM 2184 2185 Producer: SW/FW 2186 2187 2188 2189 In case of 'NULL' pointer, this field is set to 0 2190 2191 2192 2193 Indicates to which buffer manager the buffer OR 2194 MSDU_EXTENSION descriptor OR link descriptor that is being 2195 pointed to shall be returned after the frame has been 2196 processed. It is used by WBM for routing purposes. 2197 2198 2199 2200 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2201 to the WMB buffer idle list 2202 2203 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2204 returned to the WMB idle link descriptor idle list 2205 2206 <enum 2 FW_BM> This buffer shall be returned to the FW 2207 2208 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2209 ring 0 2210 2211 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2212 ring 1 2213 2214 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2215 ring 2 2216 2217 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2218 ring 3 2219 2220 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2221 ring 4 2222 2223 2224 2225 <legal all> 2226 */ 2227 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2228 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2229 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2230 2231 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2232 2233 Cookie field exclusively used by SW. 2234 2235 2236 2237 In case of 'NULL' pointer, this field is set to 0 2238 2239 2240 2241 HW ignores the contents, accept that it passes the 2242 programmed value on to other descriptors together with the 2243 physical address 2244 2245 2246 2247 Field can be used by SW to for example associate the 2248 buffers physical address with the virtual address 2249 2250 The bit definitions as used by SW are within SW HLD 2251 specification 2252 2253 2254 2255 NOTE: 2256 2257 The three most significant bits can have a special 2258 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2259 STRUCT, and field transmit_bw_restriction is set 2260 2261 2262 2263 In case of NON punctured transmission: 2264 2265 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2266 2267 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2268 2269 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2270 2271 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2272 2273 2274 2275 In case of punctured transmission: 2276 2277 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2278 2279 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2280 2281 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2282 2283 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2284 2285 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2286 2287 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2288 2289 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2290 2291 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2292 2293 2294 2295 Note: a punctured transmission is indicated by the 2296 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2297 TLV 2298 2299 2300 2301 <legal all> 2302 */ 2303 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 2304 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2305 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2306 2307 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_12 */ 2308 2309 2310 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2311 2312 2313 /* Description RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2314 2315 Address (lower 32 bits) of the MSDU buffer OR 2316 MSDU_EXTENSION descriptor OR Link Descriptor 2317 2318 2319 2320 In case of 'NULL' pointer, this field is set to 0 2321 2322 <legal all> 2323 */ 2324 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 2325 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2326 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2327 2328 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2329 2330 Address (upper 8 bits) of the MSDU buffer OR 2331 MSDU_EXTENSION descriptor OR Link Descriptor 2332 2333 2334 2335 In case of 'NULL' pointer, this field is set to 0 2336 2337 <legal all> 2338 */ 2339 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c 2340 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2341 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2342 2343 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2344 2345 Consumer: WBM 2346 2347 Producer: SW/FW 2348 2349 2350 2351 In case of 'NULL' pointer, this field is set to 0 2352 2353 2354 2355 Indicates to which buffer manager the buffer OR 2356 MSDU_EXTENSION descriptor OR link descriptor that is being 2357 pointed to shall be returned after the frame has been 2358 processed. It is used by WBM for routing purposes. 2359 2360 2361 2362 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2363 to the WMB buffer idle list 2364 2365 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2366 returned to the WMB idle link descriptor idle list 2367 2368 <enum 2 FW_BM> This buffer shall be returned to the FW 2369 2370 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2371 ring 0 2372 2373 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2374 ring 1 2375 2376 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2377 ring 2 2378 2379 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2380 ring 3 2381 2382 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2383 ring 4 2384 2385 2386 2387 <legal all> 2388 */ 2389 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c 2390 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2391 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2392 2393 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2394 2395 Cookie field exclusively used by SW. 2396 2397 2398 2399 In case of 'NULL' pointer, this field is set to 0 2400 2401 2402 2403 HW ignores the contents, accept that it passes the 2404 programmed value on to other descriptors together with the 2405 physical address 2406 2407 2408 2409 Field can be used by SW to for example associate the 2410 buffers physical address with the virtual address 2411 2412 The bit definitions as used by SW are within SW HLD 2413 specification 2414 2415 2416 2417 NOTE: 2418 2419 The three most significant bits can have a special 2420 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2421 STRUCT, and field transmit_bw_restriction is set 2422 2423 2424 2425 In case of NON punctured transmission: 2426 2427 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2428 2429 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2430 2431 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2432 2433 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2434 2435 2436 2437 In case of punctured transmission: 2438 2439 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2440 2441 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2442 2443 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2444 2445 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2446 2447 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2448 2449 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2450 2451 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2452 2453 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2454 2455 2456 2457 Note: a punctured transmission is indicated by the 2458 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2459 TLV 2460 2461 2462 2463 <legal all> 2464 */ 2465 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c 2466 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2467 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2468 2469 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_13 */ 2470 2471 2472 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2473 2474 2475 /* Description RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2476 2477 Address (lower 32 bits) of the MSDU buffer OR 2478 MSDU_EXTENSION descriptor OR Link Descriptor 2479 2480 2481 2482 In case of 'NULL' pointer, this field is set to 0 2483 2484 <legal all> 2485 */ 2486 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 2487 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2488 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2489 2490 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2491 2492 Address (upper 8 bits) of the MSDU buffer OR 2493 MSDU_EXTENSION descriptor OR Link Descriptor 2494 2495 2496 2497 In case of 'NULL' pointer, this field is set to 0 2498 2499 <legal all> 2500 */ 2501 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 2502 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2503 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2504 2505 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2506 2507 Consumer: WBM 2508 2509 Producer: SW/FW 2510 2511 2512 2513 In case of 'NULL' pointer, this field is set to 0 2514 2515 2516 2517 Indicates to which buffer manager the buffer OR 2518 MSDU_EXTENSION descriptor OR link descriptor that is being 2519 pointed to shall be returned after the frame has been 2520 processed. It is used by WBM for routing purposes. 2521 2522 2523 2524 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2525 to the WMB buffer idle list 2526 2527 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2528 returned to the WMB idle link descriptor idle list 2529 2530 <enum 2 FW_BM> This buffer shall be returned to the FW 2531 2532 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2533 ring 0 2534 2535 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2536 ring 1 2537 2538 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2539 ring 2 2540 2541 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2542 ring 3 2543 2544 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2545 ring 4 2546 2547 2548 2549 <legal all> 2550 */ 2551 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2552 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2553 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2554 2555 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2556 2557 Cookie field exclusively used by SW. 2558 2559 2560 2561 In case of 'NULL' pointer, this field is set to 0 2562 2563 2564 2565 HW ignores the contents, accept that it passes the 2566 programmed value on to other descriptors together with the 2567 physical address 2568 2569 2570 2571 Field can be used by SW to for example associate the 2572 buffers physical address with the virtual address 2573 2574 The bit definitions as used by SW are within SW HLD 2575 specification 2576 2577 2578 2579 NOTE: 2580 2581 The three most significant bits can have a special 2582 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2583 STRUCT, and field transmit_bw_restriction is set 2584 2585 2586 2587 In case of NON punctured transmission: 2588 2589 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2590 2591 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2592 2593 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2594 2595 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2596 2597 2598 2599 In case of punctured transmission: 2600 2601 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2602 2603 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2604 2605 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2606 2607 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2608 2609 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2610 2611 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2612 2613 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2614 2615 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2616 2617 2618 2619 Note: a punctured transmission is indicated by the 2620 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2621 TLV 2622 2623 2624 2625 <legal all> 2626 */ 2627 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 2628 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2629 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2630 2631 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_14 */ 2632 2633 2634 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2635 2636 2637 /* Description RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2638 2639 Address (lower 32 bits) of the MSDU buffer OR 2640 MSDU_EXTENSION descriptor OR Link Descriptor 2641 2642 2643 2644 In case of 'NULL' pointer, this field is set to 0 2645 2646 <legal all> 2647 */ 2648 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 2649 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2650 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2651 2652 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2653 2654 Address (upper 8 bits) of the MSDU buffer OR 2655 MSDU_EXTENSION descriptor OR Link Descriptor 2656 2657 2658 2659 In case of 'NULL' pointer, this field is set to 0 2660 2661 <legal all> 2662 */ 2663 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c 2664 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2665 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2666 2667 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2668 2669 Consumer: WBM 2670 2671 Producer: SW/FW 2672 2673 2674 2675 In case of 'NULL' pointer, this field is set to 0 2676 2677 2678 2679 Indicates to which buffer manager the buffer OR 2680 MSDU_EXTENSION descriptor OR link descriptor that is being 2681 pointed to shall be returned after the frame has been 2682 processed. It is used by WBM for routing purposes. 2683 2684 2685 2686 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2687 to the WMB buffer idle list 2688 2689 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2690 returned to the WMB idle link descriptor idle list 2691 2692 <enum 2 FW_BM> This buffer shall be returned to the FW 2693 2694 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2695 ring 0 2696 2697 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2698 ring 1 2699 2700 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2701 ring 2 2702 2703 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2704 ring 3 2705 2706 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2707 ring 4 2708 2709 2710 2711 <legal all> 2712 */ 2713 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c 2714 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2715 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2716 2717 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2718 2719 Cookie field exclusively used by SW. 2720 2721 2722 2723 In case of 'NULL' pointer, this field is set to 0 2724 2725 2726 2727 HW ignores the contents, accept that it passes the 2728 programmed value on to other descriptors together with the 2729 physical address 2730 2731 2732 2733 Field can be used by SW to for example associate the 2734 buffers physical address with the virtual address 2735 2736 The bit definitions as used by SW are within SW HLD 2737 specification 2738 2739 2740 2741 NOTE: 2742 2743 The three most significant bits can have a special 2744 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2745 STRUCT, and field transmit_bw_restriction is set 2746 2747 2748 2749 In case of NON punctured transmission: 2750 2751 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2752 2753 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2754 2755 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2756 2757 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2758 2759 2760 2761 In case of punctured transmission: 2762 2763 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2764 2765 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2766 2767 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2768 2769 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2770 2771 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2772 2773 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2774 2775 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2776 2777 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2778 2779 2780 2781 Note: a punctured transmission is indicated by the 2782 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2783 TLV 2784 2785 2786 2787 <legal all> 2788 */ 2789 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c 2790 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2791 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2792 2793 2794 #endif // _RX_REO_QUEUE_EXT_H_ 2795