1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RXPCU_PPDU_END_INFO_H_ 25 #define _RXPCU_PPDU_END_INFO_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "phyrx_abort_request_info.h" 30 #include "macrx_abort_request_info.h" 31 32 // ################ START SUMMARY ################# 33 // 34 // Dword Fields 35 // 0 wb_timestamp_lower_32[31:0] 36 // 1 wb_timestamp_upper_32[31:0] 37 // 2 rx_antenna[23:0], tx_ht_vht_ack[24], unsupported_mu_nc[25], otp_txbf_disable[26], previous_tlv_corrupted[27], phyrx_abort_request_info_valid[28], macrx_abort_request_info_valid[29], reserved[31:30] 38 // 3 coex_bt_tx_from_start_of_rx[0], coex_bt_tx_after_start_of_rx[1], coex_wan_tx_from_start_of_rx[2], coex_wan_tx_after_start_of_rx[3], coex_wlan_tx_from_start_of_rx[4], coex_wlan_tx_after_start_of_rx[5], mpdu_delimiter_errors_seen[6], ftm_tm[8:7], dialog_token[16:9], follow_up_dialog_token[24:17], bb_captured_channel[25], bb_captured_reason[28:26], bb_captured_timeout[29], reserved_3[31:30] 39 // 4 before_mpdu_count_passing_fcs[9:0], before_mpdu_count_failing_fcs[19:10], after_mpdu_count_passing_fcs[29:20], reserved_4[31:30] 40 // 5 after_mpdu_count_failing_fcs[9:0], reserved_5[31:10] 41 // 6 phy_timestamp_tx_lower_32[31:0] 42 // 7 phy_timestamp_tx_upper_32[31:0] 43 // 8 bb_length[15:0], bb_data[16], reserved_8[19:17], first_bt_broadcast_status_details[31:20] 44 // 9 rx_ppdu_duration[23:0], reserved_9[31:24] 45 // 10 ast_index[15:0], ast_index_valid[16], reserved_10[19:17], second_bt_broadcast_status_details[31:20] 46 // 11 struct phyrx_abort_request_info phyrx_abort_request_info_details; 47 // 12 struct macrx_abort_request_info macrx_abort_request_info_details; 48 // 13 rx_ppdu_end_marker[31:0] 49 // 50 // ################ END SUMMARY ################# 51 52 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14 53 54 struct rxpcu_ppdu_end_info { 55 uint32_t wb_timestamp_lower_32 : 32; //[31:0] 56 uint32_t wb_timestamp_upper_32 : 32; //[31:0] 57 uint32_t rx_antenna : 24, //[23:0] 58 tx_ht_vht_ack : 1, //[24] 59 unsupported_mu_nc : 1, //[25] 60 otp_txbf_disable : 1, //[26] 61 previous_tlv_corrupted : 1, //[27] 62 phyrx_abort_request_info_valid : 1, //[28] 63 macrx_abort_request_info_valid : 1, //[29] 64 reserved : 2; //[31:30] 65 uint32_t coex_bt_tx_from_start_of_rx : 1, //[0] 66 coex_bt_tx_after_start_of_rx : 1, //[1] 67 coex_wan_tx_from_start_of_rx : 1, //[2] 68 coex_wan_tx_after_start_of_rx : 1, //[3] 69 coex_wlan_tx_from_start_of_rx : 1, //[4] 70 coex_wlan_tx_after_start_of_rx : 1, //[5] 71 mpdu_delimiter_errors_seen : 1, //[6] 72 ftm_tm : 2, //[8:7] 73 dialog_token : 8, //[16:9] 74 follow_up_dialog_token : 8, //[24:17] 75 bb_captured_channel : 1, //[25] 76 bb_captured_reason : 3, //[28:26] 77 bb_captured_timeout : 1, //[29] 78 reserved_3 : 2; //[31:30] 79 uint32_t before_mpdu_count_passing_fcs : 10, //[9:0] 80 before_mpdu_count_failing_fcs : 10, //[19:10] 81 after_mpdu_count_passing_fcs : 10, //[29:20] 82 reserved_4 : 2; //[31:30] 83 uint32_t after_mpdu_count_failing_fcs : 10, //[9:0] 84 reserved_5 : 22; //[31:10] 85 uint32_t phy_timestamp_tx_lower_32 : 32; //[31:0] 86 uint32_t phy_timestamp_tx_upper_32 : 32; //[31:0] 87 uint32_t bb_length : 16, //[15:0] 88 bb_data : 1, //[16] 89 reserved_8 : 3, //[19:17] 90 first_bt_broadcast_status_details: 12; //[31:20] 91 uint32_t rx_ppdu_duration : 24, //[23:0] 92 reserved_9 : 8; //[31:24] 93 uint32_t ast_index : 16, //[15:0] 94 ast_index_valid : 1, //[16] 95 reserved_10 : 3, //[19:17] 96 second_bt_broadcast_status_details: 12; //[31:20] 97 struct phyrx_abort_request_info phyrx_abort_request_info_details; 98 struct macrx_abort_request_info macrx_abort_request_info_details; 99 uint16_t pre_bt_broadcast_status_details : 12, //[27:16] 100 reserved_12a : 4; //[31:28] 101 uint32_t rx_ppdu_end_marker : 32; //[31:0] 102 }; 103 104 /* 105 106 wb_timestamp_lower_32 107 108 WLAN/BT timestamp is a 1 usec resolution timestamp which 109 does not get updated based on receive beacon like TSF. The 110 same rules for capturing tsf_timestamp are used to capture 111 the wb_timestamp. This field represents the lower 32 bits of 112 the 64-bit timestamp 113 114 wb_timestamp_upper_32 115 116 WLAN/BT timestamp is a 1 usec resolution timestamp which 117 does not get updated based on receive beacon like TSF. The 118 same rules for capturing tsf_timestamp are used to capture 119 the wb_timestamp. This field represents the upper 32 bits of 120 the 64-bit timestamp 121 122 rx_antenna 123 124 Receive antenna value ??? 125 126 tx_ht_vht_ack 127 128 Indicates that a HT or VHT Ack/BA frame was transmitted 129 in response to this receive packet. 130 131 unsupported_mu_nc 132 133 Set if MU Nc > 2 in received NDPA. 134 135 If this bit is set, even though AID and BSSID are 136 matched, MAC doesn't send tx_expect_ndp to PHY, because MU 137 Nc > 2 is not supported in Helium. 138 139 otp_txbf_disable 140 141 Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 142 set and if RXPU receives directed NDPA frame. Then, RXPCU 143 should not send TX_EXPECT_NDP TLV to SW but set this bit to 144 inform SW. 145 146 previous_tlv_corrupted 147 148 When set, the TLV preceding this RXPCU_END_INFO TLV 149 within the RX_PPDU_END TLV, is corrupted. Not the entire TLV 150 was received.... Likely due to an abort scenario... If abort 151 is to blame, see the abort data datastructure for details. 152 153 <legal all> 154 155 phyrx_abort_request_info_valid 156 157 When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to 158 RXPCU. The abort fields embedded in this TLV contain valid 159 info. 160 161 <legal all> 162 163 macrx_abort_request_info_valid 164 165 When set, the MAC sent an MACRX_ABORT_REQUEST TLV to 166 PHYRX. The abort fields embedded in this TLV contain valid 167 info. 168 169 <legal all> 170 171 reserved 172 173 <legal 0> 174 175 coex_bt_tx_from_start_of_rx 176 177 Set when BT TX was ongoing when WLAN RX started 178 179 coex_bt_tx_after_start_of_rx 180 181 182 coex_wan_tx_from_start_of_rx 183 184 Set when WAN TX was ongoing when WLAN RX started 185 186 coex_wan_tx_after_start_of_rx 187 188 Set when WAN TX started while WLAN RX was already 189 ongoing 190 191 coex_wlan_tx_from_start_of_rx 192 193 Set when other WLAN TX was ongoing when WLAN RX started 194 195 coex_wlan_tx_after_start_of_rx 196 197 Set when other WLAN TX started while WLAN RX was already 198 ongoing 199 200 mpdu_delimiter_errors_seen 201 202 When set, MPDU delimiter errors have been detected 203 during this PPDU reception 204 205 ftm_tm 206 207 Indicate the timestamp is for the FTM or TM frame 208 209 210 211 0: non TM or FTM frame 212 213 1: FTM frame 214 215 2: TM frame 216 217 3: reserved 218 219 <legal all> 220 221 dialog_token 222 223 The dialog token in the FTM or TM frame. Only valid when 224 the FTM is set. Clear to 254 for a non-FTM frame 225 226 <legal all> 227 228 follow_up_dialog_token 229 230 The follow up dialog token in the FTM or TM frame. Only 231 valid when the FTM is set. Clear to 0 for a non-FTM frame, 232 The follow up dialog token in the FTM frame. Only valid when 233 the FTM is set. Clear to 255 for a non-FTM frame<legal all> 234 235 bb_captured_channel 236 237 Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 238 sent to PHY, FW check it to correlate current PPDU TLVs with 239 uploaded channel information. 240 241 242 243 <legal all> 244 245 bb_captured_reason 246 247 Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL TLV 248 to here for FW usage. Valid when bb_captured_channel or 249 bb_captured_timeout is set. 250 251 252 253 This field indicates why the MAC asked to capture the 254 channel 255 256 <enum 0 freeze_reason_TM> 257 258 <enum 1 freeze_reason_FTM> 259 260 <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 261 262 <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 263 264 <enum 4 freeze_reason_NDPA_NDP> 265 266 <enum 5 freeze_reason_ALL_PACKET> 267 268 269 270 <legal 0-5> 271 272 bb_captured_timeout 273 274 Set by RxPCU to indicate channel capture condition is 275 meet, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY 276 due to AST long delay, which means the rx_frame_falling edge 277 to FREEZE TLV ready time exceed the threshold time defined 278 by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 279 280 Bb_captured_reason is still valid in this case. 281 282 283 284 <legal all> 285 286 reserved_3 287 288 <legal 0> 289 290 before_mpdu_count_passing_fcs 291 292 Number of MPDUs received in this PPDU that passed the 293 FCS check before the Coex TX started 294 295 296 297 The counter saturates at 0x3FF. 298 299 <legal all> 300 301 before_mpdu_count_failing_fcs 302 303 Number of MPDUs received in this PPDU that failed the 304 FCS check before the Coex TX started 305 306 307 308 The counter saturates at 0x3FF. 309 310 <legal all> 311 312 after_mpdu_count_passing_fcs 313 314 Number of MPDUs received in this PPDU that passed the 315 FCS check after the moment the Coex TX started 316 317 318 319 (Note: The partially received MPDU when the COEX tx 320 start event came in falls in the after category) 321 322 323 324 The counter saturates at 0x3FF. 325 326 <legal all> 327 328 reserved_4 329 330 <legal 0> 331 332 after_mpdu_count_failing_fcs 333 334 Number of MPDUs received in this PPDU that failed the 335 FCS check after the moment the Coex TX started 336 337 338 339 (Note: The partially received MPDU when the COEX tx 340 start event came in falls in the after category) 341 342 343 344 The counter saturates at 0x3FF. 345 346 <legal all> 347 348 reserved_5 349 350 <legal 0> 351 352 phy_timestamp_tx_lower_32 353 354 The PHY timestamp in the AMPI of the most recent rising 355 edge (TODO: of what ???) after the TX_PHY_DESC. This field 356 indicates the lower 32 bits of the timestamp 357 358 phy_timestamp_tx_upper_32 359 360 The PHY timestamp in the AMPI of the most recent rising 361 edge (TODO: of what ???) after the TX_PHY_DESC. This field 362 indicates the upper 32 bits of the timestamp 363 364 bb_length 365 366 Indicates the number of bytes of baseband information 367 for PPDUs where the BB descriptor preamble type is 0x80 to 368 0xFF which indicates that this is not a normal PPDU but 369 rather contains baseband debug information. 370 371 TODO: Is this still needed ??? 372 373 bb_data 374 375 Indicates that BB data associated with this PPDU will 376 exist in the receive buffer. The exact contents of this BB 377 data can be found by decoding the BB TLV in the buffer 378 associated with the BB data. See vector_fragment in the 379 Helium_mac_phy_interface.docx 380 381 reserved_8 382 383 Reserved: HW should fill with 0, FW should ignore. 384 385 first_bt_broadcast_status_details 386 387 Same contents as field bt_broadcast_status_details for 388 the first received COEX_STATUS_BROADCAST tlv during this 389 PPDU reception. 390 391 392 393 If no COEX_STATUS_BROADCAST tlv is received during this 394 PPDU reception, this field will be set to 0 395 396 397 398 399 400 For detailed info see doc: TBD 401 402 <legal all> 403 404 rx_ppdu_duration 405 406 The length of this PPDU reception in us 407 408 reserved_9 409 410 <legal 0> 411 412 ast_index 413 414 The AST index of the receive Ack/BA. This information 415 is provided from the TXPCU to the RXPCU for receive Ack/BA 416 for implicit beamforming. 417 418 <legal all> 419 420 ast_index_valid 421 422 Indicates that ast_index is valid. Should only be set 423 for receive Ack/BA where single stream implicit sounding is 424 captured. 425 426 reserved_10 427 428 <legal 0> 429 430 second_bt_broadcast_status_details 431 432 Same contents as field bt_broadcast_status_details for 433 the second received COEX_STATUS_BROADCAST tlv during this 434 PPDU reception. 435 436 437 438 If no second COEX_STATUS_BROADCAST tlv is received 439 during this PPDU reception, this field will be set to 0 440 441 442 443 444 445 For detailed info see doc: TBD 446 447 <legal all> 448 449 struct phyrx_abort_request_info phyrx_abort_request_info_details 450 451 Field only valid when Phyrx_abort_request_info_valid is 452 set 453 454 The reason why PHY generated an abort request 455 456 struct macrx_abort_request_info macrx_abort_request_info_details 457 458 Field only valid when macrx_abort_request_info_valid is 459 set 460 461 The reason why MACRX generated an abort request 462 463 rx_ppdu_end_marker 464 465 Field used by SW to double check that their structure 466 alignment is in sync with what HW has done. 467 468 <legal 0xAABBCCDD> 469 */ 470 471 472 /* Description RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32 473 474 WLAN/BT timestamp is a 1 usec resolution timestamp which 475 does not get updated based on receive beacon like TSF. The 476 same rules for capturing tsf_timestamp are used to capture 477 the wb_timestamp. This field represents the lower 32 bits of 478 the 64-bit timestamp 479 */ 480 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 481 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0 482 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff 483 484 /* Description RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32 485 486 WLAN/BT timestamp is a 1 usec resolution timestamp which 487 does not get updated based on receive beacon like TSF. The 488 same rules for capturing tsf_timestamp are used to capture 489 the wb_timestamp. This field represents the upper 32 bits of 490 the 64-bit timestamp 491 */ 492 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 493 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0 494 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff 495 496 /* Description RXPCU_PPDU_END_INFO_2_RX_ANTENNA 497 498 Receive antenna value ??? 499 */ 500 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008 501 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0 502 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff 503 504 /* Description RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK 505 506 Indicates that a HT or VHT Ack/BA frame was transmitted 507 in response to this receive packet. 508 */ 509 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008 510 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24 511 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000 512 513 /* Description RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC 514 515 Set if MU Nc > 2 in received NDPA. 516 517 If this bit is set, even though AID and BSSID are 518 matched, MAC doesn't send tx_expect_ndp to PHY, because MU 519 Nc > 2 is not supported in Helium. 520 */ 521 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008 522 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25 523 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000 524 525 /* Description RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE 526 527 Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 528 set and if RXPU receives directed NDPA frame. Then, RXPCU 529 should not send TX_EXPECT_NDP TLV to SW but set this bit to 530 inform SW. 531 */ 532 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008 533 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26 534 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000 535 536 /* Description RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED 537 538 When set, the TLV preceding this RXPCU_END_INFO TLV 539 within the RX_PPDU_END TLV, is corrupted. Not the entire TLV 540 was received.... Likely due to an abort scenario... If abort 541 is to blame, see the abort data datastructure for details. 542 543 <legal all> 544 */ 545 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 546 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27 547 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 548 549 /* Description RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID 550 551 When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to 552 RXPCU. The abort fields embedded in this TLV contain valid 553 info. 554 555 <legal all> 556 */ 557 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 558 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 559 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 560 561 /* Description RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID 562 563 When set, the MAC sent an MACRX_ABORT_REQUEST TLV to 564 PHYRX. The abort fields embedded in this TLV contain valid 565 info. 566 567 <legal all> 568 */ 569 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 570 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 571 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 572 573 /* Description RXPCU_PPDU_END_INFO_2_RESERVED 574 575 <legal 0> 576 */ 577 #define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008 578 #define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30 579 #define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000 580 581 /* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX 582 583 Set when BT TX was ongoing when WLAN RX started 584 */ 585 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c 586 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0 587 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 588 589 /* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX 590 591 */ 592 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 593 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 594 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 595 596 /* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX 597 598 Set when WAN TX was ongoing when WLAN RX started 599 */ 600 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 601 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 602 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 603 604 /* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX 605 606 Set when WAN TX started while WLAN RX was already 607 ongoing 608 */ 609 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 610 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 611 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 612 613 /* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX 614 615 Set when other WLAN TX was ongoing when WLAN RX started 616 */ 617 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 618 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 619 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 620 621 /* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX 622 623 Set when other WLAN TX started while WLAN RX was already 624 ongoing 625 */ 626 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 627 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 628 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 629 630 /* Description RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN 631 632 When set, MPDU delimiter errors have been detected 633 during this PPDU reception 634 */ 635 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c 636 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 637 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 638 639 /* Description RXPCU_PPDU_END_INFO_3_FTM_TM 640 641 Indicate the timestamp is for the FTM or TM frame 642 643 644 645 0: non TM or FTM frame 646 647 1: FTM frame 648 649 2: TM frame 650 651 3: reserved 652 653 <legal all> 654 */ 655 #define RXPCU_PPDU_END_INFO_3_FTM_TM_OFFSET 0x0000000c 656 #define RXPCU_PPDU_END_INFO_3_FTM_TM_LSB 7 657 #define RXPCU_PPDU_END_INFO_3_FTM_TM_MASK 0x00000180 658 659 /* Description RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN 660 661 The dialog token in the FTM or TM frame. Only valid when 662 the FTM is set. Clear to 254 for a non-FTM frame 663 664 <legal all> 665 */ 666 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c 667 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9 668 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00 669 670 /* Description RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN 671 672 The follow up dialog token in the FTM or TM frame. Only 673 valid when the FTM is set. Clear to 0 for a non-FTM frame, 674 The follow up dialog token in the FTM frame. Only valid when 675 the FTM is set. Clear to 255 for a non-FTM frame<legal all> 676 */ 677 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c 678 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17 679 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 680 681 /* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL 682 683 Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 684 sent to PHY, FW check it to correlate current PPDU TLVs with 685 uploaded channel information. 686 687 688 689 <legal all> 690 */ 691 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c 692 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25 693 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000 694 695 /* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON 696 697 Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL TLV 698 to here for FW usage. Valid when bb_captured_channel or 699 bb_captured_timeout is set. 700 701 702 703 This field indicates why the MAC asked to capture the 704 channel 705 706 <enum 0 freeze_reason_TM> 707 708 <enum 1 freeze_reason_FTM> 709 710 <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 711 712 <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 713 714 <enum 4 freeze_reason_NDPA_NDP> 715 716 <enum 5 freeze_reason_ALL_PACKET> 717 718 719 720 <legal 0-5> 721 */ 722 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c 723 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26 724 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000 725 726 /* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT 727 728 Set by RxPCU to indicate channel capture condition is 729 meet, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY 730 due to AST long delay, which means the rx_frame_falling edge 731 to FREEZE TLV ready time exceed the threshold time defined 732 by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 733 734 Bb_captured_reason is still valid in this case. 735 736 737 738 <legal all> 739 */ 740 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c 741 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29 742 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000 743 744 /* Description RXPCU_PPDU_END_INFO_3_RESERVED_3 745 746 <legal 0> 747 */ 748 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c 749 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30 750 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000 751 752 /* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS 753 754 Number of MPDUs received in this PPDU that passed the 755 FCS check before the Coex TX started 756 757 758 759 The counter saturates at 0x3FF. 760 761 <legal all> 762 */ 763 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 764 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 765 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff 766 767 /* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS 768 769 Number of MPDUs received in this PPDU that failed the 770 FCS check before the Coex TX started 771 772 773 774 The counter saturates at 0x3FF. 775 776 <legal all> 777 */ 778 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 779 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 780 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 781 782 /* Description RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS 783 784 Number of MPDUs received in this PPDU that passed the 785 FCS check after the moment the Coex TX started 786 787 788 789 (Note: The partially received MPDU when the COEX tx 790 start event came in falls in the after category) 791 792 793 794 The counter saturates at 0x3FF. 795 796 <legal all> 797 */ 798 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 799 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 800 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 801 802 /* Description RXPCU_PPDU_END_INFO_4_RESERVED_4 803 804 <legal 0> 805 */ 806 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010 807 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30 808 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000 809 810 /* Description RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS 811 812 Number of MPDUs received in this PPDU that failed the 813 FCS check after the moment the Coex TX started 814 815 816 817 (Note: The partially received MPDU when the COEX tx 818 start event came in falls in the after category) 819 820 821 822 The counter saturates at 0x3FF. 823 824 <legal all> 825 */ 826 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 827 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 828 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff 829 830 /* Description RXPCU_PPDU_END_INFO_5_RESERVED_5 831 832 <legal 0> 833 */ 834 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014 835 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10 836 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00 837 838 /* Description RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32 839 840 The PHY timestamp in the AMPI of the most recent rising 841 edge (TODO: of what ???) after the TX_PHY_DESC. This field 842 indicates the lower 32 bits of the timestamp 843 */ 844 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 845 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 846 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff 847 848 /* Description RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32 849 850 The PHY timestamp in the AMPI of the most recent rising 851 edge (TODO: of what ???) after the TX_PHY_DESC. This field 852 indicates the upper 32 bits of the timestamp 853 */ 854 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c 855 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 856 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff 857 858 /* Description RXPCU_PPDU_END_INFO_8_BB_LENGTH 859 860 Indicates the number of bytes of baseband information 861 for PPDUs where the BB descriptor preamble type is 0x80 to 862 0xFF which indicates that this is not a normal PPDU but 863 rather contains baseband debug information. 864 865 TODO: Is this still needed ??? 866 */ 867 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020 868 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0 869 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff 870 871 /* Description RXPCU_PPDU_END_INFO_8_BB_DATA 872 873 Indicates that BB data associated with this PPDU will 874 exist in the receive buffer. The exact contents of this BB 875 data can be found by decoding the BB TLV in the buffer 876 associated with the BB data. See vector_fragment in the 877 Helium_mac_phy_interface.docx 878 */ 879 #define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020 880 #define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16 881 #define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000 882 883 /* Description RXPCU_PPDU_END_INFO_8_RESERVED_8 884 885 Reserved: HW should fill with 0, FW should ignore. 886 */ 887 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020 888 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17 889 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000 890 891 /* Description RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS 892 893 Same contents as field bt_broadcast_status_details for 894 the first received COEX_STATUS_BROADCAST tlv during this 895 PPDU reception. 896 897 898 899 If no COEX_STATUS_BROADCAST tlv is received during this 900 PPDU reception, this field will be set to 0 901 902 903 904 905 906 For detailed info see doc: TBD 907 908 <legal all> 909 */ 910 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 911 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 912 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 913 914 /* Description RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION 915 916 The length of this PPDU reception in us 917 */ 918 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024 919 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0 920 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff 921 922 /* Description RXPCU_PPDU_END_INFO_9_RESERVED_9 923 924 <legal 0> 925 */ 926 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024 927 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24 928 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000 929 930 /* Description RXPCU_PPDU_END_INFO_10_AST_INDEX 931 932 The AST index of the receive Ack/BA. This information 933 is provided from the TXPCU to the RXPCU for receive Ack/BA 934 for implicit beamforming. 935 936 <legal all> 937 */ 938 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028 939 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0 940 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff 941 942 /* Description RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID 943 944 Indicates that ast_index is valid. Should only be set 945 for receive Ack/BA where single stream implicit sounding is 946 captured. 947 */ 948 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028 949 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16 950 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000 951 952 /* Description RXPCU_PPDU_END_INFO_10_RESERVED_10 953 954 <legal 0> 955 */ 956 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028 957 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17 958 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000 959 960 /* Description RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS 961 962 Same contents as field bt_broadcast_status_details for 963 the second received COEX_STATUS_BROADCAST tlv during this 964 PPDU reception. 965 966 967 968 If no second COEX_STATUS_BROADCAST tlv is received 969 during this PPDU reception, this field will be set to 0 970 971 972 973 974 975 For detailed info see doc: TBD 976 977 <legal all> 978 */ 979 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 980 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 981 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 982 983 /* EXTERNAL REFERENCE : struct phyrx_abort_request_info phyrx_abort_request_info_details */ 984 985 986 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON 987 988 <enum 0 phyrx_err_phy_off> Reception aborted due to 989 receiving a PHY_OFF TLV 990 991 <enum 1 phyrx_err_synth_off> 992 993 <enum 2 phyrx_err_ofdma_timing> 994 995 <enum 3 phyrx_err_ofdma_signal_parity> 996 997 <enum 4 phyrx_err_ofdma_rate_illegal> 998 999 <enum 5 phyrx_err_ofdma_length_illegal> 1000 1001 <enum 6 phyrx_err_ofdma_restart> 1002 1003 <enum 7 phyrx_err_ofdma_service> 1004 1005 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 1006 1007 1008 1009 <enum 9 phyrx_err_cck_blokker> 1010 1011 <enum 10 phyrx_err_cck_timing> 1012 1013 <enum 11 phyrx_err_cck_header_crc> 1014 1015 <enum 12 phyrx_err_cck_rate_illegal> 1016 1017 <enum 13 phyrx_err_cck_length_illegal> 1018 1019 <enum 14 phyrx_err_cck_restart> 1020 1021 <enum 15 phyrx_err_cck_service> 1022 1023 <enum 16 phyrx_err_cck_power_drop> 1024 1025 1026 1027 <enum 17 phyrx_err_ht_crc_err> 1028 1029 <enum 18 phyrx_err_ht_length_illegal> 1030 1031 <enum 19 phyrx_err_ht_rate_illegal> 1032 1033 <enum 20 phyrx_err_ht_zlf> 1034 1035 <enum 21 phyrx_err_false_radar_ext> 1036 1037 1038 1039 <enum 22 phyrx_err_green_field> 1040 1041 1042 1043 <enum 23 phyrx_err_bw_gt_dyn_bw> 1044 1045 <enum 24 phyrx_err_leg_ht_mismatch> 1046 1047 <enum 25 phyrx_err_vht_crc_error> 1048 1049 <enum 26 phyrx_err_vht_siga_unsupported> 1050 1051 <enum 27 phyrx_err_vht_lsig_len_invalid> 1052 1053 <enum 28 phyrx_err_vht_ndp_or_zlf> 1054 1055 <enum 29 phyrx_err_vht_nsym_lt_zero> 1056 1057 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 1058 1059 <enum 31 phyrx_err_vht_rx_skip_group_id0> 1060 1061 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 1062 1063 <enum 33 phyrx_err_vht_rx_skip_group_id63> 1064 1065 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 1066 1067 <enum 35 phyrx_err_defer_nap> 1068 1069 <enum 36 phyrx_err_fdomain_timeout> 1070 1071 <enum 37 phyrx_err_lsig_rel_check> 1072 1073 <enum 38 phyrx_err_bt_collision> 1074 1075 <enum 39 phyrx_err_unsupported_mu_feedback> 1076 1077 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 1078 1079 <enum 41 phyrx_err_unsupported_cbf> 1080 1081 1082 1083 <enum 42 phyrx_err_other> Should not really be used. If 1084 needed, ask for documentation update 1085 1086 1087 1088 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 1089 phyrx_err_he_crc_error > <enum 45 1090 phyrx_err_he_sigb_unsupported > <enum 46 1091 phyrx_err_he_mu_mode_unsupported > <enum 47 1092 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 1093 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 1094 phyrx_err_he_num_users_unsupported ><enum 51 1095 phyrx_err_he_sounding_params_unsupported > 1096 1097 1098 1099 <enum 52 phyrx_err_MU_UL_no_power_detected> 1100 1101 <enum 53 phyrx_err_MU_UL_not_for_me> 1102 1103 1104 1105 <legal 0 - 53> 1106 */ 1107 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c 1108 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 1109 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff 1110 1111 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE 1112 1113 When set, PHY enters PHY NAP state after sending this 1114 abort 1115 1116 1117 1118 Note that nap and defer state are mutually exclusive. 1119 1120 1121 1122 Field put pro-actively in place....usage still to be 1123 agreed upon. 1124 1125 <legal all> 1126 */ 1127 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c 1128 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 1129 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 1130 1131 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE 1132 1133 When set, PHY enters PHY defer state after sending this 1134 abort 1135 1136 1137 1138 Note that nap and defer state are mutually exclusive. 1139 1140 1141 1142 Field put pro-actively in place....usage still to be 1143 agreed upon. 1144 1145 <legal all> 1146 */ 1147 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c 1148 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 1149 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 1150 1151 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0 1152 1153 <legal 0> 1154 */ 1155 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c 1156 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10 1157 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00 1158 1159 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION 1160 1161 The remaining receive duration of this PPDU in the 1162 medium (in us). When PHY does not know this duration when 1163 this TLV is generated, the field will be set to 0. 1164 1165 The timing reference point is the reception by the MAC 1166 of this TLV. The value shall be accurate to within 2us. 1167 1168 1169 1170 In case Phy_enters_nap_state and/or 1171 Phy_enters_defer_state is set, there is a possibility that 1172 MAC PMM can also decide to go into a low(er) power state. 1173 1174 <legal all> 1175 */ 1176 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c 1177 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 1178 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 1179 1180 /* EXTERNAL REFERENCE : struct macrx_abort_request_info macrx_abort_request_info_details */ 1181 1182 1183 /* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON 1184 1185 <enum 0 macrx_abort_sw_initiated> 1186 1187 <enum 1 macrx_abort_obss_reception> Upon receiving this 1188 abort reason, PHY should stop reception of the current frame 1189 and go back into a search mode 1190 1191 <enum 2 macrx_abort_other> 1192 1193 <enum 3 macrx_abort_sw_initiated_channel_switch > MAC FW 1194 issued an abort for channel switch reasons 1195 1196 <enum 4 macrx_abort_sw_initiated_power_save > MAC FW 1197 issued an abort power save reasons 1198 1199 <enum 5 macrx_abort_too_much_bad_data > RXPCU is 1200 terminating the current ongoing reception, as the data that 1201 MAC is receiving seems to be all garbage... The PER is too 1202 high, or in case of MU UL, Likely the trigger frame never 1203 got properly received by any of the targeted MU UL devices. 1204 After the abort, PHYRX can resume a normal search mode. 1205 1206 1207 1208 <legal 0-5> 1209 */ 1210 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 1211 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 1212 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff 1213 1214 /* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0 1215 1216 <legal 0> 1217 */ 1218 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 1219 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 1220 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 1221 1222 /* Description RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER 1223 1224 Field used by SW to double check that their structure 1225 alignment is in sync with what HW has done. 1226 1227 <legal 0xAABBCCDD> 1228 */ 1229 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034 1230 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0 1231 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff 1232 1233 1234 #endif // _RXPCU_PPDU_END_INFO_H_ 1235